CN110651331B - 用于存储器的坏位寄存器 - Google Patents

用于存储器的坏位寄存器 Download PDF

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Publication number
CN110651331B
CN110651331B CN201880033345.3A CN201880033345A CN110651331B CN 110651331 B CN110651331 B CN 110651331B CN 201880033345 A CN201880033345 A CN 201880033345A CN 110651331 B CN110651331 B CN 110651331B
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China
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bad
bit
register
bit register
address
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Chinese (zh)
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CN110651331A (zh
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D.沃利奇
J.K.德布罗斯
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1677—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/06—Acceleration testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Probability & Statistics with Applications (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Memory System (AREA)
CN201880033345.3A 2017-06-22 2018-06-11 用于存储器的坏位寄存器 Active CN110651331B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/630,538 US10394647B2 (en) 2017-06-22 2017-06-22 Bad bit register for memory
US15/630,538 2017-06-22
PCT/IB2018/054195 WO2018234920A1 (en) 2017-06-22 2018-06-11 Bad bit register for memory

Publications (2)

Publication Number Publication Date
CN110651331A CN110651331A (zh) 2020-01-03
CN110651331B true CN110651331B (zh) 2023-05-12

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US (2) US10394647B2 (https=)
JP (1) JP7116376B2 (https=)
CN (1) CN110651331B (https=)
DE (1) DE112018002029T5 (https=)
GB (1) GB2577659B (https=)
WO (1) WO2018234920A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11696297B2 (en) * 2019-11-08 2023-07-04 Qualcomm Incorporated Techniques for release validation of uplink configured grant and semi-persistent scheduling

Citations (6)

* Cited by examiner, † Cited by third party
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US3588830A (en) * 1968-01-17 1971-06-28 Ibm System for using a memory having irremediable bad bits
JP2002133894A (ja) * 2000-10-30 2002-05-10 Toshiba Corp 不揮発性半導体記憶装置
CN101996689A (zh) * 2009-08-12 2011-03-30 台湾积体电路制造股份有限公司 存储器错误处理方法
CN102541667A (zh) * 2010-09-21 2012-07-04 国际商业机器公司 用散列函数区分存储系统中随机和重复差错的方法和系统
CN104094237A (zh) * 2011-12-08 2014-10-08 桑迪士克科技股份有限公司 存储器设备中的增强的错误校正
CN106462480A (zh) * 2014-06-30 2017-02-22 英特尔公司 用于处理持久存储器中的错误的技术

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JPH06242925A (ja) 1993-02-15 1994-09-02 Mitsubishi Electric Corp ソート処理装置
US5475693A (en) 1994-12-27 1995-12-12 Intel Corporation Error management processes for flash EEPROM memory arrays
US5687353A (en) 1995-03-03 1997-11-11 Hal Computer Systems, Inc. Merging data using a merge code from a look-up table and performing ECC generation on the merged data
JPH11175409A (ja) * 1997-12-05 1999-07-02 Nec Corp メモリ制御方式
US6868022B2 (en) * 2003-03-28 2005-03-15 Matrix Semiconductor, Inc. Redundant memory structure using bad bit pointers
JP4722839B2 (ja) * 2004-05-19 2011-07-13 パナソニック株式会社 メモリ制御回路、不揮発性記憶装置及びメモリ制御方法
KR100626391B1 (ko) * 2005-04-01 2006-09-20 삼성전자주식회사 원낸드 플래시 메모리 및 그것을 포함한 데이터 처리시스템
US8595573B2 (en) 2006-12-03 2013-11-26 Apple Inc. Automatic defect management in memory devices
US7861138B2 (en) * 2006-12-05 2010-12-28 Qimonda Ag Error correction in memory devices
US20080181035A1 (en) * 2007-01-26 2008-07-31 Atsushi Kawasumi Method and system for a dynamically repairable memory
JP5292706B2 (ja) * 2007-02-28 2013-09-18 富士通セミコンダクター株式会社 コンピュータシステム
JP2009158018A (ja) * 2007-12-27 2009-07-16 Toshiba Corp 不揮発性半導体記憶装置
TWI416523B (zh) * 2009-06-10 2013-11-21 Silicon Motion Inc 非揮發性記憶體之寫入錯誤管理方法、非揮發性記憶體、記憶卡、以及非揮發性記憶體之控制器
CN102592680B (zh) 2011-01-12 2015-04-08 北京兆易创新科技股份有限公司 一种存储芯片的修复装置和方法
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US3588830A (en) * 1968-01-17 1971-06-28 Ibm System for using a memory having irremediable bad bits
JP2002133894A (ja) * 2000-10-30 2002-05-10 Toshiba Corp 不揮発性半導体記憶装置
CN101996689A (zh) * 2009-08-12 2011-03-30 台湾积体电路制造股份有限公司 存储器错误处理方法
CN102541667A (zh) * 2010-09-21 2012-07-04 国际商业机器公司 用散列函数区分存储系统中随机和重复差错的方法和系统
CN104094237A (zh) * 2011-12-08 2014-10-08 桑迪士克科技股份有限公司 存储器设备中的增强的错误校正
CN106462480A (zh) * 2014-06-30 2017-02-22 英特尔公司 用于处理持久存储器中的错误的技术

Also Published As

Publication number Publication date
US20180373589A1 (en) 2018-12-27
US10394647B2 (en) 2019-08-27
US20180373588A1 (en) 2018-12-27
GB2577659B (en) 2020-08-26
JP2020524871A (ja) 2020-08-20
WO2018234920A1 (en) 2018-12-27
US10437665B2 (en) 2019-10-08
DE112018002029T5 (de) 2020-01-09
GB2577659A (en) 2020-04-01
JP7116376B2 (ja) 2022-08-10
CN110651331A (zh) 2020-01-03
GB202000334D0 (en) 2020-02-26

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