CN110648714A - Data reading method and device, electronic equipment and storage medium - Google Patents
Data reading method and device, electronic equipment and storage medium Download PDFInfo
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- CN110648714A CN110648714A CN201810669080.8A CN201810669080A CN110648714A CN 110648714 A CN110648714 A CN 110648714A CN 201810669080 A CN201810669080 A CN 201810669080A CN 110648714 A CN110648714 A CN 110648714A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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Abstract
The embodiment of the invention discloses a data reading method and device, electronic equipment and a storage medium. The method comprises the following steps: after the bit line charging end corresponding to the selected word line is charged to the reading working voltage, applying the reading voltage of a first set time to the grids of the selected word line and the unselected word line; screening an erasing state bit line from the bit lines according to the current voltage of the charging end of the bit line, and determining that the data stored in the storage unit corresponding to the erasing state bit line is 1; charging the charging ends of the bit lines to be determined except the bit line in the erasing state in the bit lines to a reading working voltage, and applying a reading voltage of a second set time to the gates of the selected word line and the unselected word line after the charging ends of the bit lines in the erasing state are not charged; and determining the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging end of the bit line to be determined. The technical scheme of the embodiment of the invention realizes the reduction of the power consumption of the read data of the memory and improves the accuracy of the read data of the memory.
Description
Technical Field
The embodiment of the invention relates to the technical field of data reading of memories, in particular to a data reading method and device, electronic equipment and a storage medium.
Background
The Nand-flash memory is one of flash memories, has the advantages of large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is widely applied in the industry, for example, embedded products comprise a digital camera, an MP3 walkman memory card, a small-sized U-disk and the like.
In the prior art, when a Nand-flash memory performs a data reading operation, voltages of all bit lines are generally charged first, after the charging is completed, corresponding operating voltages are applied to gates of selected word lines and gates of unselected word lines at the same time, and after the operating voltages are applied for a period of time (for example, 20 microseconds), voltage values of the bit lines are read to determine what data needs to be read.
In the process of implementing the invention, the inventor finds that the prior art has the following defects: during reading data, the bit lines in the erased state generate a large current, which not only increases the power consumption of the memory, but also may cause errors in reading data from the respective bit lines in the erased state.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for reading data, an electronic device, and a storage medium, so as to optimize an existing method for reading data from a memory.
In a first aspect, an embodiment of the present invention provides a data reading method, including:
after charging the charging end of each bit line corresponding to the selected word line to the reading working voltage, applying the reading voltage corresponding to the first set time to the grid of the selected word line and the grid of the unselected word line;
screening an erased bit line from the bit lines according to the current voltage of the charging end of each bit line, and determining that the data stored in the storage unit corresponding to the erased bit line is 1;
charging the charging end of the bit line to be determined except the bit line in the erasing state in each bit line to the reading working voltage again, and applying the reading voltages corresponding to the second set time to the grid of the selected word line and the grid of the unselected word line after not charging the charging end of the bit line in the erasing state;
and determining the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging end of the bit line to be determined.
In the above method, optionally, the first set time is less than the second set time.
In the foregoing method, optionally, the screening the bit lines in the erased state from the bit lines according to the current voltage of the charging terminal of the bit line includes:
and if the current voltage of the charging end is less than the set voltage threshold, determining that the bit line corresponding to the charging end is the bit line in the erasing state.
In the foregoing method, optionally, the determining, according to the current voltage of the charging terminal of the bit line to be determined, data stored in a memory cell corresponding to the bit line to be determined includes:
if the current voltage of the charging end of the bit line to be determined is 0V, determining that the data stored in the storage unit corresponding to the bit line to be determined is 1;
and if the current voltage of the charging end of the bit line to be determined is greater than 0V, determining that the data stored in the storage unit corresponding to the bit line to be determined is 0.
In a second aspect, an embodiment of the present invention provides an apparatus for reading data, including:
the first voltage applying module is used for applying reading voltages corresponding to a first set time to the grid of the selected word line and the grid of the unselected word line after the charging ends of the bit lines corresponding to the selected word line are charged to the reading working voltage;
the erasing state bit line determining module is used for screening the erasing state bit lines from the bit lines according to the current voltage of the charging end of each bit line and determining that the data stored in the storage unit corresponding to the erasing state bit line is 1;
a second voltage applying module, configured to charge the charging end of the bit line to be determined in each bit line except the bit line in the erase state to the read working voltage again, and apply, after the charging end of the bit line in the erase state is not charged, the read voltages corresponding to the gates of the selected word line and the gates of the unselected word lines for a second set time;
and the storage data determining module is used for determining the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging end of the bit line to be determined.
In the above apparatus, optionally, the first set time is less than the second set time.
In the foregoing device, optionally, the erase state bit line determining module is specifically configured to:
and if the current voltage of the charging end is less than the set voltage threshold, determining that the bit line corresponding to the charging end is the bit line in the erasing state.
In the above apparatus, optionally, the stored data determining module includes:
the first data determining unit is used for determining that the data stored in the storage unit corresponding to the bit line to be determined is 1 if the current voltage of the charging end of the bit line to be determined is 0V;
and the second data determination unit is used for determining that the data stored in the storage unit corresponding to the bit line to be determined is 0 if the current voltage of the charging end of the bit line to be determined is greater than 0V.
In a third aspect, an embodiment of the present invention provides an electronic device, including:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement a method according to any one of the embodiments of the invention.
In a fourth aspect, embodiments of the present invention provide a storage medium containing computer-executable instructions for performing a method according to any one of the embodiments of the present invention when executed by a computer processor.
The embodiment of the invention provides a data reading method, a data reading device, electronic equipment and a storage medium, wherein a data reading process is divided into two data reading processes with different time lengths, most of bit lines in an erasing state are screened out in the first data reading process through a short first set time, and conventional data reading is performed on the rest of the bit lines for a second set time in the second data reading process, so that the technical defects that in the prior art, a memory is high in power consumption and easy to have data reading errors in the data reading process are overcome, the data reading power consumption of the memory is reduced, and the data reading accuracy of the memory is improved.
Drawings
Fig. 1 is a flowchart of a data reading method according to an embodiment of the present invention;
fig. 2 is a flowchart of a data reading method according to a second embodiment of the present invention;
fig. 3 is a structural diagram of a data reading apparatus according to a third embodiment of the present invention;
fig. 4 is a structural diagram of an electronic device according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a flowchart of a data reading method according to an embodiment of the present invention, where the method of this embodiment may be executed by a data reading apparatus, and the apparatus may be implemented by hardware and/or software, and may be generally integrated in a memory, such as a Nand-flash memory. The method of the embodiment specifically includes:
s110, after charging the charging terminals of the bit lines corresponding to the selected word line to the read operating voltage, applying the read voltages corresponding to the gates of the selected word line and the gates of the unselected word lines for the first set time.
It can be understood that, when the memory reads the stored data corresponding to a certain word line, all bit lines corresponding to the certain word line are first charged, that is, the drain voltages of all field effect transistors in the drain-gated switched word line corresponding to the certain word line are raised to a certain voltage (for example, a voltage of 1.8V), so that after the read voltage is applied to the gate of the selected word line and the gate of the unselected word line, the stored data corresponding to the certain word line is determined according to the voltage value after the discharge of the drain voltages.
Therefore, in this embodiment, it is also necessary to charge the charging terminals of the bit lines corresponding to the selected word line (i.e., the drains of all the fets in the drain-gated word line corresponding to the selected word line) to the read operating voltage. The read operation voltage is a voltage that the charging terminal of each bit line should reach when the memory performs a data reading operation.
Further, in this embodiment, after the charging terminals of the bit lines corresponding to the selected word line are charged to the read operating voltage, the corresponding read voltages for the first set time are applied to the gates of the selected word line and the gates of the unselected word lines. For example, when the memory is operated to read data, a voltage of about 0.5V is applied to the gate of the selected word line, and a voltage of about 8V is applied to the gate of the unselected word line. The first setting time is a relatively short time compared with a time (for example, 20 microseconds) for applying the read voltage to the selected word line and the unselected word line simultaneously in the memory in the prior art, so that power consumption generated in the first data reading process in the step is as small as possible, and the total power consumption for reading data by the memory is reduced. The first set time may typically be 2 microseconds or the like.
It can be understood that, in the process of reading data, after the charging terminals of the bit lines are charged completely and the read voltages are applied to the gates of the selected word line and the non-selected word line, the floating gate fet corresponding to the selected word line with the stored data "1" should be in a conducting state. At this time, the bit line corresponding to the floating gate fet in the on state generates a large current (e.g., 500 microamperes), and the large current not only increases the power consumption of the memory, but also causes a plurality of bit lines to simultaneously generate a large current when the data stored in the floating gate fet corresponding to the selected word line is all "1", thereby causing the voltage of the charging terminal of the bit line corresponding to the floating gate fet partially storing data "1" to be raised, and the memory is prone to have a situation of data reading error, and misreads "1" as "0".
Therefore, in the present embodiment, the data reading operation is completed twice, and the reading voltage is applied to the gates of the selected word line and the non-selected word line for the first set time only for the first time. Through the discharging operation in the first set time, for the floating gate field effect transistor with a better erasing effect, the voltage of the charging end of the bit line corresponding to the floating gate field effect transistor can be discharged to 0V, and then after the first set time, most of the bit lines with the data of '1' stored in the corresponding floating gate field effect transistor can be screened out according to the current voltage of the charging end of each bit line. Because the first set time is shorter, not only the power consumption in the process of reading data for the first time is smaller, but also the adverse effect of large current on the voltage of the bit line charging terminal is weakened.
S120, screening the bit lines in the erasing state from the bit lines according to the current voltage of the charging end of each bit line, and determining that the data stored in the storage unit corresponding to the bit line in the erasing state is 1.
In this embodiment, after the discharging operation is performed on the charging terminal of each bit line for the first set time, most bit lines with "1" stored in the corresponding floating gate field effect transistor, i.e. the erased bit lines, are selected according to the current voltage of the charging terminal of each bit line. For example, when the current voltage of the charging terminal is 0V or less than the set voltage threshold, the bit line is determined to be the erased bit line.
It is understood that the floating gate fet in the memory device will have a portion of electrons residing in the floating gate or tunnel oxide layer during repeated data writing, data reading, and data erasing operations, and these electrons will raise the threshold of the floating gate fet. If the threshold of the floating gate fet is raised, when the data stored in the floating gate fet is "1", the discharge speed of the bit line where the floating gate fet is located will be slowed down during the process of reading the data, and the voltage at the charging terminal of the bit line may not be discharged to 0V within the first set time. Therefore, in order to further reduce the power consumption during the second reading of the data in step 130, a voltage threshold (e.g., 0.2V) may be set, and the bit line whose charged terminal voltage is less than the voltage threshold after the discharging in step 110 is also determined as the erased bit line.
And S130, charging the charging ends of the bit lines to be determined except the bit line in the erasing state in each bit line to the reading working voltage again, and applying the reading voltages corresponding to the second set time to the grid of the selected word line and the grid of the unselected word line after the charging ends of the bit lines in the erasing state are not charged.
As can be seen from the above description, the erased bit lines screened in step 120 may not include all erased bit lines, and therefore, the bit lines to be determined in this step may include both the programmed bit lines (i.e. the corresponding floating gate field effect transistors storing data "0") and a small number of erased bit lines.
In this embodiment, after the first data reading process of steps 110 and 120, the charging terminals of the bit lines to be determined except for the erased state in each bit line are charged again and charged to the reading operation voltage. At this time, the charging terminal of the erased state bit line is not charged any more, and specifically, a voltage of 0V may be applied to the charging terminal of the erased state bit line, or the charging terminal may be left floating. Because only a small part of the bit lines to be determined are the bit lines in the erasing state or the bit lines in the erasing state are not included at all, when the grid electrodes of the selected word lines and the grid electrodes of the unselected word lines are applied with the respective corresponding reading voltages to discharge in the step, the situation that large currents simultaneously appear on a plurality of bit lines does not exist, and the accuracy of reading data is further improved.
Further, when "0V" is used as the standard for screening the erased bit line in step 120, the floating gate fet with the raised threshold may not be screened, but after the recharging and discharging operation of the second set time in this step, the bit line charging terminal corresponding to the floating gate fet with the raised threshold is mostly discharged to 0V. Of course, in order to reduce the time required for reading data from the memory, the second setting time is not set to be too long, and then after the discharge of the second setting time, the charging voltage of the bit line corresponding to the floating gate field effect transistor with the threshold value being raised more may not be discharged to 0V, at this time, a voltage threshold (for example, 0.1V) may also be set, and the bit line with the charging voltage being less than the voltage threshold after the discharge in this step is also determined as the bit line in the erased state.
Further, in this embodiment, the second setting time should be longer than the first setting time to ensure that the data stored in the floating gate fet corresponding to the bit line to be determined is correctly read. The first setting time may be equal to or slightly less than a time for discharging the voltage at the charging terminal of the bit line during the data reading operation of the memory in the prior art.
S140, determining the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging end of the bit line to be determined.
In this embodiment, after the charging terminal of the bit line to be determined is discharged in step 130, the data stored in the memory cell (e.g., floating gate fet) corresponding to the bit line to be determined is determined according to the current voltage of the charging terminal of the bit line to be determined.
Specifically, if the current voltage of the charging terminal of the bit line to be determined is 0V or a smaller voltage (e.g., a voltage below 0.1V), the bit line to be determined is determined to be the erased bit line, and the data stored in the memory cell corresponding to the bit line to be determined is "1"; if the voltage of the charging terminal of the bit line to be determined is greater than 0V or greater than a set voltage threshold (e.g., 0.1V), the bit line to be determined is determined to be a programmed bit line, and the data stored in the memory cell corresponding to the bit line to be determined is "0".
The embodiment of the invention provides a data reading method, which divides a data reading process into two data reading processes with different time lengths, wherein the bit lines in most of the erasing state are screened out in the first data reading process by a short first set time, and the conventional data reading of the second set time is carried out on the rest bit lines in the second data reading process, so that the technical defects that in the prior art, the power consumption of a memory is large and the data reading error is easy to occur in the data reading process are overcome, the data reading power consumption of the memory is reduced, and the data reading accuracy of the memory is improved.
Example two
Fig. 2 is a flowchart of a data reading method according to a second embodiment of the present invention. The present embodiment is optimized based on the above embodiments, and in the present embodiment, a specific method for determining an erased bit line, a specific method for determining data stored in a memory cell corresponding to a bit line to be determined, and a specific implementation for specifying a magnitude relationship between a first setting time and a second setting time are provided.
Correspondingly, the method of the embodiment specifically includes:
s210, after charging the charging terminals of the bit lines corresponding to the selected word line to the read operating voltage, applying the read voltages corresponding to the gates of the selected word line and the gates of the unselected word lines for a first set time.
S220, if the current voltage of the charging end is smaller than the set voltage threshold, determining that the bit line corresponding to the charging end is an erasing state bit line, and determining that the data stored in the storage unit corresponding to the erasing state bit line is 1.
In this embodiment, after the charging terminals of the bit lines are discharged for the first time through step 210, specifically, the bit lines in the erased state are screened according to the set voltage threshold, and if the current voltage of the charging terminals is less than the set voltage threshold, the bit lines are determined to be the bit lines in the erased state. The set voltage threshold may typically be 0.2V or the like.
And S230, charging the charging ends of the bit lines to be determined except the bit line in the erasing state in each bit line to the reading working voltage again, and applying the reading voltages corresponding to the second set time to the grid of the selected word line and the grid of the unselected word line after the charging ends of the bit lines in the erasing state are not charged, wherein the first set time is less than the second set time.
In the embodiment, the first setting time is smaller than the second setting time, and since all the bit lines in the erase state are discharged simultaneously during the discharging process of the first setting time, the power consumption of the memory is greatly increased. Therefore, the first setting time should be set as short as possible to reduce the power consumption of reading data from the memory as much as possible, as long as it is ensured that the voltage of the charging terminal of most of the erased bit lines can be reduced to 0V or less than the setting voltage threshold after the discharging operation of the first setting time.
S240, if the current voltage of the charging end of the bit line to be determined is 0V, determining that the data stored in the storage unit corresponding to the bit line to be determined is 1.
In the present embodiment, with the "0V" voltage as the determination criterion, only the bit line of which the current voltage of the charging terminal is reduced to 0V is determined as the erased bit line after the discharging operation for the second set time in step 230. In this case, the second setting time can be set to be longer to ensure that the voltage of the charging terminal of the bit line corresponding to the floating gate field effect transistor in the erased state with the threshold raised to be higher can be reduced to 0V.
And S250, if the current voltage of the charging end of the bit line to be determined is greater than 0V, determining that the data stored in the storage unit corresponding to the bit line to be determined is 0.
The embodiment of the invention provides a data reading method, which embodies the magnitude relation between first set time and second set time, also embodies a determination method of an erasing bit line, further reduces the power consumption in the process of reading data for the second time, embodies the determination method of data stored in a storage unit corresponding to the bit line to be determined, and further improves the accuracy of reading the data.
EXAMPLE III
Fig. 3 is a structural diagram of a data reading apparatus according to a third embodiment of the present invention. As shown in fig. 3, the apparatus includes: a first voltage applying module 301, an erased state bit line determining module 302, a second voltage applying module 303, and a stored data determining module 304, wherein:
a first voltage applying module 301, configured to apply respective read voltages corresponding to a first set time to the gates of the selected word line and the gates of the unselected word lines after charging the charging terminals of the bit lines corresponding to the selected word line to the read operating voltage;
an erase state bit line determining module 302, configured to screen an erase state bit line from each bit line according to a current voltage of a charging end of each bit line, and determine that data stored in a storage unit corresponding to the erase state bit line is 1;
a second voltage applying module 303, configured to charge the charging terminal of the bit line to be determined, except for the bit line in the erase state, in each bit line to the read working voltage again, and apply the read voltages corresponding to the second set time to the gates of the selected word line and the gates of the unselected word lines after the charging terminal of the bit line in the erase state is not charged;
and the stored data determining module 304 is configured to determine, according to the current voltage of the charging terminal of the bit line to be determined, data stored in the memory cell corresponding to the bit line to be determined.
The embodiment of the invention provides a data reading device, which firstly applies respective corresponding reading voltages of a first set time to the gate of a selected word line and the gate of an unselected word line after charging the charging end of each bit line corresponding to the selected word line to a reading working voltage through a first voltage applying module 301, then screens an erasing state bit line from each bit line according to the current voltage of the charging end of each bit line through an erasing state bit line determining module 302, determines that the data stored in the memory unit corresponding to the erasing state bit line is 1, then charges the charging end of the to-be-determined bit line except the erasing state bit line in each bit line to the reading working voltage again according to a second voltage applying module 303, and applies respective corresponding reading voltages of a second set time to the gate of the selected word line and the gate of the unselected word line after not charging the charging end of the erasing state bit line, finally, the storage data determining module 304 determines the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging terminal of the bit line to be determined.
The device overcomes the technical defects that the power consumption of the memory is high and data reading errors are easy to occur in the data reading process in the prior art, reduces the data reading power consumption of the memory and improves the data reading accuracy of the memory.
On the basis of the above embodiments, the first set time may be smaller than the second set time.
On the basis of the foregoing embodiments, the erase state bit line determination module may be specifically configured to:
and if the current voltage of the charging end is less than the set voltage threshold, determining that the bit line corresponding to the charging end is the bit line in the erasing state.
On the basis of the foregoing embodiments, the storage data determination module may include:
the first data determination unit is used for determining that the data stored in the storage unit corresponding to the bit line to be determined is 1 if the current voltage of the charging end of the bit line to be determined is 0V;
and the second data determination unit is used for determining that the data stored in the storage unit corresponding to the bit line to be determined is 0 if the current voltage of the charging end of the bit line to be determined is greater than 0V.
The data reading device provided by the embodiment of the invention can be used for executing the data reading method provided by any embodiment of the invention, has corresponding functional modules and realizes the same beneficial effects.
Example four
Fig. 4 is a schematic structural diagram of an electronic apparatus according to a fourth embodiment of the present invention, as shown in fig. 4, the electronic apparatus includes a processor 40, a memory 41, an input device 42, and an output device 43; the number of the processors 40 in the electronic device may be one or more, and one processor 40 is taken as an example in fig. 4; the processor 40, the memory 41, the input device 42 and the output device 43 in the electronic apparatus may be connected by a bus or other means, and the bus connection is exemplified in fig. 4.
The memory 41, which is a computer-readable storage medium, may be used to store software programs, computer-executable programs, and modules, such as the modules corresponding to the reading method of data in the embodiment of the present invention (for example, the first voltage applying module 301, the erase state bit line determining module 302, the second voltage applying module 303, and the stored data determining module 304 in the reading apparatus of data). The processor 40 executes various functional applications of the electronic device and data processing, that is, implements the above-described data reading method, by executing software programs, instructions, and modules stored in the memory 41.
The memory 41 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 41 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 41 may further include memory located remotely from processor 40, which may be connected to the electronic device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 42 is operable to receive input numeric or character information and to generate key signal inputs relating to user settings and function controls of the electronic apparatus. The output device 43 may include a display device such as a display screen.
EXAMPLE five
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, where the computer-executable instructions are executed by a computer processor to perform a data reading method, and the method includes:
after charging the charging end of each bit line corresponding to the selected word line to the reading working voltage, applying the reading voltage corresponding to the first set time to the grid of the selected word line and the grid of the unselected word line;
screening an erasing state bit line from each bit line according to the current voltage of the charging end of each bit line, and determining that the data stored in the storage unit corresponding to the erasing state bit line is 1;
charging the charging ends of the bit lines to be determined except the bit line in the erasing state in each bit line to a reading working voltage again, and applying the reading voltages corresponding to the gates of the selected word line and the unselected word line for a second set time after the charging ends of the bit lines in the erasing state are not charged;
and determining the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging end of the bit line to be determined.
Of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the method operations described above, and may also perform related operations in the data reading method provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the data reading apparatus, the units and modules included in the embodiment are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for reading data, comprising:
after charging the charging end of each bit line corresponding to the selected word line to the reading working voltage, applying the reading voltage corresponding to the first set time to the grid of the selected word line and the grid of the unselected word line;
screening an erased bit line from the bit lines according to the current voltage of the charging end of each bit line, and determining that the data stored in the storage unit corresponding to the erased bit line is 1;
charging the charging end of the bit line to be determined except the bit line in the erasing state in each bit line to the reading working voltage again, and applying the reading voltages corresponding to the second set time to the grid of the selected word line and the grid of the unselected word line after not charging the charging end of the bit line in the erasing state;
and determining the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging end of the bit line to be determined.
2. The method of claim 1, wherein the first set time is less than the second set time.
3. The method of claim 1, wherein the screening the bit lines for an erased state from the respective bit lines according to the current voltage of the charged terminal of the respective bit lines comprises:
and if the current voltage of the charging end is less than the set voltage threshold, determining that the bit line corresponding to the charging end is the bit line in the erasing state.
4. The method of claim 1, wherein the determining the data stored in the memory cell corresponding to the bit line to be determined according to the current voltage of the charging terminal of the bit line to be determined comprises:
if the current voltage of the charging end of the bit line to be determined is 0V, determining that the data stored in the storage unit corresponding to the bit line to be determined is 1;
and if the current voltage of the charging end of the bit line to be determined is greater than 0V, determining that the data stored in the storage unit corresponding to the bit line to be determined is 0.
5. An apparatus for reading data, comprising:
the first voltage applying module is used for applying reading voltages corresponding to a first set time to the grid of the selected word line and the grid of the unselected word line after the charging ends of the bit lines corresponding to the selected word line are charged to the reading working voltage;
the erasing state bit line determining module is used for screening the erasing state bit lines from the bit lines according to the current voltage of the charging end of each bit line and determining that the data stored in the storage unit corresponding to the erasing state bit line is 1;
a second voltage applying module, configured to charge the charging end of the bit line to be determined in each bit line except the bit line in the erase state to the read working voltage again, and apply, after the charging end of the bit line in the erase state is not charged, the read voltages corresponding to the gates of the selected word line and the gates of the unselected word lines for a second set time;
and the storage data determining module is used for determining the data stored in the storage unit corresponding to the bit line to be determined according to the current voltage of the charging end of the bit line to be determined.
6. The apparatus of claim 5, wherein the first set time is less than the second set time.
7. The apparatus of claim 5, wherein the erase state bit line determination module is specifically configured to:
and if the current voltage of the charging end is less than the set voltage threshold, determining that the bit line corresponding to the charging end is the bit line in the erasing state.
8. The apparatus of claim 5, wherein the stored data determination module comprises:
the first data determining unit is used for determining that the data stored in the storage unit corresponding to the bit line to be determined is 1 if the current voltage of the charging end of the bit line to be determined is 0V;
and the second data determination unit is used for determining that the data stored in the storage unit corresponding to the bit line to be determined is 0 if the current voltage of the charging end of the bit line to be determined is greater than 0V.
9. An electronic device, characterized in that the electronic device comprises:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1-4.
10. A storage medium containing computer-executable instructions for performing the method of any one of claims 1-4 when executed by a computer processor.
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