CN110648712A - Method and device for applying word line voltage, electronic device and storage medium - Google Patents
Method and device for applying word line voltage, electronic device and storage medium Download PDFInfo
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- CN110648712A CN110648712A CN201810669076.1A CN201810669076A CN110648712A CN 110648712 A CN110648712 A CN 110648712A CN 201810669076 A CN201810669076 A CN 201810669076A CN 110648712 A CN110648712 A CN 110648712A
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
Abstract
The embodiment of the invention discloses a method and a device for applying word line voltage, electronic equipment and a storage medium. The method comprises the following steps: when data is read or written, one or two grids matched with the operation type are selected from grids of a selected word line, an unselected word line and a drain gated word line to serve as grids to be processed; acquiring a first initial voltage and a first target voltage corresponding to a grid to be processed according to the operation type, and respectively corresponding to second target voltages of non-to-be-processed grids in grids of a selected word line, an unselected word line and a drain gated word line; after applying a first initial voltage for a set time to the grid to be processed, applying a first target voltage to the grid to be processed, and applying a second target voltage to the grid not to be processed. The technical scheme of the embodiment of the invention realizes the weakening of program disturb and read disturb phenomena when the memory writes data and reads data, and reduces the error rate of the memory for storing data.
Description
Technical Field
The embodiment of the invention relates to the technical field of memory data processing, in particular to a method and a device for applying word line voltage, electronic equipment and a storage medium.
Background
The Nand-flash memory is one of flash memories, has the advantages of large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is widely applied in the industry, for example, embedded products comprise a digital camera, an MP3 walkman memory card, a small-sized U-disk and the like.
When the Nand flash memory reads data, a read disturb phenomenon can be generated due to the voltage difference between the control gate of the unselected word line and the substrate, so that a certain amount of electrons are absorbed by the floating gate in the floating gate field effect tube in the unselected word line.
When the Nand flash memory performs data writing operation, a program disturb phenomenon can be generated due to the voltage difference between the control gate of the unselected word line and the substrate, so that a certain amount of electrons are sucked by the floating gate in the floating gate field effect tube in the unselected word line.
Disclosure of Invention
Embodiments of the present invention provide a method and an apparatus for applying a word line voltage, an electronic device, and a storage medium, so as to optimize existing methods for reading and writing data in a memory.
In a first aspect, an embodiment of the present invention provides a method for applying a word line voltage, including:
when the operation type corresponding to the data operation instruction is reading data or writing data, selecting one or two grids matched with the operation type from the grid of the selected word line, the grid of the unselected word line and the grid of the drain gated word line as a grid to be processed;
according to the operation type, acquiring a first initial voltage and a first target voltage corresponding to the grid to be processed, and a second target voltage corresponding to a non-to-be-processed grid in the grids of the selected word line, the unselected word line and the drain gated word line, wherein the first initial voltage is greater than 0V and is less than the first target voltage;
after the first initial voltage with set time is applied to the grid to be processed, the first target voltage is applied to the grid to be processed, and meanwhile, the second target voltage is applied to the grid not to be processed.
In the above method, preferably, when the operation type corresponding to the data operation instruction is read data or write data, selecting one or two gates matching the operation type from the gate of the selected word line, the gate of the unselected word line, and the gate of the drain gated word line as a gate to be processed, includes:
and when the operation type corresponding to the data operation instruction is reading data, taking the grid of the unselected word line and/or the drain gated word line as the grid to be processed.
In the above method, preferably, when the operation type corresponding to the data operation instruction is read data or write data, selecting one or two gates matching the operation type from the gate of the selected word line, the gate of the unselected word line, and the gate of the drain gated word line as a gate to be processed, includes:
and when the operation type corresponding to the data operation instruction is write-in data, taking the grid of the selected word line and/or the drain gated word line as the grid to be processed.
In the above method, preferably, the set time is matched to the first initial voltage.
In the above method, it is preferable that the first initial voltage is equal to a product of the first target voltage and a value of 0.4.
In a second aspect, an embodiment of the present invention provides an apparatus for applying a word line voltage, including:
the grid electrode to be processed determining module is used for selecting one or two grid electrodes matched with the operation type from the grid electrode of the selected word line, the grid electrode of the unselected word line and the grid electrode of the drain electrode gating word line as grid electrodes to be processed when the operation type corresponding to the data operation instruction is reading data or writing data;
a voltage obtaining module, configured to obtain, according to the operation type, a first initial voltage and a first target voltage corresponding to the gate to be processed, and a second target voltage corresponding to a gate not to be processed in the gates of the selected word line, the unselected word line, and the drain-gated word line, where the first initial voltage is greater than 0V and is less than the first target voltage;
and the voltage application module is used for applying the first target voltage to the grid to be processed after applying the first initial voltage for set time to the grid to be processed, and applying the second target voltage to the grid not to be processed at the same time.
In the above apparatus, preferably, the to-be-processed gate determining module is specifically configured to:
and when the operation type corresponding to the data operation instruction is reading data, taking the grid of the unselected word line and/or the drain gated word line as the grid to be processed.
In the above apparatus, preferably, the to-be-processed gate determining module is specifically configured to:
and when the operation type corresponding to the data operation instruction is write-in data, taking the grid of the selected word line and/or the drain gated word line as the grid to be processed.
In a third aspect, an embodiment of the present invention provides an electronic device, including:
one or more processors;
storage means for storing one or more programs;
when the one or more programs are executed by the one or more processors, the one or more processors implement the method for applying the word line voltage according to any embodiment of the present invention.
In a fourth aspect, embodiments of the present invention provide a storage medium containing computer-executable instructions for performing a method of applying a wordline voltage according to any one of the embodiments of the present invention when executed by a computer processor.
The embodiment of the invention provides a method and a device for applying word line voltage, electronic equipment and a storage medium, wherein when data are written in and read out from a memory, final target voltages are not applied to a grid of a selected word line, a grid of an unselected word line and a grid of a drain gated word line simultaneously, but one or two of the final target voltages are selected to be applied first, and then the final target voltages are applied to the three simultaneously, so that the technical defects that the program disturb phenomenon and the read disturb phenomenon are serious when the memory writes data and reads data in the prior art are overcome, the program disturb phenomenon and the read disturb phenomenon of the memory when the data are written in and read are weakened, and the error rate of the data stored in the memory is reduced.
Drawings
FIG. 1 is a flowchart of a method for applying word line voltages according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for applying word line voltages according to a second embodiment of the present invention;
FIG. 3 is a flowchart of a method for applying word line voltages according to a third embodiment of the present invention;
FIG. 4 is a block diagram of a word line voltage applying apparatus according to a fourth embodiment of the present invention;
fig. 5 is a structural diagram of an electronic device according to a fifth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a flowchart of a method for applying a word line voltage according to an embodiment of the present invention, where the method of this embodiment may be performed by a device for applying a word line voltage, the device may be implemented by hardware and/or software, and may be generally integrated in a memory, such as a Nand flash memory. The method of the embodiment specifically includes:
and S110, when the operation type corresponding to the data operation instruction is reading data or writing data, selecting one or two grids matched with the operation type from the grid of the selected word line, the grid of the unselected word line and the grid of the drain gating word line as the grid to be processed.
It can be understood that, the memory using the floating gate memory as the basic memory cell has a readdisturb phenomenon and a program disturb phenomenon during the data reading operation and the data writing operation, respectively, due to the inherent hardware structure of the memory, which are unavoidable, but the readdisturb phenomenon and the program disturb phenomenon can be reduced by a proper method.
In the embodiment, creatively, the final target voltage is not directly applied to the gates of the selected word line, the unselected word line and the drain-gated word line at the same time, so that the gates of the selected word line, the unselected word line and the drain-gated word line are not lifted from 0V to the respective target voltages at the same time, and thus the readdisturb phenomenon and the program disturb phenomenon can be effectively reduced.
In this embodiment, one or two gates are selected from the gate of the selected word line, the gate of the unselected word line, and the gate of the drain-gated word line as the gate to be processed, according to the current operation type. The gate to be processed is specifically an electrode to which a set voltage value is first applied to other electrodes to which a working voltage is to be applied when data is read and written.
Further, the gates to be processed are different corresponding to different operation types. In order to reduce the read disturb phenomenon and the program disturb phenomenon without excessively increasing the time required for data processing, the gate to be processed should select as much as possible the gate to which the higher operating voltage needs to be applied. For example, when the operation type is reading data, since the voltage applied to the gates of the unselected word lines is 8V, the voltage applied to the selected word line is 0.5V, and the voltage applied to the gates of the drain-gated word lines is 2V, the gates of the unselected word lines are generally selected as the gates to be processed.
S120, according to the operation type, a first initial voltage and a first target voltage corresponding to the grid to be processed are obtained, and a second target voltage corresponding to the grid of the selected word line, the grid of the unselected word line and a non-to-be-processed grid of the drain gated word line is obtained, wherein the first initial voltage is greater than 0V, and the first initial voltage is smaller than the first target voltage.
In this embodiment, the first initial voltage specifically refers to a first voltage applied to the gate to be processed when reading data and writing data. The first target voltage specifically refers to a voltage that the gate to be processed should reach last when data is read and written, that is, a second voltage applied to the gate to be processed. The first initial voltage should be greater than 0V, and the first initial voltage should be less than the first target voltage. In addition, the first initial voltages corresponding to different gates to be processed may be the same or different.
Further, the value of the first initial voltage is not particularly limited in this embodiment, but in order to better reduce the read disturb phenomenon and the program disturb phenomenon, the value of the first initial voltage is not preferably set to be too small, and may be generally set to be half or 40 percent of the first target voltage, and the like. In addition, in consideration of the time required for the data operation, the difference between the first initial voltage and the first target voltage is as small as possible less than the target voltages of the other electrodes to which the operating voltage is to be applied.
In this embodiment, the target voltages corresponding to the non-to-be-processed gates among the gates of the selected word line, the gates of the unselected word lines, and the gates of the drain-gated word lines are directly applied, so that a second target voltage corresponding to the non-to-be-processed gates needs to be obtained while the first initial voltage and the first target voltage are obtained.
S130, after the first initial voltage with the set time is applied to the grid electrode to be processed, the first target voltage is applied to the grid electrode to be processed, and meanwhile, the second target voltage is applied to the grid electrode not to be processed.
In this embodiment, when reading data and writing data, a first initial voltage is applied to the gate to be processed for a set time, and no voltage is applied to other electrodes (including non-gate to be processed) to which an operating voltage is applied. And after the set time is reached, starting to simultaneously apply target voltages to all the electrodes to which the working voltage is to be applied, wherein the first target voltage is applied to the grid to be processed, and the second target voltage is applied to the grid not to be processed.
Further, since it is necessary to simultaneously apply the target voltages to all the electrodes to which the operating voltages are to be applied after the voltages of the gates to be processed reach the stable first initial voltages in order to effectively reduce the read disturb phenomenon and the program disturb phenomenon, the determination of the "set time" should be specifically referred to the value of the first initial voltage. The larger the first initial voltage is, the longer the setting time is, and it should be ensured that the voltage of the gate to be processed can be stably raised to the first initial voltage within the setting time.
The embodiment of the invention provides a method for applying word line voltage, which is characterized in that when data is written into a memory and data is read out, final target voltage is not applied to a grid of a selected word line, a grid of an unselected word line and a grid of a drain gated word line at the same time, but one or two of the final target voltage is applied first, and then the final target voltage is applied to the three simultaneously, so that the technical defects that the program disturb phenomenon and the read disturb phenomenon are serious when the memory writes data and reads data in the prior art are overcome, the program disturb phenomenon and the read disturb phenomenon of the memory when the data is written into and read from the memory are weakened, and the error rate of the memory for storing data is reduced.
Example two
Fig. 2 is a flowchart of a method for applying a word line voltage according to a second embodiment of the present invention. The present embodiment is optimized based on the above embodiments, and in the present embodiment, a specific implementation is given to embody the relationship between the set time and the first initial voltage by using the gate of the unselected word line as the gate to be processed and/or the gate of the drain gated word line.
Correspondingly, the method of the embodiment specifically includes:
s210, when the operation type corresponding to the data operation instruction is reading data, taking the grid of the drain gating word line as a grid to be processed.
In this embodiment, the operation type corresponding to the data operation instruction is specifically read data, and at this time, the gate to be processed may be a gate of an unselected word line, a gate of a drain-gated word line, a gate of an unselected word line, and a gate of a drain-gated word line. In this embodiment, a gate with a to-be-processed gate as a drain-gated word line is taken as an example for description, and voltage application methods corresponding to the arrangement modes of other two to-be-processed gates are similar to the voltage application method in this embodiment, and can be analogized, and detailed descriptions thereof are omitted.
S220, according to the operation type, a first initial voltage and a first target voltage corresponding to the grid of the drain gated word line and a second target voltage corresponding to the grid of the selected word line and the grid of the unselected word line respectively are obtained, wherein the first initial voltage is larger than 0V, and the first initial voltage is smaller than the first target voltage.
In this embodiment, the non-to-be-processed gates are gates of the selected word line and gates of unselected word lines, and therefore, when the second target voltage is obtained, the second target voltage corresponding to the gate of the selected word line and the second target voltage corresponding to the gate of the unselected word line need to be obtained respectively.
And S230, after a first initial voltage with set time is applied to the grid of the drain gated word line, a first target voltage is applied to the grid of the drain gated word line, and simultaneously a second target voltage is respectively applied to the grid of the selected word line and the grid of the unselected word line, wherein the set time is matched with the first initial voltage.
In this embodiment, the matching of the set time and the first initial voltage means that the voltage of the gate of the drain gated word line can be raised to the first initial voltage within the set time.
The embodiment of the invention provides a method for applying a word line voltage, which embodies that a gate to be processed is a gate of a drain gated word line, embodies the relation between set time and a first initial voltage, and realizes the reduction of a read disturb phenomenon when a memory reads data.
In the above embodiments, the first initial voltage is embodied to be equal to the product of the first target voltage and the value 0.4.
The benefits of this arrangement are: the time required for reading and writing data is reduced as much as possible while the program and read disturb phenomena are effectively reduced.
EXAMPLE III
Fig. 3 is a flowchart of a method for applying word line voltages according to a third embodiment of the present invention. The present embodiment is optimized based on the above embodiments, and in the present embodiment, a specific implementation is given in which the gate of the selected word line and/or the gate of the drain gated word line is the gate to be processed.
Correspondingly, the method of the embodiment specifically includes:
and S310, when the operation type corresponding to the data operation instruction is write-in data, taking the grid of the selected word line and the grid of the drain gating word line as the grid to be processed.
In this embodiment, the operation type corresponding to the data operation instruction is specifically write data, and at this time, the gate to be processed may specifically be a gate of a selected word line, a gate of a drain-gated word line, or a gate of the selected word line and a gate of the drain-gated word line. In this embodiment, a gate to be processed is taken as a gate of a selected word line and a gate of a drain-gated word line as an example for description, and voltage application methods corresponding to the arrangement modes of other two gates to be processed are similar to the voltage application method in this embodiment, and can be analogized, and detailed description is not repeated here.
S320, according to the operation type, a first initial voltage and a first target voltage which are respectively corresponding to the grid electrode of the selected word line and the grid electrode of the drain electrode gating word line are obtained, and a second target voltage which is corresponding to the grid electrode of the unselected word line is obtained, wherein the first initial voltage is larger than 0V, and the first initial voltage is smaller than the first target voltage.
In this embodiment, the gates to be processed are a first initial voltage and a first target voltage corresponding to the gate of the selected word line and the gate of the drain gated word line, respectively, and therefore, the first initial voltage and the first target voltage corresponding to the gate of the selected word line and the first initial voltage and the first target voltage corresponding to the gate of the drain gated word line need to be obtained respectively.
Here, the first initial voltages corresponding to the gate of the selected word line and the gate of the drain-gated word line may be the same or different. If the same, the time required to write the data can be minimized. However, since the target voltage of the gate of the selected word line is 20V and the target voltage of the gate of the drain-gated word line is 5V when data is written, the first initial voltage of the gate of the selected word line may be set to be a little higher, for example, 8V, in order to further reduce the program disturb phenomenon when data is written, and at this time, a certain time is wasted in the pressurizing process of the gate of the drain-gated word line for a set time. Therefore, the first initial voltages corresponding to the gate of the selected word line and the gate of the drain gated word line, respectively, can be determined according to the time required to write data and the result of measuring the severity of the programdisturb phenomenon.
S330, after the first initial voltage with set time is applied to the grid of the selected word line and the grid of the drain gated word line, the first target voltage is applied to the grid of the selected word line and the grid of the drain gated word line, and meanwhile, the second target voltage is applied to the grid of the unselected word line.
The embodiment of the invention provides a word line voltage applying method, which embodies that a grid to be processed is a grid of a selected word line and a grid of a drain gating word line, and realizes the reduction of a program disturb phenomenon when a memory writes data.
Example four
Fig. 4 is a structural diagram of a word line voltage applying apparatus according to a fourth embodiment of the present invention. As shown in fig. 4, the apparatus includes: a gate to be processed determining module 401, a voltage obtaining module 402, and a voltage applying module 403, wherein:
a to-be-processed gate determining module 401, configured to select one or two gates matching the operation type from the gate of the selected word line, the gates of the unselected word lines, and the gate of the drain-gated word line as a to-be-processed gate when the operation type corresponding to the data operation instruction is read data or write data;
a voltage obtaining module 402, configured to obtain, according to an operation type, a first initial voltage and a first target voltage corresponding to a gate to be processed, and a second target voltage corresponding to a gate not to be processed in a gate of a selected word line, a gate of an unselected word line, and a gate of a drain-gated word line, where the first initial voltage is greater than 0V and is less than the first target voltage;
the voltage applying module 403 is configured to apply a first initial voltage for a set time to the gate to be processed, and then apply a first target voltage to the gate to be processed, and apply a second target voltage to the gate not to be processed.
The embodiment of the invention provides a word line voltage applying device, which firstly selects one or two gates matched with an operation type from a gate of a selected word line, a gate of an unselected word line and a gate of a drain gated word line as a gate to be processed through a gate to be processed determining module 401 when the operation type corresponding to a data operation instruction is read data or write data, then acquires a first initial voltage and a first target voltage corresponding to the gate to be processed and a second target voltage corresponding to a gate of the selected word line, a gate of the unselected word line and a gate of the drain gated word line according to the operation type through a voltage acquiring module 402, wherein the first initial voltage is greater than 0V and smaller than the first target voltage, and finally applies the first initial voltage with a set time to the gate to be processed through a voltage applying module 403, and applying a first target voltage to the grid to be processed, and simultaneously applying a second target voltage to the grid not to be processed.
The device solves the technical defects that the program disturb phenomenon and the read disturb phenomenon are serious when the memory writes data and reads data in the prior art, the program disturb phenomenon and the read disturb phenomenon of the memory when writing data and reading data are weakened, and the error rate of data storage of the memory is reduced.
On the basis of the foregoing embodiments, the to-be-processed gate determining module 401 may be specifically configured to:
and when the operation type corresponding to the data operation instruction is reading data, taking the grid of the unselected word line and/or the drain gated word line as the grid to be processed.
On the basis of the foregoing embodiments, the to-be-processed gate determining module 401 may be further configured to:
and when the operation type corresponding to the data operation instruction is write-in data, taking the grid of the selected word line and/or the drain gated word line as the grid to be processed.
On the basis of the above embodiments, the set time may be matched to the first initial voltage.
On the basis of the above embodiments, the first initial voltage may be equal to the product of the first target voltage and the value 0.4.
The word line voltage applying device provided by the embodiment of the invention can be used for executing the word line voltage applying method provided by any embodiment of the invention, has corresponding functional modules and realizes the same beneficial effects.
EXAMPLE five
Fig. 5 is a schematic structural diagram of an electronic device according to a fifth embodiment of the present invention, as shown in fig. 5, the electronic device includes a processor 50, a memory 51, an input device 52, and an output device 53; the number of the processors 50 in the electronic device may be one or more, and one processor 50 is taken as an example in fig. 5; the processor 50, the memory 51, the input device 52 and the output device 53 in the electronic apparatus may be connected by a bus or other means, and the bus connection is exemplified in fig. 5.
The memory 51, as a computer-readable storage medium, may be used to store software programs, computer-executable programs, and modules, such as 5 modules corresponding to the method of applying a wordline voltage in the embodiment of the present invention (for example, the to-be-processed gate determining module 401, the voltage obtaining module 402, and the voltage applying module 403 in the apparatus for applying a wordline voltage). The processor 50 executes various functional applications and data processing of the electronic device, that is, implements the above-described word line voltage application method, by executing software programs, instructions, and modules stored in the memory 51.
The memory 51 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 51 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 51 may further include memory located remotely from the processor 50, which may be connected to the electronic device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 52 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function controls of the electronic apparatus. The output device 53 may include a display device such as a display screen.
EXAMPLE six
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a method for applying a word line voltage, the method including:
when the operation type corresponding to the data operation instruction is reading data or writing data, selecting one or two grid electrodes matched with the operation type from the grid electrode of the selected word line, the grid electrode of the unselected word line and the grid electrode of the drain electrode gating word line as grid electrodes to be processed;
according to the operation type, a first initial voltage and a first target voltage corresponding to the grid to be processed are obtained, and second target voltages corresponding to non-to-be-processed grids in the grid of the selected word line, the grid of the unselected word line and the grid of the drain gated word line are obtained, wherein the first initial voltage is greater than 0V, and the first initial voltage is smaller than the first target voltage;
after applying a first initial voltage for a set time to the gate to be processed, applying a first target voltage to the gate to be processed, and simultaneously applying a second target voltage to the gate not to be processed.
Of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the method operations described above, and may also perform related operations in the method for applying the word line voltage provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the word line voltage applying apparatus, the included units and modules are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be realized; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for applying a word line voltage, comprising:
when the operation type corresponding to the data operation instruction is reading data or writing data, selecting one or two grids matched with the operation type from the grid of the selected word line, the grid of the unselected word line and the grid of the drain gated word line as a grid to be processed;
according to the operation type, a first initial voltage and a first target voltage corresponding to the grid to be processed are obtained, and second target voltages corresponding to non-to-be-processed grids in the grid of the selected word line, the grid of the unselected word line and the grid of the drain gated word line are obtained, wherein the first initial voltage is greater than 0V, and the first initial voltage is smaller than the first target voltage;
after the first initial voltage with set time is applied to the grid to be processed, the first target voltage is applied to the grid to be processed, and meanwhile, the second target voltage is applied to the grid not to be processed.
2. The method of claim 1, wherein when the operation type corresponding to the data operation command is read data or write data, selecting one or two gates matching the operation type from the gates of the selected word line, the unselected word line and the drain-gated word line as a gate to be processed, comprises:
and when the operation type corresponding to the data operation instruction is reading data, taking the grid of the unselected word line and/or the grid of the drain gating word line as the grid to be processed.
3. The method of claim 1, wherein when the operation type corresponding to the data operation command is read data or write data, selecting one or two gates matching the operation type from the gates of the selected word line, the unselected word line and the drain-gated word line as a gate to be processed, comprises:
and when the operation type corresponding to the data operation instruction is write-in data, taking the grid of the selected word line and/or the grid of the drain gating word line as the grid to be processed.
4. The method of claim 1, wherein the set time matches the first initial voltage.
5. The method of any one of claims 1-4, wherein the first initial voltage is equal to the first target voltage multiplied by a value of 0.4.
6. An apparatus for applying a word line voltage, comprising:
the grid electrode to be processed determining module is used for selecting one or two grid electrodes matched with the operation type from the grid electrode of the selected word line, the grid electrode of the unselected word line and the grid electrode of the drain electrode gating word line as grid electrodes to be processed when the operation type corresponding to the data operation instruction is reading data or writing data;
a voltage obtaining module, configured to obtain, according to the operation type, a first initial voltage and a first target voltage corresponding to the gate to be processed, and a second target voltage corresponding to a gate not to be processed in the gates of the selected word line, the unselected word line, and the drain-gated word line, where the first initial voltage is greater than 0V and is less than the first target voltage;
and the voltage application module is used for applying the first target voltage to the grid to be processed after applying the first initial voltage for set time to the grid to be processed, and applying the second target voltage to the grid not to be processed at the same time.
7. The apparatus of claim 6, wherein the pending gate determination module is specifically configured to:
and when the operation type corresponding to the data operation instruction is reading data, taking the grid of the unselected word line and/or the drain gated word line as the grid to be processed.
8. The apparatus of claim 6, wherein the pending gate determination module is specifically configured to:
and when the operation type corresponding to the data operation instruction is write-in data, taking the grid of the selected word line and/or the drain gated word line as the grid to be processed.
9. An electronic device, characterized in that the electronic device comprises:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the method of applying word line voltages of any of claims 1-5.
10. A storage medium containing computer-executable instructions for performing the method of applying a word line voltage of any one of claims 1-5 when executed by a computer processor.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404610A (en) * | 2000-02-28 | 2003-03-19 | 先进微装置公司 | Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage |
| CN101005081A (en) * | 2006-01-04 | 2007-07-25 | 海力士半导体有限公司 | Non-volatile memory device, and manufacturing method and programming method thereof |
| CN101315813A (en) * | 2007-06-01 | 2008-12-03 | 海力士半导体有限公司 | Method of reading flash memory device for depressing read disturb |
| US20090016110A1 (en) * | 2007-07-10 | 2009-01-15 | Samsung Electronics Co., Ltd. | Methods of reading data from non-volatile semiconductor memory device |
| CN101356587A (en) * | 2005-09-09 | 2009-01-28 | 桑迪士克股份有限公司 | Last-first mode and method for programming of non-volatile memory of NAND type with reduced program disturb |
| US20100054036A1 (en) * | 2008-08-27 | 2010-03-04 | Samsung Electronics Co., Ltd. | Methods of precharging non-volatile memory devices during a programming operation and memory devices programmed thereby |
| US20100091575A1 (en) * | 2008-10-13 | 2010-04-15 | Samsung Electronics Co., Ltd. | Programming method and initial charging method of nonvolatile memory device |
| US20150103592A1 (en) * | 2013-10-10 | 2015-04-16 | Sandisk Technologies Inc. | Programming time improvement for non-volatile memory |
| CN107393590A (en) * | 2016-04-04 | 2017-11-24 | 三星电子株式会社 | Non-volatile memory device and its programmed method |
| CN107507646A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of control method and device for reducing programming interference |
| CN107564567A (en) * | 2016-06-30 | 2018-01-09 | 爱思开海力士有限公司 | The method being programmed to semiconductor memory system |
| CN107689245A (en) * | 2017-08-31 | 2018-02-13 | 长江存储科技有限责任公司 | A kind of programmed method of nand flash memory device |
-
2018
- 2018-06-26 CN CN201810669076.1A patent/CN110648712A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404610A (en) * | 2000-02-28 | 2003-03-19 | 先进微装置公司 | Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage |
| CN101356587A (en) * | 2005-09-09 | 2009-01-28 | 桑迪士克股份有限公司 | Last-first mode and method for programming of non-volatile memory of NAND type with reduced program disturb |
| CN101005081A (en) * | 2006-01-04 | 2007-07-25 | 海力士半导体有限公司 | Non-volatile memory device, and manufacturing method and programming method thereof |
| CN101315813A (en) * | 2007-06-01 | 2008-12-03 | 海力士半导体有限公司 | Method of reading flash memory device for depressing read disturb |
| US20090016110A1 (en) * | 2007-07-10 | 2009-01-15 | Samsung Electronics Co., Ltd. | Methods of reading data from non-volatile semiconductor memory device |
| US20100054036A1 (en) * | 2008-08-27 | 2010-03-04 | Samsung Electronics Co., Ltd. | Methods of precharging non-volatile memory devices during a programming operation and memory devices programmed thereby |
| US20100091575A1 (en) * | 2008-10-13 | 2010-04-15 | Samsung Electronics Co., Ltd. | Programming method and initial charging method of nonvolatile memory device |
| US20150103592A1 (en) * | 2013-10-10 | 2015-04-16 | Sandisk Technologies Inc. | Programming time improvement for non-volatile memory |
| CN107393590A (en) * | 2016-04-04 | 2017-11-24 | 三星电子株式会社 | Non-volatile memory device and its programmed method |
| CN107564567A (en) * | 2016-06-30 | 2018-01-09 | 爱思开海力士有限公司 | The method being programmed to semiconductor memory system |
| CN107507646A (en) * | 2017-08-31 | 2017-12-22 | 长江存储科技有限责任公司 | A kind of control method and device for reducing programming interference |
| CN107689245A (en) * | 2017-08-31 | 2018-02-13 | 长江存储科技有限责任公司 | A kind of programmed method of nand flash memory device |
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