CN110910940B - Programming method and device of memory, storage equipment and storage medium - Google Patents
Programming method and device of memory, storage equipment and storage medium Download PDFInfo
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- CN110910940B CN110910940B CN201811089910.6A CN201811089910A CN110910940B CN 110910940 B CN110910940 B CN 110910940B CN 201811089910 A CN201811089910 A CN 201811089910A CN 110910940 B CN110910940 B CN 110910940B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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Abstract
The embodiment of the invention discloses a programming method and device of a memory, a storage device and a storage medium. The method comprises the following steps: performing a first programming operation on a memory cell to be programmed in a selected word line, wherein a programming completion verification voltage corresponding to the first programming operation is a first verification voltage; taking all memory cells with the threshold value smaller than the second verifying voltage in the memory cells to be programmed as reprogramming units; and performing a second programming operation on the re-programmed cell, wherein a programming completion verification voltage corresponding to the second programming operation is a second verification voltage, and the second verification voltage is greater than the first verification voltage. The technical scheme of the embodiment of the invention can simply, conveniently and effectively reduce the distribution width of the threshold value of the memory unit after programming without additionally arranging a hardware circuit, and further can reduce the voltage applied to the unselected word line during reading operation, thereby weakening the phenomenon of readdisturb and improving the reliability of the memory.
Description
Technical Field
The embodiment of the invention relates to the technical field of storage equipment, in particular to a programming method and device of a memory, the storage equipment and a storage medium.
Background
Due to the problem of process fluctuation in the production process of the memory, the intrinsic threshold voltage distribution of the memory cells is in a gaussian distribution state, and the programming speeds of different memory cells are different, so that the threshold voltages of different memory cells corresponding to one page or one block in the memory after programming or erasing are different, and the distribution width of the threshold is wide. The wider threshold voltage distribution limits the voltage drop applied to the unselected wordlines during the read operation, which in turn causes a severe read disturb phenomenon. In addition, the wider threshold voltage distribution causes a larger voltage difference between the substrate and the gate of the memory cell during the erase operation and the read operation, which reduces the reliability of the memory.
In the prior art, a pre-test voltage smaller than a programming success check voltage is generally set, and when a conduction threshold of a programmed memory cell is greater than or equal to the pre-test voltage, a programming voltage pulse signal is applied to a word line of a page while a voltage pulse signal with a fixed voltage value is applied to a bit line corresponding to the programmed memory cell, so as to reduce a voltage difference between a control gate and a channel of the programmed memory cell, thereby reducing a programming speed of the programmed memory cell, and further reducing a threshold voltage distribution width of the memory cell corresponding to the page after programming.
In the process of implementing the invention, the inventor finds that the prior art has the following defects: the reduction effect of the threshold voltage distribution width after the memory cell is programmed is poor, and a circuit for applying the voltage pulse signal with a fixed voltage value needs to be additionally added, so that the complexity of the hardware structure of the memory is increased, and the manufacturing cost of the memory is increased.
Disclosure of Invention
Embodiments of the present invention provide a method, an apparatus, a storage device, and a storage medium for programming a memory, so as to reduce a distribution width of threshold values of memory cells after being programmed.
In a first aspect, an embodiment of the present invention provides a method for programming a memory, including:
performing a first programming operation on a memory cell to be programmed in a selected word line, wherein a programming completion verification voltage corresponding to the first programming operation is a first verification voltage;
taking all the memory cells with the threshold value smaller than the second verifying voltage in the memory cells to be programmed as reprogramming units;
and performing a second programming operation on the reprogramming unit, wherein a programming completion verification voltage corresponding to the second programming operation is the second verification voltage, and the second verification voltage is greater than the first verification voltage.
In the foregoing method, optionally, the performing a second programming operation on the reprogramming unit specifically includes:
and performing a second programming operation on the re-programming unit under the condition of applying a bit line cut-off voltage to bit lines corresponding to the memory units with the threshold value being more than or equal to a second verifying voltage in all the memory units to be programmed.
In the foregoing method, optionally, the performing a first programming operation on the selected word line, where a program completion verification voltage corresponding to the first programming operation is a first verification voltage, includes:
applying word line programming pulse voltages to a selected word line, and detecting whether a conduction threshold of a memory cell to be programmed in the selected word line is greater than or equal to a bit line pressurization threshold and less than a first verification voltage at the end of each pulse in the word line programming pulse voltages, wherein the bit line pressurization threshold is less than the first verification voltage;
if the conduction threshold of the memory cell to be programmed is greater than or equal to the bit line pressurization threshold and less than the first verification voltage, applying the next pulse in the word line programming pulse voltages to the selected word line, and simultaneously applying the first pulse in the bit line programming pulse voltages to the bit line corresponding to the memory cell to be programmed, wherein the voltage value of each pulse in the bit line programming pulse voltages sequentially increases and the increasing amplitude is less than the increasing amplitude of the pulse in the word line programming pulse voltages corresponding to the pulse values, the period and the pulse width of the bit line programming pulse voltages are the same, and the voltage value of the first pulse in the bit line programming pulse voltages is less than the increasing amplitude of the pulse in the word line programming pulse voltages corresponding to the bit line programming pulse voltages;
detecting whether the conduction threshold of the memory cell to be programmed is greater than or equal to the first verification voltage each time a pulse in the word line programming pulse voltage and a pulse in the bit line programming pulse voltage end simultaneously;
if the conduction threshold value of the memory cell to be programmed is greater than or equal to the first verification voltage, the bit line programming pulse voltage is not applied to the bit line corresponding to the memory cell to be programmed any more, and a cut-off voltage is applied to the bit line corresponding to the memory cell to be programmed;
if the conduction threshold of the to-be-programmed memory cell is smaller than the first verification voltage, continuing to apply the word line programming pulse voltage and the bit line programming pulse voltage to the selected word line and the bit line corresponding to the to-be-programmed memory cell respectively, and returning to execute the operation of detecting whether the conduction threshold of the to-be-programmed memory cell is larger than or equal to the first verification voltage when the pulse in the word line programming pulse voltage and the pulse in the bit line programming pulse voltage end at the same time each time until the conduction threshold of the to-be-programmed memory cell is larger than or equal to the first verification voltage.
In the above method, optionally, the method further includes:
and if the conduction threshold of the memory cell to be programmed is smaller than the bit line pressurization threshold, returning to execute the operation of applying the word line programming pulse voltage to the selected word line and detecting whether the conduction threshold of the memory cell to be programmed in the selected word line is larger than or equal to the bit line pressurization threshold and smaller than a first verification voltage or not at the end of each pulse in the word line programming pulse voltage.
In the above method, optionally, the method further includes:
and if the turn-on threshold value of the memory cell to be programmed is greater than or equal to the first verifying voltage, applying a cut-off voltage to the bit line corresponding to the memory cell to be programmed.
In the above method, optionally, the voltage values of the respective pulses in the bit line programming pulse voltages are sequentially increased by equal magnitudes.
In a second aspect, an embodiment of the present invention provides a programming apparatus for a memory, including:
the first programming module is used for carrying out first programming operation on a memory cell to be programmed in a selected word line, and a programming completion verifying voltage corresponding to the first programming operation is a first verifying voltage;
the memory cell screening module is used for taking all memory cells with threshold values smaller than the second verification voltage in the memory cells to be programmed as reprogramming units;
and the second programming module is used for carrying out second programming operation on the reprogramming unit, and the programming completion verifying voltage corresponding to the second programming operation is the second verifying voltage which is greater than the first verifying voltage.
In the above apparatus, optionally, the second programming module is specifically configured to:
and performing a second programming operation on the re-programming unit under the condition of applying a bit line cut-off voltage to bit lines corresponding to the memory units with the threshold value being more than or equal to a second verifying voltage in all the memory units to be programmed.
In a third aspect, an embodiment of the present invention provides a storage device, where the storage device includes:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the method of any embodiment of the invention.
In a fourth aspect, embodiments of the present invention provide a storage medium containing computer-executable instructions for performing a method according to any of the embodiments of the present invention when executed by a computer processor.
Embodiments of the present invention provide a programming method, apparatus, storage device, and storage medium for a memory, which decompose a programming process into two programming operations, and only the memory cell to be programmed with the threshold value smaller than the second verifying voltage is programmed in the decomposed second programming operation, so that the problem that the existing method for reducing the threshold value distribution width not only has poor effect on reducing the threshold value voltage distribution width after the memory cell is programmed is solved, and the technical defects of the complexity of the hardware circuit and the manufacturing cost of the memory are increased, and under the condition of not additionally arranging the hardware circuit, the distribution width of the threshold value of the memory cell after programming can be simply and effectively reduced, further, the voltage applied to the unselected word line during the read operation can be reduced, thereby reducing the read disturb phenomenon and improving the reliability of the memory.
Drawings
FIG. 1a is a flow chart of a method for programming a memory according to an embodiment of the present invention;
FIG. 1b is a diagram illustrating threshold distributions of memory cells to be programmed after a first programming operation and a second programming operation according to an embodiment of the present invention;
FIG. 2a is a flowchart of a method for programming a memory according to a second embodiment of the present invention;
FIG. 2b is a schematic diagram of a word line programming pulse voltage and a bit line programming pulse voltage according to the second embodiment of the present invention;
FIG. 3 is a block diagram of a programming apparatus of a memory according to a third embodiment of the present invention;
fig. 4 is a structural diagram of a storage device according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1a is a flowchart of a method for programming a memory according to an embodiment of the present invention, where the method of the present embodiment may be performed by a programming apparatus of the memory, and the apparatus may be implemented by hardware and/or software, and may be generally integrated in a storage device. The method of the embodiment specifically includes:
s101, performing a first programming operation on a memory cell to be programmed in a selected word line, wherein a programming completion verification voltage corresponding to the first programming operation is a first verification voltage.
And S102, taking the memory cells with the threshold value smaller than the second verifying voltage in all the memory cells to be programmed as reprogramming units.
S103, performing a second programming operation on the re-programming unit, wherein a programming completion verification voltage corresponding to the second programming operation is a second verification voltage, and the second verification voltage is greater than the first verification voltage.
In the present embodiment, the selected word line specifically refers to the currently programmed word line. The memory cells to be programmed are specifically the memory cells needing to be programmed in the selected word line. The first verify voltage is specifically a voltage value used to determine whether the memory cell to be programmed is successfully programmed for the first time.
In this embodiment, the programming operation for the selected word line is completed through two programming operations performed in steps 101 to 103, in which the first and second verify voltages are the program completion verify voltages, respectively. The first verifying voltage is smaller than the second verifying voltage, which is a voltage for verifying whether the memory cells to be programmed in the selected word line are finally successfully programmed, and may be typically 18V. In addition, the first verify voltage should also be greater than the maximum value of the threshold distribution width of the memory cells to be programmed after the program operation, the erase operation.
It can be understood that the intrinsic threshold voltage distributions of the memory cells are gaussian due to process fluctuation problems in the manufacturing process of the memory, and the programming speeds of different memory cells are different (for example, the programming speeds of different floating gate fets are different because it is difficult to ensure that the tunnel oxide layer thickness and quality of each floating gate fet are completely the same). Different memory cells have different intrinsic thresholds and different memory cells have different programming speeds, both of which adversely affect the threshold distribution width of the memory cell after programming.
Further, since the process fluctuation problem is difficult to completely avoid, the inherent difference between different memory cells always exists, and therefore, the threshold distributions of the memory cells in the memory after programming have a certain width, which makes it difficult to reduce the voltage Vread applied to the unselected word lines during the read operation, and thus to reduce the read disturb phenomenon.
However, the programming method of the memory in this embodiment skillfully reduces the threshold distribution width of the memory cell after programming by performing the verifying operation twice separately and corresponding to different programming completion voltages and different numbers of memory cells to be programmed, and the programming process of the memory is specifically as follows:
first, a first program operation is performed on a selected word line, that is, a normal program operation is performed on all memory cells to be programmed in the selected word line, but the normal program operation corresponds to a program completion verifying voltage that is not a normal program completion verifying voltage (e.g., a second verifying voltage in the present embodiment) but a first verifying voltage that is smaller than the normal program completion verifying voltage.
It is understood that, regardless of the value of the program-complete verification voltage corresponding to the program operation, after the program operation is completed, the threshold values of the memory cells have a threshold distribution width corresponding to the intrinsic difference of their hardware, so that the threshold distribution of the memory cells to be programmed is still large after the first program operation is completed.
Fig. 1b exemplarily shows threshold distribution curves of memory cells to be programmed after the first programming operation and the second programming operation in the present embodiment, which are curve 1 and curve 2, respectively. As shown in fig. 1b, for curve 1, Vt1 is the first verify voltage, Vt1 to Vt3 are the threshold distribution widths of the memory cells to be programmed after the first program operation, and the vertical axis in fig. 1b is the number of memory cells to be programmed corresponding to the current threshold voltage after the first program operation.
Next, a reprogramming unit is selected according to the second verify voltage.
It is understood that, since the threshold distributions of all the memory cells to be programmed have a certain width after the first programming operation is performed on the memory cells to be programmed, the threshold distributions of some memory cells in all the memory cells to be programmed after the first programming operation can be made to be greater than or equal to the second verifying voltage as long as the first verifying voltage is properly selected, that is, the "some memory cells" actually complete the programming operation. Therefore, for a memory cell to be programmed (hereinafter, referred to as a first type memory cell) whose threshold value is equal to or higher than the second verify voltage after the first programming, it is not necessary to perform the second programming operation, but for a memory cell to be programmed (hereinafter, referred to as a second type memory cell) whose threshold value is equal to or higher than the second verify voltage after the first programming, it is necessary to further perform the second programming operation so that its threshold value is equal to or higher than the second verify voltage.
It can be further understood that the programming speed of the first type memory cell is faster than that of the second type memory cell, and if the programming of all the memory cells to be programmed is not stopped until the threshold values of all the memory cells to be programmed are greater than or equal to the second verifying voltage, the difference between the threshold values of the first type memory cell and the threshold values of the second type memory cell is larger at this time, that is, the threshold distribution width of the memory cells to be programmed is larger after the programming. However, in the programming method of the memory in this embodiment, after the first programming operation is finished, the programming operation on the first type memory cells is stopped, so that the threshold of the first type memory cells does not continue to be raised, thereby greatly reducing the threshold distribution width of the memory cells to be programmed after the second programming operation is finished.
Further, it can be understood that, for the setting of the first verifying voltage, if the first verifying voltage is set to be relatively small, after the first programming operation, the number of memory cells to be programmed with the threshold value greater than or equal to the second verifying voltage is relatively small (hereinafter referred to as a first case); if the first verify voltage is set to be relatively large, the number of memory cells to be programmed having a threshold value equal to or greater than the second verify voltage after the first programming operation is relatively large (hereinafter referred to as a second case).
For the second case, since the first verify voltage is set to be relatively large, the number of pulses in the word line program pulse voltage required to be applied to the selected word line at the time of the first program operation is relatively large, and thus the difference between the maximum value of the threshold value of the memory cell to be programmed and the second verify voltage is relatively large after the first program operation is completed. It is understood that the width of the threshold distribution of the memory cell to be programmed after the second programming operation is certainly not smaller than the difference between the maximum value of the threshold of the memory cell to be programmed after the first programming operation and the second verifying voltage, and thus it is known that the effect of reducing the width of the threshold distribution of the memory cell to be programmed after the programming operation is relatively poor at this time.
For the first case, since the first verify voltage is set to be relatively small, the number of pulses in the word line program pulse voltage required to be applied to the selected word line at the time of the first program operation is relatively small, and thus the difference between the maximum value of the threshold value of the memory cell to be programmed and the second verify voltage is relatively small after the first program operation is completed. However, since the difference between the minimum value of the threshold value of the memory cell to be programmed and the second verify voltage is relatively large after the first programming operation, the number of pulses in the word line program pulse voltage on the selected word line, which needs to be applied when the second programming operation is performed, is larger. It is understood that, the larger the number of pulses in the word line programming pulse voltage applied to the selected word line, the larger the difference between the threshold values of the memory cell with the fast programming speed and the memory cell with the slow programming speed after the end of programming, so that even if the difference between the maximum value of the threshold value of the memory cell to be programmed and the second verifying voltage is relatively small after the first programming operation in the first case, it cannot be guaranteed that the threshold value distribution of the memory cell to be programmed after the second programming operation is necessarily small.
As can be seen from the above description of the two cases, for the setting of the first verify voltage, it should be firstly ensured that after the first programming operation, the second verify voltage is less than or equal to the middle voltage value of the threshold distribution width of the current memory cell to be programmed; secondly, it can be understood that, because the manufacturing processes, the manufacturing materials and the manufacturing levels of different memories are different, the programming capabilities of the memory cells in different memories and the number of memory cells with the same programming capability are different. If different memories all use the same second verifying voltage, then the effect of reducing the threshold distribution width after programming of different memories is different for the same first verifying voltage by the programming method of the memory in this embodiment, so that the most suitable first verifying voltage can be selected for different memories through experiments.
The threshold distribution curves of the memory cells to be programmed after the first and second programming operations are exemplarily shown as gaussian curves in fig. 1 b. In fact, in practical cases, the threshold distribution curve after programming corresponding to most memories is similar to a gaussian curve. It is understood that if the threshold distribution curve of the to-be-programmed memory cell after programming is a normal gaussian curve, a programming completion verify voltage that can make the voltage value of the midpoint of the curve 1 equal to the second verify voltage value is selected as the first verify voltage, and then the threshold distribution width of the to-be-programmed memory cell after the second programming operation can be minimized. As shown in FIG. 1b, for curve 2, Vt2 is the second verify voltage, Vt 2-Vt 3 is the threshold distribution width of the memory cells to be programmed after the second programming operation, and Vt2 is the midpoint of the threshold voltage range formed by Vt 1-Vt 3.
Finally, the second programming operation is performed on the re-programmed cell according to the second verify voltage.
After the second programming operation, the threshold values of all the memory cells to be programmed are greater than or equal to the second verifying voltage and have a smaller threshold distribution width.
In addition, it can be understood that, for the floating gate field effect transistor, the larger the voltage difference between the gate and the substrate of the memory cell, the larger the destructive force to the tunneling oxide layer, which not only shortens the service life of the memory, but also reduces the reliability of the memory. The programming method of the memory in the embodiment reduces the threshold distribution width of the memory cell after programming, and further can reduce the voltage applied to the unselected word line during the reading operation, thereby reducing the pressure difference between the grid electrode of the memory cell and the substrate during the reading operation, reducing the damage to the tunneling oxide layer, and simultaneously weakening the read disturb phenomenon.
The embodiment of the invention provides a programming method of a memory, which decomposes a programming process into two programming operations, and only performs the programming operation on a to-be-programmed memory cell with a threshold value smaller than a second inspection voltage in the decomposed second programming operation, thereby solving the technical defects that the existing method for reducing the threshold value distribution width has poor effect of reducing the threshold value voltage distribution width after the memory cell is programmed, and increases the complexity of a hardware circuit and the manufacturing cost of the memory, realizing that the threshold value distribution width of the memory cell after programming can be simply, conveniently and effectively reduced under the condition of not additionally adding the hardware circuit, further reducing the voltage applied to non-selected word lines during reading operation, weakening the read disturb phenomenon and improving the reliability of the memory.
Example two
Fig. 2a is a flowchart of a method for programming a memory according to a second embodiment of the present invention. The present embodiment is optimized based on the above-described embodiments, and in the present embodiment, a voltage application method embodying the second programming operation is provided, embodying the specific implementation of the first programming process.
Correspondingly, the method of the embodiment specifically includes:
s201, applying word line programming pulse voltage to a selected word line, detecting whether the conduction threshold value of a to-be-programmed storage unit in the selected word line is larger than or equal to a bit line pressurization threshold value or not when each pulse in the word line programming pulse voltage is ended, if not, executing the step 201 again, and if so, executing the step 202.
In the present embodiment, a first time programming process is embodied, and steps 201 to 207 are specific steps of the first time programming process. Likewise, the second programming process may be set as a similar programming process to the first programming process, and only the first programming process will be described in detail in this embodiment.
In this embodiment, the word line programming pulse voltage is specifically a voltage signal applied to the selected word line, and the voltage values of the pulses in the word line programming pulse voltage sequentially increase, and the increasing magnitudes may be equal or different. The bit line voltage threshold is specifically a voltage value used to determine whether the bit line programming pulse voltage described in step 204 needs to be applied to the bit line corresponding to the memory cell to be programmed.
Generally, in a program operation of a memory (e.g., Nand flash memory), a program voltage is applied to a selected word line in a pulse voltage manner. Since different memory cells (e.g., floating gate field effect transistors) have different programming speeds (i.e., different lengths of time required for the turn-on threshold of the memory cell to be raised to be equal to or greater than the program verify voltage threshold), different numbers of programming voltage pulses required for raising the turn-on threshold of the memory cell having different programming speeds to be equal to or greater than the program complete verify voltage (the voltage value used for verifying whether programming is successful, e.g., the first verify voltage) are different.
It can be understood that the word line programming pulse voltage is stopped from being applied to the selected word line only when the conduction threshold values of all the memory cells to be programmed in the selected word line are greater than or equal to the programming completion verification voltage, so that at the end of the programming operation, a conduction threshold difference exists between the conduction threshold value of the fast-programming memory cell and the conduction threshold value of the slow-programming memory cell, and the larger the programming speed difference is, the larger the conduction threshold difference is, so that the threshold voltage distribution width of the memory cells to be programmed in the selected word line after being programmed is larger.
In this embodiment, in order to reduce the threshold voltage distribution width of the memory cell to be programmed in the selected word line after being programmed, the bit line boosting threshold is set. When each of the word line programming pulse voltages applied to the selected word line ends, it is not only detected whether the conduction threshold of the memory cell to be programmed in the selected word line is equal to or greater than the first verify voltage, but it is detected whether the conduction threshold of the memory cell to be programmed in the selected word line is equal to or greater than the bit line stressing threshold and less than the first verify voltage. Further, when the conduction threshold of the to-be-programmed memory cell in the selected word line is greater than or equal to the bit line stressing threshold and less than the first verifying voltage, steps 204 to 207 are performed to decrease the programming speed of the to-be-programmed memory cell (i.e., decrease a programming voltage pulse to increase the conduction threshold of the to-be-programmed memory cell).
It is understood that the purpose of setting the bit line stressing threshold is to slow down the programming speed of the memory cell to be programmed after the turn-on threshold of the memory cell to be programmed is greater than or equal to the bit line stressing threshold, thereby reducing the threshold distribution width of all the memory cells to be programmed. Then, the number of pulses in the word line program pulse voltage, the value of the first verify voltage, the increment amplitude of each pulse in the word line program pulse voltage, and the like, which are required for the fast-programming and slow-programming memory cells, respectively, may be considered together to determine the value of the bit line stress threshold.
Specifically, the larger the increment of each pulse in the word line programming pulse voltage (in this case, if the difference between the bit line stressing threshold and the first verify voltage is not large enough, it may occur that the conduction threshold of the memory cell to be programmed before the application of one pulse in the word line programming pulse voltage is smaller than the bit line stressing threshold, but the conduction threshold of the memory cell to be programmed after the application of the one pulse is equal to or greater than the first verify voltage, in this case, the programming speed of the memory cell to be programmed cannot be reduced through steps 204 to 207), the smaller the number of pulses in the word line programming pulse voltage required for a fast programming memory cell, or the larger the number of pulses in the word line programming pulse voltage required for a slow programming memory cell, the lower the bit line stressing threshold should be set.
In this embodiment, when one of the word line programming pulse voltages applied to the selected word line ends, if it is determined through the detection that the turn-on threshold of the to-be-programmed memory cell is less than or equal to the bit line pressurization threshold, the next pulse of the lower word line programming pulse voltage is continuously applied to the selected word line, but the bit line programming pulse voltage is not applied to the bit line corresponding to the to-be-programmed memory cell, and at this time, the voltage value of the bit line corresponding to the to-be-programmed memory cell is still maintained at about 0V, so that the next pulse of the word line programming pulse voltage can sufficiently charge the to-be-programmed memory cell.
S202, detecting whether the conduction threshold value of the memory cell to be programmed in the selected word is smaller than a first check voltage, if not, executing a step 203, and if so, executing a step 204.
S203, applying a cut-off voltage to the bit line corresponding to the memory cell to be programmed.
In this embodiment, when one of the programming pulses in the word line programming pulse voltage applied to the selected word line is ended, if the on threshold of the to-be-programmed memory cell is not only equal to or greater than the bit line stressing threshold but also equal to or greater than the first verifying voltage, that is, the to-be-programmed memory cell has completed the first programming operation, the off voltage is applied to the bit line corresponding to the to-be-programmed memory cell to end the programming operation on the to-be-programmed memory cell.
Specifically, the off-state voltage may be typically 1.8V, and when the off-state voltage is applied to the bit line corresponding to the memory cell to be programmed, the same off-state voltage is applied to the gate of the switching device (the source of the switching device is connected to the bit line corresponding to the memory cell to be programmed and is used for controlling the on/off of the bit line) connected to the upper end of the bit line, so as to turn off the switching device (e.g., the field effect transistor), thereby making it impossible to perform the programming operation on all the memory cells to be programmed corresponding to the bit line.
S204, applying the next pulse in the word line programming pulse voltage to the selected word line, and simultaneously applying the first pulse in the bit line programming pulse voltage to the bit line corresponding to the memory cell to be programmed, wherein the voltage value of each pulse in the bit line programming pulse voltage sequentially increases, the increasing amplitude is smaller than the increasing amplitude of the pulse in the word line programming pulse voltage corresponding to the pulse, the period and the pulse width of the bit line programming pulse voltage and the word line programming pulse voltage are the same, and the voltage value of the first pulse in the bit line programming pulse voltage is smaller than the increasing amplitude of the pulse in the word line programming pulse voltage corresponding to the bit line programming pulse voltage.
It can be understood that when the word line programming pulse voltage is applied to the gate of the memory cell to be programmed, if a voltage greater than zero is applied to the bit line corresponding to the memory cell to be programmed at the same time, the substrate voltage of the memory cell to be programmed is increased, so that the voltage difference between the gate and the substrate of the memory cell to be programmed is reduced, the increase of the word line programming pulse voltage to the turn-on threshold of the memory cell to be programmed is reduced, and the effect of slowing down the programming speed of the memory cell to be programmed is achieved.
Therefore, in this embodiment, when the conduction threshold of the memory cell to be programmed is greater than or equal to the bit line applied threshold and less than the first verify voltage, the first pulse of the bit line programming pulse voltages is applied to the bit line corresponding to the memory cell to be programmed while the next pulse of the word line programming pulse voltages is applied to the selected word line.
Further, in this embodiment, the voltage value of each pulse in the bit line programming pulse voltages sequentially increases, and the increasing amplitude is smaller than the increasing amplitude of the pulse in the word line programming pulse voltage corresponding to the pulse value, the period and the pulse width of the bit line programming pulse voltage and the word line programming pulse voltage are the same, and the voltage value of the first pulse in the bit line programming pulse voltage is smaller than the increasing amplitude of the pulse in the word line programming pulse voltage corresponding to the pulse value
It can be understood that, since the voltage values of the pulses in the word line programming pulse voltage are sequentially increased, if the voltage values of the respective pulses in the bit line programming pulse voltage are all equal, as the voltage value of the pulse in the word line programming pulse voltage is increased, the voltage difference between the pulse in the bit line programming pulse voltage and the pulse in the word line programming pulse voltage corresponding to the pulse in the bit line programming pulse voltage is increased, and thus the effect of the bit line programming pulse voltage on reducing the programming speed of the memory cell to be programmed is reduced. Therefore, in the embodiment, the voltage value of each pulse in the bit line programming pulse voltage is sequentially increased, so that the voltage difference between the pulse in the bit line programming pulse voltage and the pulse in the word line programming pulse voltage corresponding to the pulse in the bit line programming pulse voltage can be better controlled, and the control effect of the programming speed of the memory cell to be programmed is ensured. Of course, the sequentially increasing amplitude of the voltage value of each pulse in the bit line programming pulse voltages should be smaller than the increasing amplitude of the pulse in the word line programming pulse voltages corresponding to the pulse value of each pulse in the bit line programming pulse voltages, so as to ensure that the word line programming pulse voltages can perform effective programming operation on the memory cells to be programmed.
The following is illustrated by way of example in FIG. 2 b:
as shown in FIG. 2b, pulses No. 1-6 are the first 6 consecutive pulses in the word line programming pulse voltage, and pulses No. 7-9 are the first three consecutive pulses in the bit line programming pulse voltage, after pulse No. 3 ends, it is detected that the turn-on threshold of the memory cell to be programmed is greater than or equal to the bit line stressing threshold and less than the first verify voltage, and therefore, the first pulse in the bit line programming pulse voltage, i.e., pulse No. 7, is applied at the same time as pulse No. 4 is applied to reduce the programming speed of the memory cell to be programmed. The voltage value of pulse No. 7 must be smaller than the incremental amplitude of the corresponding pulse No. 4, i.e., Δ 1. Likewise, the incremental amplitude Δ 5 of pulse No. 8 must be less than the incremental amplitude Δ 2 of pulse No. 5, and the incremental amplitude Δ 6 of pulse No. 9 must be less than the incremental amplitude Δ 3 of pulse No. 6. In addition, fig. 2b exemplarily shows that Δ 1 ═ Δ 2 ═ Δ 3, and Δ 4 ═ Δ 5 ═ Δ 6. In actual operation, Δ 1, Δ 2, and Δ 3 may be equal or different, and similarly, Δ 4, Δ 5, and Δ 6 may be equal or different.
As shown in fig. 2b, when the pulses No. 5 and No. 6 are applied, the voltage difference between the gate voltage and the substrate voltage of the memory cell to be programmed is kept unchanged due to the existence of two incremental voltages Δ 5 and Δ 6 (because the bit line programming pulse voltage is applied to the bit line corresponding to the memory cell to be programmed to raise the substrate voltage of the memory cell to be programmed), thereby ensuring the control effect of the programming speed of the memory cell to be programmed. If there are no two incremental voltages Δ 5 and Δ 6, i.e. the voltage values of pulses No. 7, 8 and 9 are equal, the voltage difference between the gate voltage and the substrate voltage of the memory cell to be programmed is greater during the application of pulses No. 5 and 6, resulting in poor control of the programming speed of the memory cell to be programmed.
S205, when the pulse in the word line programming pulse voltage and the pulse in the bit line programming pulse voltage end at the same time, detecting whether the turn-on threshold of the to-be-programmed memory cell is greater than or equal to the first verify voltage, if so, executing step 206, and if not, executing step 207.
S206, no longer applying the bit line programming pulse voltage to the bit line corresponding to the memory cell to be programmed, but applying a cut-off voltage to the bit line corresponding to the memory cell to be programmed.
S207, continuously applying the word line programming pulse voltage and the bit line programming pulse voltage to the selected word line and the bit line corresponding to the memory cell to be programmed respectively, and returning to execute the step 206 until the conduction threshold value of the memory cell to be programmed is greater than or equal to the first verification voltage.
S208, the memory cells with the threshold value smaller than the second verifying voltage in all the memory cells to be programmed corresponding to the selected word line are taken as reprogramming units.
S209, under the condition that the bit line cut-off voltage is applied to the bit lines corresponding to the memory cells with the threshold value being larger than or equal to the second verifying voltage in all the memory cells to be programmed, carrying out the second programming operation on the re-programming cells.
In this embodiment, since the second programming operation is only performed on the re-programmed cell, it should be ensured that other to-be-programmed memory cells in the selected word line (i.e., the to-be-programmed memory cells with the threshold value equal to or greater than the second verifying voltage after the first programming operation) are not continuously programmed during the second programming operation, and therefore, in this embodiment, a bit line cut-off voltage is applied to the bit lines of the to-be-programmed memory cells with the threshold value equal to or greater than the second verifying voltage after the first programming operation.
The embodiment of the invention provides a programming method of a memory, which embodies a voltage application method of a second programming operation, realizes simple and effective prevention of a to-be-programmed memory cell with a threshold value larger than or equal to a second verification voltage after a first programming operation from being programmed in the second programming operation, embodies a first programming process, realizes effective control of the programming speed of a fast-programming to-be-programmed memory cell, reduces the maximum threshold difference value between the fast-programming to-be-programmed memory cell and a slow-programming to-be-programmed memory cell after the first programming is finished, and further reduces the threshold voltage distribution width of the to-be-programmed memory cell after the programming.
In addition to the above embodiments, the voltage values of the respective pulses in the bit line programming pulse voltage may be sequentially increased by equal magnitudes.
The benefits of this arrangement are: the hardware design difficulty and the manufacturing cost of the storage device are reduced.
EXAMPLE III
Fig. 3 is a structural diagram of a programming apparatus of a memory according to a third embodiment of the present invention. As shown in fig. 3, the apparatus includes: a first programming module 301, a memory cell screening module 302, and a second programming module 303, wherein:
a first programming module 301, configured to perform a first programming operation on a memory cell to be programmed in a selected word line, where a programming completion verification voltage corresponding to the first programming operation is a first verification voltage;
a memory cell screening module 302, configured to use a memory cell with a threshold value smaller than the second verification voltage among all memory cells to be programmed as a reprogramming unit;
the second programming module 303 is configured to perform a second programming operation on the re-programmed cell, where a program-completed verification voltage corresponding to the second programming operation is a second verification voltage, and the second verification voltage is greater than the first verification voltage.
The embodiment of the invention provides a programming device of a memory, which firstly performs a first programming operation on memory cells to be programmed in a selected word line through a first programming module 301, wherein a programming completion verification voltage corresponding to the first programming operation is a first verification voltage, then a memory cell screening module 302 is used for taking all memory cells to be programmed, of which the threshold value is smaller than a second verification voltage, as a reprogramming unit, and finally performs a second programming operation on the reprogramming unit through a second programming module 303, wherein the programming completion verification voltage corresponding to the second programming operation is a second verification voltage, and the second verification voltage is larger than the first verification voltage.
The device solves the technical defects that the existing method for reducing the threshold distribution width has poor effect of reducing the threshold voltage distribution width after the memory cell is programmed, and increases the hardware circuit complexity and the manufacturing cost of the memory, and realizes that the threshold distribution width of the memory cell after programming can be simply, conveniently and effectively reduced under the condition of not additionally arranging a hardware circuit, so that the voltage applied to unselected word lines during reading operation can be reduced, the read disturb phenomenon is weakened, and the reliability of the memory can be improved.
On the basis of the foregoing embodiments, the second programming module may specifically be configured to:
and performing a second programming operation on the re-programming unit under the condition that the bit line cut-off voltage is applied to the bit line corresponding to the memory unit with the threshold value being more than or equal to the second verifying voltage in all the memory units to be programmed.
On the basis of the above embodiments, the first programming module 301 may include:
the first voltage interpretation unit is used for applying word line programming pulse voltage to a selected word line and detecting whether the conduction threshold of a to-be-programmed memory cell in the selected word line is greater than or equal to a bit line pressurization threshold and smaller than a first check voltage or not when each pulse in the word line programming pulse voltage is ended, wherein the bit line pressurization threshold is smaller than the first check voltage;
a bit line programming pulse voltage applying unit, configured to apply a next pulse in the word line programming pulse voltages to the selected word line and apply a first pulse in the bit line programming pulse voltages to the bit line corresponding to the memory cell to be programmed at the same time if a turn-on threshold of the memory cell to be programmed is greater than or equal to a bit line pressurization threshold and less than a first verification voltage, where a voltage value of each pulse in the bit line programming pulse voltages sequentially increases and the increasing amplitude is less than an increasing amplitude of a pulse in the word line programming pulse voltages corresponding to the pulse, the cycle and pulse width of the bit line programming pulse voltages and the word line programming pulse voltages are the same, and a voltage value of the first pulse in the bit line programming pulse voltages is less than the increasing amplitude of the pulse in the word line programming pulse voltages corresponding to the bit line programming pulse voltages;
a second voltage judging unit for detecting whether the conduction threshold of the memory cell to be programmed is greater than or equal to the first verifying voltage when the pulse in the word line programming pulse voltage and the pulse in the bit line programming pulse voltage end at the same time each time;
a first off bit line unit, configured to apply an off voltage to a bit line corresponding to the to-be-programmed memory cell instead of applying the bit line programming pulse voltage to the bit line corresponding to the to-be-programmed memory cell if the turn-on threshold of the to-be-programmed memory cell is greater than or equal to the first verification voltage;
and the first returning unit is used for continuously applying the word line programming pulse voltage and the bit line programming pulse voltage to the selected word line and the bit line corresponding to the memory cell to be programmed respectively if the conduction threshold of the memory cell to be programmed is smaller than the first verifying voltage, and returning to detect whether the conduction threshold of the memory cell to be programmed is larger than or equal to the first verifying voltage or not when the pulse in the word line programming pulse voltage and the pulse in the bit line programming pulse voltage end at the same time each time until the conduction threshold of the memory cell to be programmed is larger than or equal to the first verifying voltage.
On the basis of the above embodiments, the first programming module 301 may further include:
and a second returning unit for applying a next pulse of the word line programming pulse voltage to the selected word line if the turn-on threshold of the memory cell to be programmed is less than the bit line pressurization threshold, and returning to perform the operation of applying the word line programming pulse voltage to the selected word line, and detecting whether the turn-on threshold of the memory cell to be programmed in the selected word line is greater than or equal to the bit line pressurization threshold and less than the first verification voltage at the end of each pulse of the word line programming pulse voltages.
On the basis of the above embodiments, the first programming module 301 may further include:
and a second off bit line unit for applying an off voltage to a bit line corresponding to the memory cell if the turn-on threshold of the memory cell to be programmed is greater than or equal to the first verify voltage.
On the basis of the above embodiments, the voltage values of the respective pulses in the bit line programming pulse voltage may be sequentially increased by the same magnitude.
The programming device of the memory provided by the embodiment of the invention can be used for executing the programming method of the memory provided by any embodiment of the invention, has corresponding functional modules and realizes the same beneficial effects.
Example four
Fig. 4 is a schematic structural diagram of a storage device according to a fourth embodiment of the present invention, as shown in fig. 4, the storage device includes a processor 40, a memory 41, an input device 42, and an output device 43; the number of processors 40 in the storage device may be one or more, and one processor 40 is taken as an example in fig. 4; the processor 40, the memory 41, the input device 42 and the output device 43 in the storage apparatus may be connected by a bus or other means, and the bus connection is exemplified in fig. 4.
The memory 41, which is a computer-readable storage medium, may be used to store software programs, computer-executable programs, and modules, such as modules corresponding to the programming method of the memory in the embodiment of the present invention (for example, the first programming module 301, the memory cell screening module 302, and the second programming module 303 in the programming apparatus of the memory). The processor 40 executes various functional applications of the storage device and data processing by executing software programs, instructions, and modules stored in the memory 41, that is, implements the above-described memory programming method.
The memory 41 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 41 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 41 may further include memory located remotely from processor 40, which may be connected to a storage device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 42 is operable to receive input numeric or character information and to generate key signal inputs relating to user settings and function controls of the memory device. The output device 43 may include a display device such as a display screen.
EXAMPLE five
Fifth, an embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform the method according to the fifth embodiment of the present invention. Namely: performing a first programming operation on a memory cell to be programmed in a selected word line, wherein a programming completion verification voltage corresponding to the first programming operation is a first verification voltage; taking all memory cells with the threshold value smaller than the second verifying voltage in the memory cells to be programmed as reprogramming units; and performing a second programming operation on the re-programmed cell, wherein a programming completion verification voltage corresponding to the second programming operation is a second verification voltage, and the second verification voltage is greater than the first verification voltage.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method of programming a memory, comprising:
performing a first programming operation on a memory cell to be programmed in a selected word line, wherein a programming completion verification voltage corresponding to the first programming operation is a first verification voltage;
taking all the memory cells with the threshold value smaller than the second verifying voltage in the memory cells to be programmed as reprogramming units;
and performing a second programming operation on the reprogramming unit, wherein a programming completion verification voltage corresponding to the second programming operation is the second verification voltage, the second verification voltage is greater than the first verification voltage, the first verification voltage meets the requirement, and after the first programming operation, the second verification voltage is less than or equal to an intermediate voltage value of the threshold distribution width of the current memory cell to be programmed.
2. The method of claim 1, wherein performing the second programming operation on the reprogramming unit comprises:
and performing a second programming operation on the re-programming unit under the condition of applying a bit line cut-off voltage to bit lines corresponding to the memory units with the threshold value being more than or equal to a second verifying voltage in all the memory units to be programmed.
3. The method according to claim 1, wherein performing a first program operation on the memory cells to be programmed in the selected word line, wherein a program completion verify voltage corresponding to the first program operation is a first verify voltage, comprises:
applying word line programming pulse voltages to a selected word line, and detecting whether a conduction threshold of a memory cell to be programmed in the selected word line is greater than or equal to a bit line pressurization threshold and less than a first verification voltage at the end of each pulse in the word line programming pulse voltages, wherein the bit line pressurization threshold is less than the first verification voltage;
if the conduction threshold of the memory cell to be programmed is greater than or equal to the bit line pressurization threshold and less than the first verification voltage, applying the next pulse in the word line programming pulse voltages to the selected word line, and simultaneously applying the first pulse in the bit line programming pulse voltages to the bit line corresponding to the memory cell to be programmed, wherein the voltage value of each pulse in the bit line programming pulse voltages sequentially increases and the increasing amplitude is less than the increasing amplitude of the pulse in the word line programming pulse voltages corresponding to the pulse values, the period and the pulse width of the bit line programming pulse voltages are the same, and the voltage value of the first pulse in the bit line programming pulse voltages is less than the increasing amplitude of the pulse in the word line programming pulse voltages corresponding to the bit line programming pulse voltages;
detecting whether the conduction threshold of the memory cell to be programmed is greater than or equal to the first verification voltage each time a pulse in the word line programming pulse voltage and a pulse in the bit line programming pulse voltage end simultaneously;
if the conduction threshold value of the memory cell to be programmed is greater than or equal to the first verification voltage, the bit line programming pulse voltage is not applied to the bit line corresponding to the memory cell to be programmed any more, and a cut-off voltage is applied to the bit line corresponding to the memory cell to be programmed;
if the conduction threshold of the to-be-programmed memory cell is smaller than the first verification voltage, continuing to apply the word line programming pulse voltage and the bit line programming pulse voltage to the selected word line and the bit line corresponding to the to-be-programmed memory cell respectively, and returning to execute the operation of detecting whether the conduction threshold of the to-be-programmed memory cell is larger than or equal to the first verification voltage when the pulse in the word line programming pulse voltage and the pulse in the bit line programming pulse voltage end at the same time each time until the conduction threshold of the to-be-programmed memory cell is larger than or equal to the first verification voltage.
4. The method of claim 3, further comprising:
and if the conduction threshold of the memory cell to be programmed is smaller than the bit line pressurization threshold, returning to execute the operation of applying the word line programming pulse voltage to the selected word line and detecting whether the conduction threshold of the memory cell to be programmed in the selected word line is larger than or equal to the bit line pressurization threshold and smaller than a first verification voltage or not at the end of each pulse in the word line programming pulse voltage.
5. The method of claim 3, further comprising:
and if the turn-on threshold value of the memory cell to be programmed is greater than or equal to the first verifying voltage, applying a cut-off voltage to the bit line corresponding to the memory cell to be programmed.
6. The method of claim 3 or 4, wherein the voltage values of the respective pulses of the bit line programming pulse voltages are sequentially incremented by equal magnitudes.
7. A programming apparatus for a memory, comprising:
the first programming module is used for carrying out first programming operation on a memory cell to be programmed in a selected word line, and a programming completion verifying voltage corresponding to the first programming operation is a first verifying voltage;
the memory cell screening module is used for taking all memory cells with threshold values smaller than the second verification voltage in the memory cells to be programmed as reprogramming units;
a second programming module, configured to perform a second programming operation on the reprogramming unit, where a programming completion verification voltage corresponding to the second programming operation is the second verification voltage, and the second verification voltage is greater than the first verification voltage; the first verify voltage is satisfied such that, after a first program operation, the second verify voltage is less than or equal to an intermediate voltage value of a threshold distribution width of a memory cell currently to be programmed.
8. The apparatus of claim 7, wherein the second programming module is specifically configured to:
and performing a second programming operation on the re-programming unit under the condition of applying a bit line cut-off voltage to bit lines corresponding to the memory units with the threshold value being more than or equal to a second verifying voltage in all the memory units to be programmed.
9. A storage device, the storage device comprising:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement a method of programming the memory of any of claims 1-6.
10. A storage medium containing computer-executable instructions for performing a method of programming the memory of any one of claims 1-6 when executed by a computer processor.
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