KR20070110634A - Method for erasing flash memory device - Google Patents

Abstract

A method for erasing a flash memory device is provided to improve erase speed and to reduce P/E(Program/Erase) cycling damage due to an erase bias voltage by performing erase operation by changing the erase bias voltage according to the erase speed of a memory cell. A bias voltage is applied to a block on a semiconductor substrate to perform pre-erase operation(S401). It is checked whether a slow erase memory cell is among the pre-erased cells(S402). When the slow erase memory cell exists, erase operation is performed again by adding a first voltage to the erase bias voltage. In case of erase pass, the erase operation ends(S404). When the slow erase memory cell does not exist, erase operation is performed again by adding a second voltage higher than the first voltage to the erase bias voltage(S407).

Description

Method for erasing flash memory device

1 is a circuit diagram showing a general NAND flash memory device

2 is a diagram illustrating a slow erase fail phenomenon due to an erase speed difference.

3 is a view illustrating an erase state fail phenomenon occurring after P / E (Program / Erase) cycling

4 is a flowchart illustrating an erase method of a flash memory device according to an exemplary embodiment of the present invention.

5 is a waveform diagram showing an erase voltage according to the erase method of the present invention shown in FIG.

FIG. 6 is a view illustrating a change in threshold voltage distribution according to the erasing method of the present invention shown in FIG. 4.

The present invention relates to a method of erasing a flash memory device, and more particularly, to a method of erasing a flash memory device for improving the erase speed and reducing damage caused by P / E cycling.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that data can be stored without being erased even when power is not supplied. In order to develop a large-capacity memory device capable of storing a large number of data, high integration technology of memory cells has been developed. To this end, a NAND flash memory device in which a plurality of memory cells are connected in series to form a string and a plurality of strings form a memory cell array has been proposed.

1 is a circuit diagram illustrating a general NAND flash memory device.

First to sixteenth memory cells c1 to c16 are connected in series to the unit string. The drain of the first memory cell c1 is connected to the first bit line BL1 through the drain select transistor d, and the source of the sixteenth memory cell c16 is connected to the common source line through the source select transistor s. (CSL: Common Source Line). In addition, a plurality of such unit strings are provided to form a block of a flash memory device.

The memory cells of the NAND flash memory device include a current path formed between a source and a drain on a semiconductor substrate, and a floating gate and a control gate separated by insulating layers on the semiconductor substrate.

The program operation of the NAND flash memory cell is performed by injecting electrons from the semiconductor substrate into the floating gate in FN tunneling method to increase the threshold voltage, and the erase operation applies a voltage of 19 to 20V to the semiconductor substrate and 0V to the word line. It is achieved by lowering the threshold voltage by applying a word line voltage of to emit electrons injected into the floating gate to the bottom of the substrate.

Since the NAND flash memory is a block erase method in block units, a slow erase fail occurs when there is a slow erase memory cell having a slow erase speed in the block.

FIG. 2 is a diagram illustrating a slow erase fail phenomenon due to a difference in erase rates between cells. A dotted line shows a change in threshold voltage distribution when a slow erase fail is generated, and a solid line shows threshold voltage distribution of a normal erase cell.

In addition, the erase threshold voltage is due to P / E cycling damage in which electrons are trapped in the tunnel oxide layer under the floating gate due to a high erase bias of 19 to 20 V during program and erase cycling. This increase causes an erase status fail.

FIG. 3 is a diagram illustrating an erase state fail after P / E cycling, in which a dotted line shows a threshold voltage distribution of an erase cell when an erase state fails due to P / E cycling, and a solid line indicates normal erase. The threshold voltage distribution of the cell is shown.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and the erase speed is improved by changing the erase bias voltage according to the erase speed of the memory cell, thereby improving the erase speed and increasing the P / P due to the high erase bias voltage. An object of the present invention is to provide an erase method of a flash memory device for reducing E cycling damage.

An erase method of a flash memory device according to an embodiment of the present invention includes a first step of applying a predetermined erase bias voltage to a predetermined block of a semiconductor substrate to erase the first step, and verifying whether a slow erase memory cell is present among the erased cells. In the second step, when the slow erase memory cell is present, the erase voltage is added to the erase bias voltage, and the erase voltage is erased again. When the erase pass is performed, the erase operation is terminated and erased. A third step of returning after the second step and adding a second voltage greater than the first voltage to the erase bias voltage if the slow erase memory cell does not exist, and then performing an erase operation to terminate the erase operation. Include.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

4 is a flowchart illustrating an erase method of a flash memory device according to an exemplary embodiment of the present invention. The erase operation of the memory device, which will be described below, is performed in units of blocks.

An erase process of the flash memory device will be described with reference to FIG. 4. First, pre-erase is performed on memory cells included in a corresponding block to be erased (S401).

When an erase operation is started by a predetermined control signal, a block to be erased is designated. In order to erase the specified block, a predetermined erase bias voltage (Verase), for example, a voltage of 17 V is applied to the substrate for one pulse period (ie, one cycle), and 0 V is applied to the word lines of the memory cells included in the block. A pre-erase is performed by applying a word line voltage of.

Here, the erase bias voltage Verase and the word line voltage are not limited thereto. The erase bias voltage Verase and the word line voltage may be appropriately set according to a product. However, the erase bias voltage Verase may be 19 to 20 V applied to the substrate during the erase operation of the conventional NAND flash memory device. Set the value smaller than the voltage of.

Then, the slow erase memory cell verification is performed to verify whether the slow erase memory cell exists in the block (S402).

During one pulse period, a positive slow erase verify voltage, for example, a voltage of 0.5 V is applied to a word line of the corresponding memory cell to be verified, and the corresponding memory cell is read. At this time, a bias condition other than the voltage applied to the word line of the memory cell is the same as a normal read operation. That is, a voltage of 4.5 V is applied to the unselected word line, a voltage of 0 V is applied to the selected bit line, and a voltage of 1 V is applied to the unselected bit line, respectively, and 4.5 V is applied to the drain select line and the source select line. The voltage of not going.

Therefore, since all memory cells existing in the same string as the corresponding memory cell are turned on, when the threshold voltage of the corresponding memory cell is less than 0.5V, the turn-off state of the corresponding memory cell is read and the threshold voltage of the corresponding memory cell is 0.5V. If abnormal, the turn-on state of the memory cell is read. The slow erase memory cell verification process is sequentially performed for all memory cells in a block. In this case, if there is a memory cell read in the turned-on state in the block, it is assumed that the slow erase memory cell exists in the block.

The reason why the slow erase verify voltage is 0.5V instead of 0V is that since the line erase is performed while a low erase bias voltage (Verase) of 17V is applied to the substrate, the memory cells are not sufficiently erased and the threshold voltage distribution is positive. This is because it is shifted in the direction.

As a result of the verification in step S402, if a slow erase memory cell exists in the block (case A), after a first voltage, for example, a voltage of 1V is added to the erase bias voltage Verase (S403), one pulse section An erase bias voltage Verase of 18V is applied to the substrate during a period of time (ie, one cycle), and a voltage of 0V is applied to the word lines of the memory cells existing in the corresponding block (S404).

Thereafter, erase verification is performed on the memory cells in the block (S405).

The memory cell is read while a voltage of 0 V is applied to the word line of the memory cell to be erase verified during one pulse period. At this time, a bias condition other than the voltage applied to the word line of the corresponding memory cell is the same as a normal read operation. That is, a voltage of 4.5 V is applied to the unselected word line, a voltage of 0 V is applied to the selected bit line, and a voltage of 1 V is applied to the unselected bit line, respectively, and 4.5 V is applied to the drain select line and the source select line. The voltage of not going.

Therefore, all memory cells present in the same string as the corresponding memory cell are turned on. When the threshold voltage of the corresponding memory cell is less than 0 V, the turn-off state of the corresponding memory cell is read. When the threshold voltage of the corresponding memory cell is 0 V or higher. The turn-on state of the memory cell is read. The erase verification process is sequentially performed on all memory cells in the block. In this case, when all the memory cells in the block are read in the turned off state, it is regarded as an erase pass.

Then, when the erase fails in step S405, the process returns to step S403 to add the first voltage to the erase bias voltage Verase, and then performs the erase step of S404 and the erase verify step of S405 again. These operations S403 to S405 are performed until an erase pass is made in step S405 or an erase fail is repeated a predetermined number of times, for example, twice. That is, although not shown, when the erase verification result of step S405 fails more than once, the block is regarded as an invalid block and the erase operation is terminated.

On the other hand, if the slow erase memory cell does not exist in the block (step B) as a result of the verification in step S402, a second voltage larger than the first voltage, for example, 1.5V, is added to the erase bias voltage Verase. In operation S406, an erase bias voltage Verase, for example, 18.5 V is applied to the substrate for one pulse period (that is, one cycle), and a voltage of 0 V is applied to the word lines of the memory cells existing in the block. (erase) and the erase operation is terminated (S407).

FIG. 5 is a waveform diagram illustrating an erase voltage according to the erase method of FIG. 4, and FIG. 6 is a view illustrating a change in threshold voltage distribution according to the erase method of the present invention shown in FIG. 4.

5 and 6, when the threshold voltage of the erase cell is 1 V when a first pulse voltage of 17 V is applied as the initial value of the erase bias voltage Verase, the threshold voltage is slow erase. This cell is case A because it is larger than the memory cell verification voltage of 0.5V. Therefore, the erase bias voltage Verase of 18V and 19V is applied as a single pulse, respectively, and the threshold voltage of the memory cell becomes -1V.

Similarly, if the threshold voltage of the erase cell is 0.4V when one pulse voltage of 17V is applied as the initial value of the erase bias voltage Verase and the line erase is 0.4V, the threshold voltage is 0.5 which is the slow erase memory cell verification voltage. Since it is less than V, this cell corresponds to case B. Therefore, an erase bias voltage Verase of 18.5 V is applied as a single pulse, so that the threshold voltage of the memory cell is -1 V.

According to the present invention, since the erase operation can be performed in two pulses or one pulse according to the erase speed by performing line erase and slow erase memory cell verification, the erase speed can be improved and the erase bias voltage can be reduced, so that P is erased. / E Cycling damage can be reduced.

As described above, the present invention has the following effects.

First, the pre- erase and slow erase memory cells are verified to classify the slow erase memory cells, and the slow erase cells and the other cells are erased by applying different erase bias voltages. The erase operation may be completed for all the memory cells including the erase operation. Therefore, the erase speed can be improved.

Second, since the erase bias is lower than the conventional erase bias, cycling damage can be reduced.

Third, since all of the slow erase cells are not balanced, a fail rate can be reduced.

Claims (7)

A first step of applying a predetermined erase bias voltage to a predetermined block of the semiconductor substrate to pre-erase; Verifying whether a slow erase memory cell exists among the pre- erased cells; If a slow erase memory cell is present, the second voltage is added to the erase bias voltage and then erased again. Then, the erase verification is performed to terminate the erase operation and erase fails. Then revert to And a third step of performing an erase operation by adding a second voltage greater than the first voltage to the erase bias voltage when the slow erase memory cell does not exist, and ending the erase operation. The erase method of claim 1, wherein when the erase verification result is erased more than a predetermined number of times, the corresponding block is regarded as an invalid block and the erase operation is terminated. The erase method of claim 2, wherein the predetermined number of times is twice. The flash memory device of claim 1, wherein in the second step, when a memory cell having a threshold voltage of 0.5 V or more is read by reading threshold voltages of the memory cells existing in the corresponding block, the slow erase memory cell is considered to exist. Erasing method. The erase method of claim 1, wherein the predetermined erase bias voltage is set to 17V. The erase method of claim 1, wherein the first voltage is set to 1V. The erase method of claim 1, wherein the second voltage is set to 1.5V.

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