CN108538333B - NAND flash memory read operation processing method and device and NAND storage equipment - Google Patents
NAND flash memory read operation processing method and device and NAND storage equipment Download PDFInfo
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- CN108538333B CN108538333B CN201710128834.4A CN201710128834A CN108538333B CN 108538333 B CN108538333 B CN 108538333B CN 201710128834 A CN201710128834 A CN 201710128834A CN 108538333 B CN108538333 B CN 108538333B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Abstract
The embodiment of the invention discloses a read operation processing method and device of a NAND flash memory and NAND storage equipment. The method is applied to a NAND memory device, the memory device comprises a plurality of word lines and a plurality of NAND memory units, each word line is respectively connected with the corresponding memory unit, and the method comprises the following steps: determining a memory cell to be read; adding a first voltage to two adjacent word lines of the word line corresponding to the memory cell to be read, wherein the first voltage is the voltage filtered by a filter; and applying a second voltage to the word line corresponding to the memory cell to be read, wherein the first voltage is greater than the second voltage. According to the embodiment of the invention, the voltage filtered by the filter is added to the two adjacent word lines of the word line corresponding to the memory cell to be read, and the fluctuation of the voltage on the two adjacent word lines is reduced by the filter, so that the fluctuation of the voltage on the word line corresponding to the memory cell to be read is reduced, and the accuracy of the reading operation is improved.
Description
Technical Field
The embodiment of the invention relates to a memory technology, in particular to a read operation processing method and device of a NAND flash memory and a NAND storage device.
Background
The NAND Flash is one kind of Flash memory and belongs to the field of non-volatile semiconductor memory. The NAND flash includes many data blocks, each of which is composed of many memory cells for reading and writing data.
As is well known, a semiconductor memory has a large number of memory cells arranged in an array, and a particular memory cell in the array is typically selected via a word-line (WL) and a pair of bit-lines (BL). Word lines are typically coupled to one or more control gates for each memory cell in a row. Since the turn-on characteristics of the control gate are similar to those of an NMOS, all memory cells are turned on when the word line coupled thereto has a high voltage (i.e., is activated). A bit line pair (BL pair) typically couples the storage point of each memory cell in a row to a sense amplifier. The memory cell at the intersection of the activated word line and bit line pair is the selected memory cell. The read-write erasing operation of the memory unit can be realized by controlling the high and low voltages of the word line and the bit line.
When the NAND flash realizes a read operation, as shown in fig. 1(a), if WLn is to be read, the most basic method is to apply a Vn voltage corresponding to the read operation to the selected WLn, and apply a Vm voltage higher than the other WLs, and the Vn voltage is provided by a charge pump inside the NAND flash chip. Further, in order to improve the accuracy of the read operation, it is necessary to reduce the vt distribution of the transistors, and a VmH mode is adopted in the prior art, and is implemented as shown in fig. 1(b), that is, a VmH voltage higher than Vm is applied to both WLn +1 and WLn-1 adjacent to the selected WLn, and Vm voltages are applied to other WLs, wherein the VmH voltage is greater than the Vm voltage, so that the load applied with the VmH voltage in fig. 1(b) is less than the load applied with the corresponding Vm voltage in fig. 1(a), and therefore, the voltage fluctuation (ripple) of VmH is greater, which causes WLn to be coupled by WLn +1 and WLn-1, and therefore, the ripple of WLn in fig. 1(b) is greater than the ripple of WLn in fig. 1(a), which in turn affects the accuracy of the result of the read operation on WLn in fig. 1 (b).
Disclosure of Invention
The embodiment of the invention provides a read operation processing method and device of a NAND flash memory and a NAND storage device, and aims to solve the problem that read operation accuracy is influenced due to large fluctuation of word line voltage during read operation in the prior art.
In a first aspect, an embodiment of the present invention provides a read operation processing method for a NAND flash memory, which is applied to a NAND memory device, where the NAND memory device includes a plurality of word lines and a plurality of NAND memory cells, and each word line is connected to a corresponding memory cell, where the method includes:
determining a memory cell to be read;
adding a first voltage to two adjacent word lines of the word line corresponding to the memory cell to be read, wherein the first voltage is the voltage filtered by a filter;
and applying a second voltage to the word line corresponding to the memory cell to be read, wherein the first voltage is greater than the second voltage.
Preferably, the filter is an RC filter.
In a second aspect, an embodiment of the present invention provides a read operation processing apparatus for a NAND flash memory, which is applied to a NAND memory device, where the NAND memory device includes a plurality of word lines and a plurality of NAND memory cells, and each word line is respectively connected to a corresponding memory cell, where the apparatus includes:
the determining module is used for determining a memory unit to be read;
the first voltage applying module is used for applying a first voltage to two adjacent word lines of the word line corresponding to the memory cell to be read, wherein the first voltage is the voltage filtered by the filter;
and the second voltage applying module is used for applying a second voltage to the word line corresponding to the memory cell to be read, wherein the first voltage is greater than the second voltage.
Preferably, the filter is an RC filter.
In a third aspect, an embodiment of the present invention provides a NAND memory device, where the NAND memory device includes a voltage source, firmware, a plurality of word lines, and a plurality of NAND memory cells, where each word line is connected to a corresponding memory cell, and the NAND memory device further includes a filter;
the voltage source is connected with each word line and used for providing corresponding voltage for each word line corresponding to the memory unit during reading operation;
the voltage source is also connected with each word line through the filter, and the filter is used for filtering before applying corresponding voltages to two adjacent word lines of the word line corresponding to the memory unit to be read;
the firmware includes a read operation processing device of the NAND flash memory as described above.
According to the embodiment of the invention, the voltage filtered by the filter is added to the two adjacent word lines of the word line corresponding to the memory cell to be read, and the fluctuation of the voltage on the two adjacent word lines is reduced by the filter, so that the fluctuation of the voltage on the word line corresponding to the memory cell to be read is reduced, and the accuracy of the reading operation is improved.
Drawings
FIG. 1 is a schematic diagram of a normal mode and a VmH mode in a read operation of a NAND flash of the prior art;
FIG. 2 is a flowchart of a read operation processing method of a NAND flash memory according to a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a read processing device of a NAND flash memory according to a second embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a NAND memory device in a third embodiment of the present invention;
fig. 5 is a circuit diagram of a filter according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 2 is a flowchart of a read operation processing method of a NAND flash memory according to a first embodiment of the present invention, which is applicable to a case of read operation processing of a NAND flash memory, and is applied to a NAND memory device including a plurality of word lines and a plurality of NAND memory cells, wherein each word line is respectively connected to a corresponding memory cell. The method may be performed by an apparatus having a read operation processing function of a NAND flash memory, which may be implemented in software and/or hardware, such as firmware in a NAND memory device. The method provided by the first embodiment of the invention specifically comprises the following steps:
and S110, determining a memory cell to be read.
In the NAND flash memory chip, memory units are arranged in an array, each row comprises a plurality of memory units, a control gate of each memory unit is connected with a word line, and the memory units are read and written by controlling the word lines. Specifically, the memory cell to be read may be determined by a physical address.
And S120, adding a first voltage to two adjacent word lines of the word line corresponding to the memory cell to be read, wherein the first voltage is the voltage filtered by the filter.
Specifically, in the VmH mode, in order to reduce vt distribution of the transistor, a higher voltage, for example, a VmH voltage, needs to be applied to two adjacent word lines of the word line corresponding to the selected memory cell, so that the problem of a larger voltage ripple on the word line corresponding to the selected memory cell described in the background art is caused, and accuracy of the read result is affected. Therefore, in the first embodiment of the present invention, the VmH voltage is filtered by the filter, and then applied to two adjacent word lines of the word line corresponding to the selected memory cell, so as to filter out the high frequency component in the voltage and reduce the voltage ripple.
In one example, the first voltage is, for example, 6V or 7V, which is a high voltage and needs to be provided by a charge pump in the memory device chip. Since the selected memory cell is always changed, and therefore, the memory cell to which the first voltage is applied is also changed, the switch can be used to control the application of the required voltage to the corresponding memory cell in the specific implementation.
Preferably, the filter is an RC filter.
S130, adding a second voltage to the word line corresponding to the memory cell to be read, wherein the first voltage is greater than the second voltage.
After the memory cell to be read is determined, the read operation is performed by controlling the corresponding word line voltage, specifically, applying a second voltage thereto, for example, the second voltage is a Vn voltage, in one example, 0.5V, which is a low voltage.
According to the embodiment of the invention, the voltage filtered by the filter is added to the two adjacent word lines of the word line corresponding to the memory cell to be read, and the fluctuation of the voltage on the two adjacent word lines is reduced by the filter, so that the fluctuation of the voltage on the word line corresponding to the memory cell to be read is reduced, and the accuracy of the reading operation is improved.
Example two
Fig. 3 is a schematic structural diagram of a data block processing apparatus of a NAND flash memory according to a second embodiment of the present invention, where the apparatus is applied to a NAND memory device, the NAND memory device includes a plurality of word lines and a plurality of NAND memory cells, and each word line is respectively connected to a corresponding memory cell, and the apparatus specifically includes:
a determining module 10, configured to determine a memory cell to be read;
a first voltage applying module 11, configured to apply a first voltage to two word lines adjacent to a word line corresponding to the memory cell to be read, where the first voltage is a voltage filtered by a filter;
and a second voltage applying module 12, configured to apply a second voltage to a word line corresponding to the memory cell to be read, where the first voltage is greater than the second voltage.
Further, the filter is an RC filter.
According to the embodiment of the invention, the voltage filtered by the filter is added to the two adjacent word lines of the word line corresponding to the memory cell to be read, and the fluctuation of the voltage on the two adjacent word lines is reduced by the filter, so that the fluctuation of the voltage on the word line corresponding to the memory cell to be read is reduced, and the accuracy of the reading operation is improved.
EXAMPLE III
Fig. 4 is a schematic structural diagram of a NAND memory device in a third embodiment of the present invention, and as shown in the figure, the NAND memory device 4 includes: a plurality of memory cells 40, a plurality of wordlines 41 connected to corresponding memory cells, a filter 42, a voltage source 43, and firmware 44.
Wherein, the voltage source 43 is connected to each word line 41, and is configured to provide a voltage corresponding to a read operation for each word line 41 corresponding to the memory cell 40, for example, provide a second voltage for the selected memory cell n to be read, so as to implement the read operation, for example, the second voltage is a Vn voltage, in an example, the voltage is 0.5V, and belongs to a low voltage; memory cells other than the two memory cells n +1 and n-1 adjacent to the memory cell n to be read are supplied with a Vm voltage, for example, 5V or 6V. The voltage source 43 may be a charge pump in the memory device chip.
The voltage source 43 is also connected to each word line via a filter 42, wherein the filter 42 is used for filtering before applying a voltage to two word lines adjacent to the word line corresponding to the memory cell to be read. In the above example, the voltage source 43 supplies a first voltage, i.e. the VmH voltage, e.g. 6V or 7V, higher than the Vm voltage, to the memory cell n +1 and the memory cell n-1 via the filter 42. The VmH voltage is filtered by the filter 42 to remove high frequency noise and reduce voltage fluctuations, thereby improving data reading accuracy.
In one embodiment, the voltage on the word line may be provided by a charge pump in the memory device chip, and the charge pump may provide the voltage required by the corresponding memory cell in different modes, or may provide the voltages required by the plurality of corresponding charge pumps in the same mode. For example, in embodiments of the present invention, Vm and VmH voltages may be provided by two charge pumps, respectively. Further, which word lines are supplied with the Vn voltage and which word lines are supplied with the Vm and VmH voltages can be implemented by programming in firmware cooperating with circuitry in the device, e.g., controlled by switches on the word lines. In particular, the VmH voltage is provided through a filter and then applied to the corresponding word line.
Specifically, the firmware 44 includes a read operation processing device of a NAND flash memory, the device including:
the determining module is used for determining a memory unit to be read;
the first voltage applying module is used for applying a first voltage to two adjacent word lines of the word line corresponding to the memory cell to be read, wherein the first voltage is the voltage filtered by the filter;
and the second voltage applying module is used for applying a second voltage to the word line corresponding to the memory cell to be read, wherein the first voltage is greater than the second voltage.
Preferably, the filter 42 is an RC filter, and as shown in fig. 5, the parameters of the resistor R and the capacitor C can be set as required.
According to the NAND memory device provided by the embodiment of the invention, the filter is added, the filter filters the NAND memory device, and then the corresponding voltages are added to the two adjacent word lines of the word line corresponding to the memory cell to be read, and the filter reduces the voltage fluctuation on the two adjacent word lines, so that the voltage fluctuation on the word line corresponding to the memory cell to be read is reduced, and the accuracy of the reading operation is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (5)
1. A read operation processing method of a NAND flash memory is applied to a NAND storage device, the storage device comprises a plurality of word lines and a plurality of NAND memory units, and each word line is respectively connected with the corresponding memory unit, and the method is characterized by comprising the following steps:
determining a memory cell to be read;
adding a first voltage to two adjacent word lines of the word line corresponding to the memory cell to be read, wherein the first voltage is the voltage of the high-frequency component in the voltage filtered by a filter;
applying a second voltage to the word line corresponding to the memory cell to be read, wherein the first voltage is greater than the second voltage;
providing a third voltage to word lines corresponding to memory cells other than two memory cells adjacent to the memory cell to be read and the memory cell to be read; the third voltage is less than the first voltage and greater than the second voltage.
2. The method of claim 1, wherein the filter is an RC filter.
3. A read operation processing device of a NAND flash memory, which is applied to a NAND memory device, wherein the NAND memory device comprises a plurality of word lines and a plurality of NAND memory units, and each word line is respectively connected with a corresponding memory unit, the device is characterized by comprising:
the determining module is used for determining a memory unit to be read;
the first voltage applying module is used for applying a first voltage to two adjacent word lines corresponding to the memory cell to be read, wherein the first voltage is the voltage obtained after high-frequency components in the voltage are filtered by a filter;
the second voltage applying module is used for applying a second voltage to the word line corresponding to the memory cell to be read, wherein the first voltage is greater than the second voltage;
the apparatus is further configured to: providing a third voltage to word lines corresponding to memory cells other than two memory cells adjacent to the memory cell to be read and the memory cell to be read; the third voltage is less than the first voltage and greater than the second voltage.
4. The apparatus of claim 3, wherein the filter is an RC filter.
5. A NAND memory device, the memory device comprising a voltage source, firmware, a plurality of word lines and a plurality of NAND memory cells, each word line being connected to a corresponding memory cell, the memory device further comprising a filter;
the voltage source is connected with each word line and used for providing corresponding voltage for each word line corresponding to the memory unit during reading operation;
the voltage source is also connected with each word line through the filter, and the filter is used for filtering before applying corresponding voltages to two adjacent word lines of the word line corresponding to the memory unit to be read;
the firmware includes a read operation processing device of the NAND flash memory according to claim 3 or 4.
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| EP3915115B1 (en) | 2019-11-28 | 2023-07-19 | Yangtze Memory Technologies Co., Ltd. | Methods of enhancing speed of reading data from memory device |
| CN114203236A (en) * | 2021-12-10 | 2022-03-18 | 北京得瑞领新科技有限公司 | Method and device for applying data reading operation voltage of NAND flash memory |
| CN117809708A (en) * | 2024-02-29 | 2024-04-02 | 浙江力积存储科技有限公司 | Memory array and method for improving data reading accuracy of memory array |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123115A (en) * | 2006-08-11 | 2008-02-13 | 松下电器产业株式会社 | Semiconductor memory device |
| CN101866694A (en) * | 2009-04-14 | 2010-10-20 | 海力士半导体有限公司 | Method of performing read operation of nonvolatile memory device |
| CN101989457A (en) * | 2009-08-04 | 2011-03-23 | 上海华虹Nec电子有限公司 | Nonrolatile storage system capable of reducing filter capacitor |
| CN103177763A (en) * | 2011-12-21 | 2013-06-26 | 爱思开海力士有限公司 | Reading method of non-volatile memory device |
| CN103811072A (en) * | 2012-11-15 | 2014-05-21 | 北京兆易创新科技股份有限公司 | Reading method and system of high-reliability NAND Flash |
| CN205845517U (en) * | 2016-06-07 | 2016-12-28 | 四川省豆萁科技股份有限公司 | Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4012151B2 (en) * | 2002-02-28 | 2007-11-21 | 株式会社ルネサステクノロジ | Nonvolatile semiconductor memory device |
| KR100748553B1 (en) * | 2004-12-20 | 2007-08-10 | 삼성전자주식회사 | Apparatus and method for generating ripple-free high voltage and semiconductor memory device having the same |
-
2017
- 2017-03-06 CN CN201710128834.4A patent/CN108538333B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123115A (en) * | 2006-08-11 | 2008-02-13 | 松下电器产业株式会社 | Semiconductor memory device |
| CN101866694A (en) * | 2009-04-14 | 2010-10-20 | 海力士半导体有限公司 | Method of performing read operation of nonvolatile memory device |
| CN101989457A (en) * | 2009-08-04 | 2011-03-23 | 上海华虹Nec电子有限公司 | Nonrolatile storage system capable of reducing filter capacitor |
| CN103177763A (en) * | 2011-12-21 | 2013-06-26 | 爱思开海力士有限公司 | Reading method of non-volatile memory device |
| CN103811072A (en) * | 2012-11-15 | 2014-05-21 | 北京兆易创新科技股份有限公司 | Reading method and system of high-reliability NAND Flash |
| CN205845517U (en) * | 2016-06-07 | 2016-12-28 | 四川省豆萁科技股份有限公司 | Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage |
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