CN108538333A - Read operation processing method, device and the NAND memory device of nand flash memory - Google Patents
Read operation processing method, device and the NAND memory device of nand flash memory Download PDFInfo
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- CN108538333A CN108538333A CN201710128834.4A CN201710128834A CN108538333A CN 108538333 A CN108538333 A CN 108538333A CN 201710128834 A CN201710128834 A CN 201710128834A CN 108538333 A CN108538333 A CN 108538333A
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- voltage
- wordline
- memory cell
- read
- memory
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Abstract
The embodiment of the invention discloses read operation processing method, device and the NAND memory devices of a kind of nand flash memory.Wherein, the method is applied to NAND memory device, and the storage device includes a plurality of wordline and multiple nand memory units, and every wordline is connected with corresponding memory cell respectively, the method includes：Determine memory cell to be read；Add first voltage for two adjacent wordline of wordline corresponding with the memory cell to be read, wherein first voltage is the filtered voltage of filtered device；Add second voltage for the corresponding wordline of the memory cell to be read, wherein first voltage is more than second voltage.The embodiment of the present invention for two adjacent wordline of wordline corresponding with memory cell to be read by adding the filtered voltage of filtered device, reduce the fluctuation of voltage in two adjacent wordline by filter, to reduce the fluctuation of voltage in the corresponding wordline of memory cell to be read, to improve the accuracy of read operation.
Description
Technical field
The present embodiments relate to memory technology more particularly to a kind of read operation processing method of nand flash memory, devices
And NAND memory device.
Background technology
NAND flash are one kind of Flash memories, belong to nonvolatile semiconductor memory.NAND flash include very
More data blocks, each data block is made of lots of memory unit, for reading and writing data.
It is well known that semiconductor memory, which has, is arranged in a large amount of memory cells of array, one specifically deposits in array
Storage unit is usually chosen via a wordline (word-line, WL) and a pair of bit lines (bit-line, BL).Wordline usually couples
One or more control gates of each memory cell in a line.Since the on state characteristic of control gate is similar to NMOS, when
When the wordline of coupling thereon has high voltage (that is, being activated, activate), all memory cells can be switched on.Position
Line is to the storage o'clock of each memory cell in (BL pair) usually one row of coupling to a sensing amplifier.Positioned at the word being activated
Line and the memory cell in a crosspoint of bit line pair are selected memory cells.By the height for controlling wordline and bit line
Low-voltage may be implemented the read-write to memory cell and wipe operation.
When NAND flash realize read operation, as shown in Fig. 1 (a), to read WLn, then most basic method is to selected
WLn when adding for read operation corresponding Vn voltages, other WL add higher Vm voltages by comparison, and be by NAND
What the charge pump inside flash chip provided.Further, it in order to improve the accuracy of read operation, needs to reduce transistor
Vt is distributed, and uses VmH patterns in the prior art, shown in realization such as Fig. 1 (b) of the pattern, i.e., adjacent to selected WLn
WLn+1 and WLn-1 adds VmH voltages more higher than Vm, other WL to add Vm voltages, wherein and VmH voltages are greater than Vm voltages, that
In Fig. 1 (b) plus the load of VmH voltages is less than corresponding plus Vm voltages load in Fig. 1 (a), so the voltage fluctuation of VmH
(ripple) larger, cause WLn to be coupled with WLn-1 by WLn+1, it is therefore, corresponding in ripple ratio Fig. 1 (a) of WLn in Fig. 1 (b)
The ripple of WLn is big, then influences the result accuracy that read operation is carried out to WLn in Fig. 1 (b).
Invention content
The embodiment of the present invention provides a kind of read operation processing method, device and the NAND memory device of nand flash memory, with solution
Certainly in the prior art read operation when because word line voltage fluctuation it is larger due to influence read operation accuracy the problem of.
In a first aspect, an embodiment of the present invention provides a kind of read operation processing method of nand flash memory, deposited applied to NAND
Store up equipment, the storage device includes a plurality of wordline and multiple nand memory units, every wordline respectively with corresponding storage
Device unit connects, wherein the method includes：
Determine memory cell to be read；
Add first voltage for two adjacent wordline of wordline corresponding with the memory cell to be read, wherein the
One voltage is the filtered voltage of filtered device；
Add second voltage for the corresponding wordline of the memory cell to be read, wherein first voltage is more than the second electricity
Pressure.
Preferably, the filter is RC filters.
Second aspect, an embodiment of the present invention provides a kind of read operation processing units of nand flash memory, are deposited applied to NAND
Store up equipment, the storage device includes a plurality of wordline and multiple nand memory units, every wordline respectively with corresponding storage
Device unit connects, wherein described device includes：
Determining module, for determining memory cell to be read；
First voltage applies module, for being two adjacent words of wordline corresponding with the memory cell to be read
Line adds first voltage, wherein first voltage is the filtered voltage of filtered device；
Second voltage applies module, for adding second voltage for the corresponding wordline of the memory cell to be read,
In, first voltage is more than second voltage.
Preferably, the filter is RC filters.
The third aspect, an embodiment of the present invention provides a kind of NAND memory device, the storage device includes voltage source, consolidates
Part further includes a plurality of wordline and multiple nand memory units, and every wordline is connected with corresponding memory cell respectively,
In, the storage device further includes filter；
Wherein, the voltage source is connect with every wordline, for being provided for the corresponding every wordline of the memory cell
Corresponding voltage when read operation；
The voltage source is also connect by the filter with every wordline, and the filter is used to deposit with to be read
Two adjacent wordline of the corresponding wordline of storage unit add to be filtered before corresponding voltage；
The firmware includes the read operation processing unit of nand flash memory as described above.
The embodiment of the present invention for two adjacent wordline of wordline corresponding with memory cell to be read by adding through filter
The filtered voltage of wave device reduces the fluctuation of voltage in two adjacent wordline by filter, to be read to reduce
The fluctuation of voltage in the corresponding wordline of memory cell, to improve the accuracy of read operation.
Description of the drawings
Fig. 1 be the NAND flash of the prior art read operation in normal mode and VmH patterns schematic diagram；
Fig. 2 is the flow chart of the read operation processing method of the nand flash memory in the embodiment of the present invention one；
Fig. 3 is the structural schematic diagram of the read operation processing unit of the nand flash memory in the embodiment of the present invention two；
Fig. 4 is the structural schematic diagram of the NAND memory device in the embodiment of the present invention three；
Fig. 5 is the circuit diagram of the filter in the embodiment of the present invention three.
Specific implementation mode
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 2 is the flow chart of the read operation processing method of the nand flash memory in the embodiment of the present invention one, and the present embodiment can fit
The case where read operation for nand flash memory is handled, is applied to NAND memory device, which includes a plurality of wordline
With multiple nand memory units, every wordline is connected with corresponding memory cell respectively.This method can be by with NAND
The device of the read operation processing function of flash memory executes, which may be used software and/or the mode of hardware is realized, such as
Firmware in NAND memory device.The method that the embodiment of the present invention one provides specifically includes：
S110, memory cell to be read is determined.
In NAND flash memory chips, memory cell is arranged in array, and each column all includes multiple memory cells,
The control grid of each memory cell is connect with wordline, by controlling read-write of the wordline realization to memory cell.Specifically,
Memory cell to be read can be determined by physical address.
S120, add first voltage for two adjacent wordline of wordline corresponding with memory cell to be read, wherein the
One voltage is the filtered voltage of filtered device.
Specifically, under VmH patterns, in order to reduce the vt distributions of transistor, need for selected memory cell it is corresponding
Adjacent two wordline of wordline apply higher voltage, such as VmH voltages, so as to cause the selected storage described in background technology
Device unit corresponds to the problem that voltage ripple is larger in wordline, influences the accuracy for reading result.Therefore, in the embodiment of the present invention
In one, VmH voltages are first passed through into filter and are filtered, then is applied to adjacent two of the corresponding wordline of selected memory cell
Wordline reduces voltage ripple to filter out the radio-frequency component in voltage.
In an example, first voltage is, for example, 6V or 7V, belongs to high pressure, is needed by the electricity in storage device chip
Lotus pump provides.And since selected memory cell is all variation always, therefore, it is necessary to add the memory cell of first voltage
It is variation, then when implementing, required voltage can be applied to control for corresponding memory cell by switching.
Preferably, the filter is RC filters.
S130, add second voltage for the corresponding wordline of memory cell to be read, wherein first voltage is more than the second electricity
Pressure.
After determining memory cell to be read, reading is realized by controlling its corresponding word line voltage, specifically, being
It applies second voltage and realizes read operation, for example, the second voltage is Vn voltages, in an example, which is 0.5V,
Belong to low-voltage.
The embodiment of the present invention for two adjacent wordline of wordline corresponding with memory cell to be read by adding through filter
The filtered voltage of wave device reduces the fluctuation of voltage in two adjacent wordline by filter, to be read to reduce
The fluctuation of voltage in the corresponding wordline of memory cell, to improve the accuracy of read operation.
Embodiment two
Fig. 3 is the structural schematic diagram of the data block processing unit of the nand flash memory in the embodiment of the present invention two, which answers
For NAND memory device, the storage device includes a plurality of wordline and multiple nand memory units, every wordline respectively with
Corresponding memory cell connection, the device specifically include：
Determining module 10, for determining memory cell to be read；
First voltage applies module 11, for for adjacent two of wordline corresponding with the memory cell to be read
Wordline adds first voltage, wherein first voltage is the filtered voltage of filtered device；
Second voltage applies module 12, for adding second voltage for the corresponding wordline of the memory cell to be read,
Wherein, first voltage is more than second voltage.
Further, the filter is RC filters.
The embodiment of the present invention for two adjacent wordline of wordline corresponding with memory cell to be read by adding through filter
The filtered voltage of wave device reduces the fluctuation of voltage in two adjacent wordline by filter, to be read to reduce
The fluctuation of voltage in the corresponding wordline of memory cell, to improve the accuracy of read operation.
Embodiment three
Fig. 4 is the structural schematic diagram of the NAND memory device in the embodiment of the present invention three, as shown, the storage device
4 include：Multiple memory cells 40, with corresponding memory cell connection a plurality of wordline 41, filter 42, voltage source 43 and
Firmware 44.
Wherein, voltage source 43 is connect with every wordline 41, for being provided for 40 corresponding every wordline 41 of memory cell
Corresponding voltage when read operation realizes read operation for example, providing second voltage for selected memory cell n to be read,
For example, the second voltage is Vn voltages, in an example, which is 0.5V, belongs to low-voltage；To remove the access to memory that continues
Memory cell except two memory cell n+1 and memory cell n-1 adjacent unit n provides Vm voltages, such as 5V
Or 6V.Voltage source 43 can be the charge pump in storage device chip.
Voltage source 43 is also connect by filter 42 with every wordline, wherein filter 42 is used to deposit with to be read
It is filtered before two adjacent wordline making alives of the corresponding wordline of storage unit.In the above example, voltage source 43 passes through
Wave filter 42 provides first voltage more higher than Vm voltage, i.e. VmH voltages for memory cell n+1 and memory cell n-1,
Such as 6V or 7V.VmH voltages eliminate high-frequency noise, reduce the fluctuation of voltage since filtered device 42 filters, to
Improve the accuracy of digital independent.
Firmware 44 can realize the control to the operations such as read-write wiping in NAND memory device according to external command, in the present invention
In embodiment, the control to different voltages in wordline is realized by firmware 44.
In one embodiment, the voltage in wordline can be provided by the charge pump in storage device chip, in difference
Pattern under, charge pump can provide the voltage needed for corresponding memory cell, if under same pattern, it is desirable to provide electricity
It is pressed with a variety of, then can be provided by multiple corresponding charge pumps.For example, in embodiments of the present invention, two can be passed through
Charge pump provides Vm and VmH voltages respectively.Further, for which wordline provide Vn voltages and for which wordline provide Vm and
VmH voltages can then be realized by the circuit in the program cooperating equipment in firmware, for example, can by the switch in wordline come
Control.Particularly, when VmH voltages are provided, it is also necessary to first pass through filter and be re-applied in corresponding wordline.
Specifically, firmware 44 includes the read operation processing unit of nand flash memory, which includes：
Determining module, for determining memory cell to be read；
First voltage applies module, for being two adjacent words of wordline corresponding with the memory cell to be read
Line adds first voltage, wherein first voltage is the filtered voltage of filtered device；
Second voltage applies module, for adding second voltage for the corresponding wordline of the memory cell to be read,
In, first voltage is more than second voltage.
Preferably, filter 42 be RC filters, as shown in figure 5, the parameter of resistance R and capacitance C can as needed into
Row setting.
NAND memory device provided in an embodiment of the present invention by increasing filter, and is again after first filtered device filtering
Two adjacent wordline of wordline corresponding with memory cell to be read add corresponding voltage, and it is adjacent to reduce this by filter
Two wordline on voltage fluctuation, to reduce the fluctuation of voltage in the corresponding wordline of memory cell to be read, to carry
The accuracy of high read operation.
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (5)
1. a kind of read operation processing method of nand flash memory is applied to NAND memory device, the storage device includes a plurality of word
Line and multiple nand memory units, every wordline are connected with corresponding memory cell respectively, which is characterized in that the method
Including：
Determine memory cell to be read；
Add first voltage for two adjacent wordline of wordline corresponding with the memory cell to be read, wherein the first electricity
Pressure is the filtered voltage of filtered device；
Add second voltage for the corresponding wordline of the memory cell to be read, wherein first voltage is more than second voltage.
2. according to the method described in claim 1, it is characterized in that, the filter is RC filters.
3. a kind of read operation processing unit of nand flash memory is applied to NAND memory device, the storage device includes a plurality of word
Line and multiple nand memory units, every wordline are connected with corresponding memory cell respectively, which is characterized in that described device
Including：
Determining module, for determining memory cell to be read；
First voltage applies module, for adding for two adjacent wordline of wordline corresponding with the memory cell to be read
First voltage, wherein first voltage is the filtered voltage of filtered device；
Second voltage applies module, for adding second voltage for the corresponding wordline of the memory cell to be read, wherein the
One voltage is more than second voltage.
4. device according to claim 3, which is characterized in that the filter is RC filters.
5. a kind of NAND memory device, the storage device includes voltage source, firmware, further includes that a plurality of wordline and multiple NAND are deposited
Storage unit, every wordline are connected with corresponding memory cell respectively, which is characterized in that the storage device further includes filtering
Device；
Wherein, the voltage source is connect with every wordline, for providing reading for the corresponding every wordline of the memory cell
Corresponding voltage when operation；
The voltage source is also connect by the filter with every wordline, the filter be used for be and memory to be read
Two adjacent wordline of the corresponding wordline of unit add to be filtered before corresponding voltage；
The firmware includes the read operation processing unit of nand flash memory as described in claim 3 or 4.
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| CN201710128834.4A CN108538333B (en) | 2017-03-06 | 2017-03-06 | NAND flash memory read operation processing method and device and NAND storage equipment |
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| CN201710128834.4A CN108538333B (en) | 2017-03-06 | 2017-03-06 | NAND flash memory read operation processing method and device and NAND storage equipment |
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| CN117809708A (en) * | 2024-02-29 | 2024-04-02 | 浙江力积存储科技有限公司 | Memory array and method for improving data reading accuracy of memory array |
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