CN205845517U - Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage - Google Patents

Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage Download PDF

Info

Publication number
CN205845517U
CN205845517U CN201620556791.0U CN201620556791U CN205845517U CN 205845517 U CN205845517 U CN 205845517U CN 201620556791 U CN201620556791 U CN 201620556791U CN 205845517 U CN205845517 U CN 205845517U
Authority
CN
China
Prior art keywords
memorizer
row unit
select row
circuit
wordline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201620556791.0U
Other languages
Chinese (zh)
Inventor
陶胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sichuan Douqi Technology Co Ltd
Original Assignee
Sichuan Douqi Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sichuan Douqi Technology Co Ltd filed Critical Sichuan Douqi Technology Co Ltd
Priority to CN201620556791.0U priority Critical patent/CN205845517U/en
Application granted granted Critical
Publication of CN205845517U publication Critical patent/CN205845517U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

This utility model relates to integrated circuit fields, disclose a kind of memorizer, NOR flash memory memorizer and the select row unit for memorizer and the circuit of read operation required voltage is provided, this circuit includes electric charge pump, Voltage stabilizing module, charge storage cell and phase inverter, wherein: the input of described phase inverter is used for receiving logic level signal, the outfan of described phase inverter is connected to one end of described charge storage cell, and the other end of described charge storage cell is connected in the wordline of described select row unit;And described electric charge delivery side of pump is connected to the input of described Voltage stabilizing module, the outfan of described Voltage stabilizing module is connected in the wordline of described select row unit.This utility model can either make the voltage in the wordline of the select row unit of memorizer more stable, and the voltage of the wordline of the select row unit of memorizer can be made again to be climbed to the voltage needed for memory read operation.

Description

Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage
Technical field
This utility model relates to integrated circuit fields, in particular it relates to a kind of memorizer, NOR flash memory memorizer and for depositing The select row unit of reservoir provides the circuit of read operation required voltage.
Background technology
At present, when memorizer is performed read operation, it is the most all to carry out selecting to memorizer by the circuit shown in Fig. 1 The gate terminal (namely wordline WL) of row unit applies the voltage needed for read operation, i.e. Vwl.The shortcoming of circuit shown in Fig. 1 is to be applied Voltage VwlUnstable.
In order to be applied to the voltage stabilization in the wordline of select row unit, in the wordline of memory element, generally increase by one Individual ground connection bulky capacitor C1, as shown in Figure 2.But, increase bulky capacitor C1, although the problem solving voltage stabilization, but can be significantly Increase the power-on time of word line voltage of select row unit, the i.e. voltage of wordline WL and rise to electricity needed for memory read operation from 0 The time that pressure (generally at about 5V) is to be spent.
Summary of the invention
The purpose of this utility model is to provide a kind of memorizer, NOR flash memory memorizer and the select row unit for memorizer There is provided read operation required voltage circuit, its can either make memorizer select row unit wordline on voltage more stable, again The voltage that can make the wordline of the select row unit of memorizer is climbed to the voltage needed for memory read operation.
To achieve these goals, needed for this utility model provides a kind of select row unit for memorizer to provide read operation The circuit of voltage, this circuit includes electric charge pump, Voltage stabilizing module, charge storage cell and phase inverter, wherein: described phase inverter defeated Entering to hold for receiving logic level signal, the outfan of described phase inverter is connected to one end of described charge storage cell, described The other end of charge storage cell is connected in the wordline of described select row unit;And described electric charge delivery side of pump is connected to The input of described Voltage stabilizing module, the outfan of described Voltage stabilizing module is connected in the wordline of described select row unit.
Preferably, described electric charge delivery side of pump is connected in the wordline of described select row unit, and described voltage stabilizing mould Block includes the first resistor, the second resistor, amplifier and semiconductor switch, wherein: described first resistor one end ground connection, another One end is connected to described second resistor, and the other end of described second resistor is connected to the wordline of described select row unit;Institute The input stating amplifier receives reference voltage, and another input is connected to described first resistor and described second resistance The common port of device;The outfan of described amplifier is connected to the grid of described semiconductor switch;And described semiconductor switch Drain electrode is connected to the wordline of described select row unit, the source ground of described semiconductor switch.
Preferably, described semiconductor switch is MOSFET.
Preferably, described charge storage cell is capacitor.
Preferably, the high level of described logic level signal is more than zero and less than or equal to needed for described memory read operation Voltage.
This utility model also provides for a kind of memorizer, and this memorizer includes circuitry described above.
This utility model also provides for a kind of NOR flash memory memorizer, and this NOR flash memory memorizer includes circuitry described above.
By technique scheme, owing to the input according to the phase inverter in circuit of the present utility model is patrolled for reception Collecting level signal, the outfan of described phase inverter is connected to one end of described charge storage cell, described charge storage cell The other end is connected in the wordline of described select row unit, therefore when memorizer performs read operation, by making phase inverter input The logic level signal of end becomes low level, it is possible to makes the outfan of phase inverter produce a rising edge signal, and passes through electric charge Memory element makes the word line voltage moment of the select row unit of memorizer rise to the voltage needed for memory read operation, and electric charge Pump and Voltage stabilizing module then can play the effect that above-mentioned voltage carries out voltage stabilizing, and therefore, this utility model can either make memorizer Select row unit wordline on voltage more stable, can make again the select row unit of memorizer wordline voltage quickly on It is raised to the voltage needed for memory read operation.
Other features and advantages of the utility model will be described in detail in detailed description of the invention part subsequently.
Accompanying drawing explanation
Accompanying drawing is used to offer and is further appreciated by of the present utility model, and constitutes a part for description, with following Detailed description of the invention be used for explaining this utility model together, but be not intended that restriction of the present utility model.In the accompanying drawings:
Fig. 1 is the circuit diagram of the select row unit offer read operation required voltage in prior art for memorizer;
Fig. 2 is another circuit diagram of the select row unit offer read operation required voltage in prior art for memorizer;
Fig. 3 is that the select row unit for memorizer according to a kind of embodiment of this utility model provides electricity needed for read operation The circuit diagram of pressure;And
Fig. 4 is that the select row unit for memorizer according to the another embodiment of this utility model provides electricity needed for read operation The circuit diagram of pressure.
Detailed description of the invention
Below in conjunction with accompanying drawing, detailed description of the invention of the present utility model is described in detail.It should be appreciated that herein Described detailed description of the invention is merely to illustrate and explains this utility model, is not limited to this utility model.
It is pointed out that unless stated otherwise, when referred to hereinafter, term " charge storage cell " refers to the most permissible Realize the device of electric charge storage, such as, can be electric capacity etc.;When referred to hereinafter, term " semiconductor switch " refers to permissible The switch that break-make controls, such as mosfet transistor, double pole triode etc. is realized by the signal of telecommunication.
This utility model provides a kind of select row unit for memorizer to provide the circuit of read operation required voltage, such as Fig. 3 Shown in, this circuit can include electric charge pump 100, Voltage stabilizing module 200, charge storage cell C0 and phase inverter INV1, wherein: described The input of phase inverter INV1 is used for receiving logic level signal CSb, and the outfan of described phase inverter INV1 is connected to described electricity One end of charge storing element C0, the other end of described charge storage cell C0 is connected in wordline WL of described select row unit; And described electric charge delivery side of pump is connected to the input of described Voltage stabilizing module, the outfan of described Voltage stabilizing module is connected to institute State in wordline WL of select row unit.
The shown operation principle according to circuit of the present utility model of Fig. 3 once is below described.
When the select row unit of memorizer is performed read operation, it is assumed for example that wordline WL0 ..., the WL1 in WLN is selected Regularly, the logic level signal CSb of the input of phase inverter INV1 is switched to low level, then the high electricity of phase inverter INV1 output Flat logical signal CLKA, and the voltage V in the wordline of select row unit is made by charge storage cell C0wlMoment rises to deposit Voltage needed for reservoir read operation, electric charge pump 100 and mu balanced circuit 200 are then used for maintaining this voltage Vwl.Due to select row When unit performs read operation, phase inverter INV1 output is high level, and therefore electric charge pump 100 need not export the highest voltage i.e. Can meet the requirement of select row unit read operation, therefore this can be substantially reduced the area of electric charge pump, thus reduces storage core The cost of sheet, reduces the power consumption of memory chip.It addition, during maintaining select row unit read operation required voltage, electric charge is deposited Storage element C0 may also operate as the effect of filtering such that it is able to reduces the ripple of the word line voltage of select row unit, makes select row Current potential V in the wordline of unitwlMore stable.It addition, because there being one about 10 in each wordline WL of memorizer-1Posting of PF level Raw electric capacity, therefore wordline WL switches when, owing to there being the existence of charge storage cell C0, the loss of voltage is the least, can neglect Slightly disregard.
According in a preferred implementation of the present utility model, as shown in Figure 4, the outfan of described electric charge pump 100 Be connected in the wordline (such as WL0) of described select row unit, and described Voltage stabilizing module 100 include the first resistor R1, Two resistor R2, amplifier AM1 and semiconductor switch M1, wherein: described first resistor R1 one end ground connection, the other end are connected to Described second resistor R2, the other end of described second resistor R2 is connected in the wordline of described select row unit;Described put One input of big device AM1 receives reference voltage Vref, and another input is connected to described first resistor R1 and described the The common port of two resistor R2;The outfan of described amplifier AM1 is connected to the grid of described semiconductor switch M1;And it is described The drain electrode of semiconductor switch M1 is connected in the wordline of described select row unit, the source ground of described semiconductor switch M1.Logical Cross this Voltage stabilizing module 200, it becomes possible to the output voltage of electric charge pump 100 is carried out voltage stabilizing.
Wherein, in the circuit shown in Fig. 4, described semiconductor switch M1 can be MOSFET.
It will be apparent to a skilled person that the Voltage stabilizing module 200 shown in Fig. 4 is only example.It practice, this practicality Novel not limiting the concrete structure of Voltage stabilizing module 200, any circuit structure being capable of voltage stabilizing function all can be expired Foot requirement of the present utility model.
According in a preferred implementation of the present utility model, described charge storage cell C0 can be capacitor, Such as charge storage cell can be single capacitor, it is also possible to be the parallel form of multiple capacitor.
According in a preferred implementation of the present utility model, the high level of described logic level signal CSb is preferred More than zero and less than or equal to the voltage needed for described memory read operation.So, it becomes possible to need not export very at electric charge pump 100 Meeting the requirement of the read operation voltage of select row unit in the case of high-tension, this can reduce the chip area of electric charge pump 100, And then reduce chip area and the power consumption of memorizer.
The concrete structure of amplifier AM1 is not limited by this utility model, any amplification being capable of enlarging function Device circuit structure all disclosure satisfy that requirement of the present utility model.
The concrete structure of electric charge pump 100 is not limited by this utility model, any electricity being capable of boost function Road all disclosure satisfy that this utility model requirement to electric charge pump.
This utility model also provides for a kind of memorizer, and this memorizer can include as described above according to of the present utility model Circuit.Can be NOR flash memory memorizer, NAND-flash memory or other kinds of storage according to memorizer of the present utility model Device.
Preferred implementation of the present utility model is described in detail above in association with accompanying drawing, but, this utility model does not limit Detail in above-mentioned embodiment, in technology concept of the present utility model, can be to skill of the present utility model Art scheme carries out multiple simple variant, and these simple variant belong to protection domain of the present utility model.
It is further to note that each the concrete technical characteristic described in above-mentioned detailed description of the invention, at not lance In the case of shield, can be combined by any suitable means.In order to avoid unnecessary repetition, this utility model is to respectively Plant possible compound mode to illustrate the most separately.
Additionally, combination in any can also be carried out, as long as it is not disobeyed between various different embodiment of the present utility model Carrying on the back thought of the present utility model, it should be considered as content disclosed in the utility model equally.

Claims (7)

1. the select row unit that a kind is memorizer provides the circuit of read operation required voltage, it is characterised in that this circuit includes Electric charge pump, Voltage stabilizing module, charge storage cell and phase inverter, wherein:
The input of described phase inverter is used for receiving logic level signal, and the outfan of described phase inverter is connected to described electric charge and deposits One end of storage element, the other end of described charge storage cell is connected in the wordline of described select row unit;And
Described electric charge delivery side of pump is connected to the input of described Voltage stabilizing module, and the outfan of described Voltage stabilizing module is connected to institute State in the wordline of select row unit.
Circuit the most according to claim 1, it is characterised in that described electric charge delivery side of pump is connected to described select row list In the wordline of unit, and described Voltage stabilizing module includes the first resistor, the second resistor, amplifier and semiconductor switch, wherein:
Described first resistor one end ground connection, the other end are connected to described second resistor, the other end of described second resistor It is connected in the wordline of described select row unit;
One input of described amplifier receives reference voltage, and another input is connected to described first resistor and described the The common port of two resistors;
The outfan of described amplifier is connected to the grid of described semiconductor switch;And
The drain electrode of described semiconductor switch is connected in the wordline of described select row unit, and the source electrode of described semiconductor switch connects Ground.
Circuit the most according to claim 2, it is characterised in that described semiconductor switch is MOSFET.
4. according to the circuit described in claim 1 or 2 or 3, it is characterised in that described charge storage cell is capacitor.
5. according to the circuit described in claim 1 or 2 or 3, it is characterised in that the high level of described logic level signal is more than zero And less than or equal to the voltage needed for described read operation.
6. a memorizer, it is characterised in that this memorizer includes according to described in any claim in claim 1 to 5 Circuit.
7. a NOR flash memory memorizer, it is characterised in that this NOR flash memory memorizer includes according to arbitrary in claim 1 to 5 Circuit described in claim.
CN201620556791.0U 2016-06-07 2016-06-07 Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage Expired - Fee Related CN205845517U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201620556791.0U CN205845517U (en) 2016-06-07 2016-06-07 Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201620556791.0U CN205845517U (en) 2016-06-07 2016-06-07 Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage

Publications (1)

Publication Number Publication Date
CN205845517U true CN205845517U (en) 2016-12-28

Family

ID=58151971

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201620556791.0U Expired - Fee Related CN205845517U (en) 2016-06-07 2016-06-07 Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage

Country Status (1)

Country Link
CN (1) CN205845517U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108538333A (en) * 2017-03-06 2018-09-14 北京兆易创新科技股份有限公司 Read operation processing method, device and the NAND memory device of nand flash memory
CN112086120A (en) * 2020-11-13 2020-12-15 深圳市芯天下技术有限公司 Word line and bit line voltage conversion method and circuit and non-flash memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108538333A (en) * 2017-03-06 2018-09-14 北京兆易创新科技股份有限公司 Read operation processing method, device and the NAND memory device of nand flash memory
CN108538333B (en) * 2017-03-06 2022-02-11 北京兆易创新科技股份有限公司 NAND flash memory read operation processing method and device and NAND storage equipment
CN112086120A (en) * 2020-11-13 2020-12-15 深圳市芯天下技术有限公司 Word line and bit line voltage conversion method and circuit and non-flash memory

Similar Documents

Publication Publication Date Title
CN101325411B (en) Slow starting circuit for electrifying DC power supply
CN103312144B (en) Active-control valley fill circuit and control method thereof
CN101452746B (en) Power supply switching circuit
EP1288964A3 (en) Non-volatile semiconductor memory
CN102290981B (en) The flash memory of a kind of charge pump circuit and the described charge pump circuit of employing
CN205485902U (en) Automatic start circuit and electronic equipment
CN205845517U (en) Memorizer and the select row unit for memorizer provide the circuit of read operation required voltage
CN202513599U (en) Charging circuit, memory chip and consumable container
CN103066962B (en) delay circuit
US20140152378A1 (en) Charge pump circuit
CN102158076B (en) Charge pump output voltage regulation circuit
CN103312158A (en) Boosting circuit
CN103066972A (en) Power-on reset circuit with global enabling pulse control automatic reset function
CN103812332B (en) A kind of charge pump circuit and memory
CN105576746A (en) Timing activation circuit for battery management system
CN204029386U (en) A kind of dynamically preliminary filling control circuit and flash-memory storage system
CN202524058U (en) Protection circuit against overvoltage, undervoltage and power reverse
KR102330656B1 (en) Nvm with charge pump and method therefor
CN105006860A (en) Controllable charge and discharge apparatus and voltage-equalizing circuit of a supercapacitor based on apparatus
CN109256752B (en) Battery protection circuit and power supply system
CN203933099U (en) A kind of portable power source device
CN206060238U (en) A kind of charging active circuit of lithium battery
CN109450432B (en) Radio frequency input port protection circuit
CN207602978U (en) Semiconductor integrated circuit
US9099190B2 (en) Non-volatile memory device with improved reading circuit

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20161228

Termination date: 20210607

CF01 Termination of patent right due to non-payment of annual fee