CN101887749A - Storage device and operating method thereof - Google Patents
Storage device and operating method thereof Download PDFInfo
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- CN101887749A CN101887749A CN2009101409166A CN200910140916A CN101887749A CN 101887749 A CN101887749 A CN 101887749A CN 2009101409166 A CN2009101409166 A CN 2009101409166A CN 200910140916 A CN200910140916 A CN 200910140916A CN 101887749 A CN101887749 A CN 101887749A
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Abstract
The invention discloses a storage device and an operating method thereof. The operating method comprises the following steps of: exerting a first line voltage to a storage unit to detect a first current of the storage unit; when the first current is larger than a first reference current related to the first line voltage, judging that a first data storage area is in an unprogrammed state; otherwise, exerting a second line voltage to the storage unit to detect a second current of the storage unit; when the difference between the first current and the second current is larger than that between the first reference current and a second reference current, judging that the first data storage area is in the unprogrammed state; and otherwise, judging that the first data storage area is in a programming state.
Description
Technical field
The invention relates to a kind of method and storage arrangement of operational store, and particularly relevant for the method and the storage arrangement that in storage arrangement, reduce second effect (second bit effect).
Background technology
Storer is a kind of semiconductor element that is used for store information or data.Along with the function of computer microprocessor from strength to strength, the program of carrying out by software also increases with operation thereupon.Therefore, also increase gradually for demand with high storage capacity storer.
In various memory products, nonvolatile memory (non-volatile storer) allow repeatedly data programing (programming), read (reading) and wipe (erasing) operation, and even after the power interruption of storer, can also preserve the data that are stored in wherein.Because these advantages, nonvolatile memory has become widely used storer in personal computer and the electronic equipment.
The electronic programmable of knowing about charge storing structure (charge storage structure) can wipe (electrically programmable and erasable) non-volatile memory technologies such as electronics Erasable Programmable Read Only Memory EPROM (electrically erasable programmable read-only storer, EEPROM) and flash memory (flash storer) be used in various modernizations and used.Flash memory design becomes to have memory cell array, and it can be programmed and read independently.General flash memory cell with Charge Storage in floating grid (floating gate).Another kind of flash memory uses charge-trapping structure (charge-trapping structure), as one deck nonconductor silicon nitride (SiN) material, but not is used for the conductor grid material of floating grid element.When charge capturing storage unit was programmed, electric charge was captured and can not moves through the nonconductor layer.Electric charge keeps being wiped free of up to storage unit by electric charge capture layer, keeps data mode when not continuing power supply.Charge capturing storage unit can be become two end storage unit (two-sided cell) by behaviour.That is to say that because electric charge can not move through the nonconductor electric charge capture layer, so electric charge can be positioned at different charge-trapping places.In other words, in the flash element that uses the charge-trapping structure, the information storage that surpasses is in each storage unit.
An independent storage unit can be programmed to store two positions of separating fully (concentrating the mode of close source area and drain region with electric charge respectively) in the charge-trapping structure.The programming of storage unit can be passed through channel hot electron, and (channel hot electron CHE) injects and to carry out, and it produces thermoelectron at channel region.Some thermoelectrons obtain energy and are trapped in the charge-trapping structure.Bias voltage (bias) by will being applied to source terminal and drain electrode end exchanges, and electric charge is captured to arbitrary part (near source area, near drain region or the two) of charge-trapping structure.
Therefore, if do not have Charge Storage in storage unit, the threshold voltage of storage unit (threshold voltage) has the minimum value of the combination of corresponding position 1 and 1.If near source area but keep clear of the drain region, threshold voltage has the different value of the combination of corresponding position 1 and 0 to Charge Storage in the charge-trapping structure.If Charge Storage is near drain region but keep clear of source area, threshold voltage has another value.Under this situation, the combination of the corresponding position 0 and 1 of threshold voltage.At last, if Charge Storage near source area and drain region, threshold voltage is for the highest, and corresponding 0 and 0 combination.Therefore, can store four kinds of different combinations (position 00,01,10 and 11), and each combination has corresponding threshold voltage.During read operation, the electric current that flows through storage unit will depend on the threshold voltage of storage unit and change.Typically, this electric current will have four different values, and each is corresponding to different threshold voltages.Therefore, by detecting this electric current, can judge the bit combination that is stored in the storage unit.
All effectively ranges of charge or threshold voltage ranges can classify as memory operation window (memory operation window).In other words, memory operation window defines by the program level (level) and the difference of wiping between the level.Because memory cell operation needs the good electrical between the various states to divide equally from (level separation), therefore need big memory operation window.Yet the usefulness of two storage unit reduces along with so-called " second effect " usually.Under second effect, (localized) electric charge of localization influences each other in the charge-trapping structure.For instance, in reverse read (reverse reading) operating period, apply to read and be biased into drain electrode end and detect the electric charge (i.e. " first ") that is stored near source area.Yet the position (i.e. " second ") near the drain region produces the primary potential barrier (potential barrier) that reads near source area afterwards.This potential barrier can overcome by applying suitable bias voltage, and (drain-induced barrierlowering, DIBL) effect suppresses the deputy effect near the drain region, and allows to detect primary storing state to use the drain-induced barrier reduction.Yet, when being programmed to high threshold voltage state near second of drain region and near first of source area during at programming state not, second has been improved potential barrier in fact.Therefore, along with increasing, primaryly read the potential barrier that bias voltage has not enough overcome second generation about deputy threshold voltage.Therefore, owing to increase, also improve about primary threshold voltage, thereby reduced memory operation window about deputy threshold voltage.Second effect reduced the memory operation window of 2-bit/cell operation.Therefore, need to suppress the method and the element of second effect in the memory component.
Summary of the invention
The invention provides a kind of method of reading cells, it can alleviate second effect.
The present invention provides the method for a kind of operation store unit in addition, and it can reduce operation window.
The present invention proposes the method that a kind of operation has the storage unit of first region of data storage (data storage) and second region of data storage.The method comprises and applies first electric current that first bit-line voltage to storage unit is come the detection of stored unit.When first electric current greater than about first reference current of first bit-line voltage time, judge that first region of data storage is programming state not.When first electric current during, apply second electric current that second bit-line voltage to storage unit is come the detection of stored unit less than first reference current.Then, when first difference between first electric current and second electric current during, judge that first region of data storage is programming state not greater than second difference between first reference current and second reference current.Yet, when first difference is less than or equal to second difference, judge that first region of data storage is a programming state.
According to embodiments of the invention, second bit-line voltage is different with first bit-line voltage.
According to embodiments of the invention, second bit-line voltage is greater than first bit-line voltage.
According to embodiments of the invention, first word line voltage that is used to detect first electric current equals to be used to detect second word line voltage of second electric current.
According to embodiments of the invention, the method comprises that more the programming of define storage units confirms the upper limit that the low threshold voltage of voltage (program verify voltage) and define storage units distributes.In addition, the difference between the upper limit of programming affirmation voltage and low threshold voltage distribution is about 600mV.
The present invention proposes a kind of storage arrangement in addition.This storage arrangement comprises storer and controller.Storer has a plurality of storage unit.Each storage unit has first region of data storage and second region of data storage.Controller is used for each storage unit is carried out read step (reading process).For each storage unit, read step comprises and applies first electric current that first bit-line voltage to storage unit is come the detection of stored unit.When first electric current greater than about first reference current of first bit-line voltage time, judge that first region of data storage is programming state not.When first electric current during, apply second electric current that second bit-line voltage to storage unit is come the detection of stored unit less than first reference current.Then, when first difference between first electric current and second electric current during, judge that first region of data storage is programming state not greater than second difference between first reference current and second reference current.Yet, when first difference is less than or equal to second difference, judge that first region of data storage is a programming state.
The present invention provides a kind of storage arrangement again.This storage arrangement comprises storer, testing circuit and controller.Storer has a plurality of storage unit.Each storage unit has first region of data storage and second region of data storage.Testing circuit is used for applying first electric current that first bit-line voltage to storage unit is come the detection of stored unit during read step, wherein when first electric current less than about first reference current of first bit-line voltage time, testing circuit applies second electric current that second bit-line voltage to storage unit is come the detection of stored unit.Controller is used for confirming voltage and each storage unit being carried out read step with reference to programming.For each storage unit, read step comprises the first threshold voltage that detects first region of data storage, judges when first threshold voltage is confirmed voltage less than programming that then first region of data storage is programming state not.
In the present invention, when each the region of data storage reading of data in storage unit, the performance of the threshold voltage distribution of target data storage area under different bit-line voltages (target data storage) is used for judging the programming state of target data storage area.Therefore, even operation window is very little, even there be not (closed) in operation window, and when detecting electric current less than reference current, region of data storage with position " 1 " under second effect and the region of data storage with position " 0 " can correctly be distinguished.Therefore, when the size of storage unit is dwindled, operation window will no longer be to hinder.In addition, alleviated second effect for memory cell operation.In addition, owing to alleviated second effect and had little operation window, so the time that has increased program speed and reduced memory cells.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is the diagrammatic cross-section according to the storage unit that one embodiment of the invention illustrated.
Fig. 2 is the functional block diagram according to the storage arrangement that one embodiment of the invention illustrated.
Fig. 3 is the circuit diagram of the storer of the storage arrangement among Fig. 2.
The threshold voltage distribution figure of storage unit when Fig. 4 A senses first electric current for the storage unit when storer according to one embodiment of the invention is programmed.
The threshold voltage distribution figure of storage unit when Fig. 4 B senses second electric current for the storage unit when storer according to one embodiment of the invention is programmed.
Fig. 5 is the flow chart of steps according to the read method of the storage unit of the storer that one embodiment of the invention illustrated.
Fig. 6 A for according to one embodiment of the invention at the following threshold voltage distribution figure of region of data storage in the storage unit of the not programming state " 11 " with multiple bit-line voltage.
Fig. 6 B is for having under the programming state of multiple bit-line voltage " 00 " the threshold voltage distribution figure of data storing in the storage unit according to one embodiment of the invention.
Fig. 6 C is for having under the programming state of multiple bit-line voltage " 01 "/" 10 " the threshold voltage distribution figure of region of data storage in the storage unit according to one embodiment of the invention.
Fig. 7 is the flow chart of steps according to the definition process nargin that one embodiment of the invention illustrated.
Fig. 8 is the flow chart of steps according to the read method of the storage unit of the storer that one embodiment of the invention illustrated.
[main element symbol description]
100: storage unit
110a: first region of data storage
110b: second region of data storage
102: substrate
104: source/drain regions
108,112: insulation course
110: electric charge capture layer
114: the conductor grid
200: storage arrangement
202: storer
204: controller
206: column decoder
208: line decoder
210: testing circuit
212: analog-to-digital converter
402: first threshold voltage distributes
404: the second threshold voltage distribution
406: the three threshold voltage distribution
602,604: threshold voltage distribution group
B0-Bm+1: bit line
D1, D2: voltage difference
Dr: reference voltage is poor
S501-S511, S701-S703, S801-S815: step
W0-Wn: word line
Embodiment
Fig. 1 is the diagrammatic cross-section according to the storage unit that one embodiment of the invention illustrated.As shown in Figure 1, storage unit 100 has substrate 102.Be formed with two source/drain regions 104 in the substrate 102.The bottom insulation layer 108 of storage unit 100 is formed on the passage between the source/drain regions 104.Electric charge capture layer 110 is positioned on the top of insulation course 108, its by insulation course 108 and with substrate 102 electrical isolation.When thermoelectron was injected in the electric charge capture layer 110, thermoelectron was captured, and made the threshold voltage of storage unit 100 to be adjusted under control.Top layer 112 is formed on the electric charge capture layer 110, with conductor grid 114 and electric charge capture layer 110 electrical isolation.Storage unit 100 have close source/drain regions 104 one of them the first region of data storage 110a with near source/drain regions 104 another the second region of data storage 110b wherein.The first region of data storage 110a and the second region of data storage 110b are able to programme, to store one data.Therefore, two data will be stored in the storage unit 100.
When the programming first region of data storage 110a, apply voltages to the source/drain regions 104 of conductor grid 114 and the close first region of data storage 110a, thereby produce vertical and horizontal electric field, so that electronics is quickened away from the first region of data storage 110a along the passage of storage unit 100 by another source/drain regions 104.When electronics moves along passage, some electronics obtain enough energy and the potential barrier of the bottom insulation layer 108 of jumping over, and are trapped in the electric charge capture layer 110 around the first region of data storage 110a.Therefore, when the position of programming state not was defined as logical one, the threshold voltage of the first region of data storage 110a increased, and the position of the first region of data storage 110a changes " 0 " into by " 1 ", that is was second logic state by first logic state transitions.Similarly, when the programming second region of data storage 110b, apply voltages to the source/drain regions 104 of conductor grid 114 and the close second region of data storage 110b, so that electronics is trapped in the second region of data storage 110b electric charge capture layer 110 on every side.Therefore, the threshold voltage of the second region of data storage 110b will increase, and the position of the second region of data storage 110b is changed " 0 " into by " 1 ".
Fig. 2 is the functional block diagram according to the storage arrangement that one embodiment of the invention illustrated.Fig. 3 is the circuit diagram of the storer of the storage arrangement among Fig. 2.As Fig. 2 and shown in Figure 3, storage arrangement 200 has storer 202, controller 204, column decoder (row decoder) 206, line decoder (column decoder) 208, testing circuit 210 and analog-to-digital converter (analog-to-digital converter) 212.Storer 202 has a plurality of storage unit 100 (as shown in Figure 1).The storage unit 100 of storer 202 is configured to array in the capable mode of n row m, and wherein n and m are the integer greater than 1.Controller 204 is coupled to column decoder 206 and line decoder 208, with the operation of the storage unit 100 of control store 202.Analog-to-digital converter 212 is coupled to controller 204, the form that is converted to digital value respectively with the electric current that will be detected and reference current.Column decoder 206 is via a plurality of word line W of storage arrangement 200
0-W
nAnd apply the conductor grid 114 of word line voltage to storage unit 100.Line decoder 208 is via a plurality of bit line B of storage arrangement 200
0-B
M+1And apply bit-line voltage to storage unit 100.As Fig. 1 and shown in Figure 3, the conductor grid 114 of each storage unit 100 is coupled to word line W
0-W
nIn a corresponding word lines.The source/drain regions 104 of each storage unit 100 is coupled to bit line B
0-B
M+1In two adjacent bit lines.For instance, the conductor grid of the most upper left storage unit 100 is coupled to word line W
0, and the source/drain regions of upper left storage unit 100 is coupled to bit line B respectively
0With B
1
When from data storage area read data information of storage unit 100, via word line W
0-W
nIn corresponding word lines the conductor grid 114 of storage unit 100 is applied word line voltage (for example 5V), will be under read operation, and via bit line B near the source/drain regions ground connection (grounded) of region of data storage
0-B
M+1In corresponding bit lines another source/drain regions near another region of data storage is applied bit-line voltage (for example 1.6V).As shown in Figure 1, when the position of the first region of data storage 110a of reading cells 100, conductor grid 114 is applied word line voltage, will be near source/drain regions 104 ground connection of the first region of data storage 110a, and another source/drain regions 104 applied second bit-line voltage.If word line voltage is higher than the threshold voltage of the first region of data storage 110a, then the passage between the source/drain regions 104 is unlocked (turned on), and electric current is from source/drain regions 104 (away from the first region of data storage 110a) process source/drain regions 104 (near the first region of data storage 110a) and bit line B
0-B
M+1In a corresponding bit lines and flow to testing circuit 210.Yet if word line voltage is lower than the threshold voltage of the first region of data storage 110a, the passage between the source/drain regions 104 is closed (turned off), and testing circuit 210 will can not detect the electric current from storage unit 100.Therefore, testing circuit 210 will be by detecting the logic state of judging the position of the first region of data storage 110a from the electric current of storage unit 100.Similarly, when the position of the second region of data storage 110b of reading cells 100, conductor grid 114 is applied word line voltage, (away from the second region of data storage 110b) applies bit-line voltage to source/drain regions 104, and with source/drain regions 104 (near the second region of data storage 110b) ground connection.If word line voltage is higher than the threshold voltage of the second region of data storage 110b, then the passage between the source/drain regions 104 is unlocked, and electric current is from source/drain regions 104 (away from the second region of data storage 110b) process source/drain regions 104 (near the second region of data storage 110b) and bit line B
0-B
M+1In a corresponding bit lines and flow to testing circuit 210.Yet if word line voltage is lower than the threshold voltage of the second region of data storage 110b, the passage between the source/drain regions 104 is closed, and testing circuit 210 will can not detect the electric current from storage unit 100.
For the storage unit (as storage unit 100) of two storages, have four kinds of programming states (comprising 11,01,10 and 00) at least.In this embodiment, the not programming state of storage unit is defined as logic " 11 ".Therefore, when first region of data storage and second region of data storage all were programmed, the programming state of storage unit was defined as logic " 00 ".In addition, the programming state of each storage unit can be distributed by corresponding threshold voltage and represent.The threshold voltage distribution figure of storage unit when Fig. 4 A senses first electric current for the storage unit when storer according to one embodiment of the invention is programmed.The threshold voltage distribution figure of storage unit when Fig. 4 B senses second electric current for the storage unit when storer according to one embodiment of the invention is programmed.Shown in Fig. 4 A, transverse axis among Fig. 4 A is represented first region of data storage 110a of storage unit 100 and the word line voltage of the second region of data storage 110b, and Z-axis is represented the quantity by the stored position of the first region of data storage 110a of storage unit 100 and the second region of data storage 110b.Shown in Fig. 4 A, the distribution of threshold voltage of position " 1 " that 402 expressions have the storage unit 100 of " 11 " programming state that distributes of first threshold voltage.In other words, when first region of data storage of storage unit and second region of data storage were all not programming state, it 402 be the low threshold voltage distribution of position of the not programming of storage unit that first threshold voltage distributes.
In addition, the expression of second threshold voltage distribution 404 has the distribution of " 01 " and the threshold voltage of the position " 1 " of the storage unit 100 of " 10 " programming state.That is to say the first threshold voltage distribution of not programming of second threshold voltage distribution 404 expression storage unit when first region of data storage or second region of data storage are programmed.In other words, second threshold voltage distribution 404 is the threshold voltage distribution of the not programming unit of storage unit under second effect.The distribution of the threshold voltage of the position " 0 " of the 3rd threshold voltage distribution 406 expression storage unit 100.In other words, the threshold voltage distribution of the program bit of the 3rd threshold voltage distribution 406 expression storage unit.
Shown in Fig. 4 A, second threshold voltage distribution 404 is also overlapped with the 3rd threshold voltage distribution 406 except overlapping with first threshold voltage distribution 402.Obviously as can be known, the operation window of the data message of reading cells is very little, does not even exist.The invention provides and read the method for operating that is stored in the first region of data storage 110a and the second region of data storage 110b data message in one of them.By using method of operating of the present invention, under second effect, can do difference with the programming state of region of data storage easily, even second threshold voltage distribution 404 and the 3rd threshold voltage distribution are overlapping and operation window read operation does not exist.Fig. 5 is the flow chart of steps according to the read method of the storage unit of the storer that one embodiment of the invention illustrated.When the data message of the first region of data storage 110a in the reading cells 100, controller 204 is by via word line W
0-W
nApply word line voltage to the conductor grid 114 of storage unit 100 and between the source/drain regions 104 of storage unit 100, apply bias voltage and carry out read step.That is to say, by first bit-line voltage being applied to source/drain regions 104 (away from the first region of data storage 110a) and will being applied to bias voltage between the source/drain regions 104 near source/drain regions 104 ground connection the finishing of the first region of data storage 110b.As shown in Figure 5, detect first electric current (step S501) that is caused by first bit-line voltage at source/drain regions 104.
In step S503, with first electric current with compare about first reference current of first bit-line voltage, and word line voltage is applied to storage unit 100.Typically, for the data message in the reading cells, apply predetermined and fixing word line voltage, and apply predetermined and fixing bit-line voltage to source/drain regions 104 away from region of data storage to be read to conductor grid 114.By the electric current that relatively produced with about the reference current of word line voltage and apply bit-line voltage to storage unit the current conversion (mapped) that is produced is programming state.If the electric current that reads is higher than reference current, storage unit is judged as a kind of logic state (promptly not programming state).In other words, if electric current is lower than reference current, then storage unit is judged to be another kind of logic state (being programming state).
Therefore, in step S505, when first electric current greater than about first reference current of first bit-line voltage time, judge that first region of data storage is programming state not.With regard to the threshold voltage of the first region of data storage 110a, electric current is high more, and then threshold voltage is low more.Therefore, when first electric current greater than about first reference current of first bit-line voltage time, the threshold voltage of the first region of data storage 110a is less than the reference voltage about reference current.Shown in Fig. 4 A, the upper limit and part second threshold voltage distribution 404 that are higher than first threshold voltage distribution 402 about the reference voltage of reference current, make the whole positions have less than the threshold voltage of reference voltage correctly to be divided into logical one, and do not have the position of logical zero to be judged to be logical one mistakenly.Therefore, when detection be higher than reference current first electric current and during from the first region of data storage 110a read data information of storage unit 100, data message among the first region of data storage 110a is judged as logical one, and the first region of data storage 110a is judged as not programming state.
In addition, because second effect increased the potential barrier of (region of data storage of contiguous another programming state) read data information from the target data storage area, therefore when working as the electric current that detected, be not easy by simply the current conversion (mapping) that is detected is judged the data message of target data storage area in the storage unit for programming state less than reference current.With regard to threshold voltage, electric current is more little, and then threshold voltage is high more.Shown in Fig. 4 A, for from target data storage area read data information, when the electric current that is detected during less than reference current, the threshold voltage of target data storage area is higher than the reference voltage about reference current.Yet, shown in Fig. 4 A,, also have the threshold voltage that is higher than reference voltage at the region of data storage of second effect the next " 1 " except the region of data storage of position " 0 " has the threshold voltage that is higher than reference voltage.Therefore, when threshold voltage is higher than reference voltage, under second effect or target data storage area meta only be the programming state of logical zero, by simply with reference to the electric current of the target data storage area that detected and be not easy to judge whether the position in the target data storage area is the logical one of storage unit.
Fig. 6 A for according to one embodiment of the invention at the following threshold voltage distribution figure of region of data storage in the storage unit of the not programming state " 11 " with multiple bit-line voltage.Fig. 6 B is for having under the programming state of multiple bit-line voltage " 00 " the threshold voltage distribution figure of data storing in the storage unit according to one embodiment of the invention.It should be noted that the bit-line voltage among Fig. 6 A, Fig. 6 B and Fig. 6 C changes and can show by the different voltages that see through external power source device detection (probing) bit line.As shown in Figure 6A, no matter how bit-line voltage changes into 1.6V and 2.3V by 1V, the pattern of the threshold voltage distribution of the position " 1 " of the storage unit 100 of " 11 " programming state is nearly all identical.In addition, getting rid of, can not offset each other about the threshold voltage distribution of different bit-line voltages because electric current changes the voltage deviation factor (voltage deviationfactor) that produces afterwards with different bit-line voltages.Similarly, shown in Fig. 6 B, obviously as can be known, the pattern of the threshold voltage distribution of the position " 0 " of the storage unit 100 of " 00 " programming state is nearly all identical.In addition, after getting rid of voltage deviation factor, threshold voltage distribution can not offset each other.The threshold voltage distribution of position " 1 " of storage unit 100 of threshold voltage distribution and " 11 " programming state of position " 0 " that it should be noted that the storage unit 100 of " 00 " programming state can not be applied in different bit-line voltages and influence.
Fig. 6 C is for having under the programming state of multiple bit-line voltage " 01 "/" 10 " the threshold voltage distribution figure of region of data storage in the storage unit according to one embodiment of the invention.Shown in Fig. 6 C, the threshold voltage distribution of the position " 0 " of the storage unit 100 of threshold voltage distribution group 602 expressions " 10 " or " 01 " programming state when bit-line voltage is changed into 1.6V, 2.3V and 3V by 1V.In addition, the threshold voltage distribution of the position " 1 " of the storage unit 100 of threshold voltage distribution group 604 expressions " 01 " or " 10 " programming state when bit-line voltage is changed into 1.6V, 2.3V and 3V by 1V.Shown in Fig. 6 C, obviously as can be known, in the threshold voltage distribution group 602 of the position " 0 " of the storage unit 100 of " 10 " or " 01 " programming state, the pattern of threshold voltage distribution much at one.In addition, after getting rid of voltage deviation factor, threshold voltage distribution can not offset each other.
Yet shown in threshold voltage distribution group 604, the pattern of the threshold voltage distribution of the position " 1 " of the storage unit 100 of " 10 " or " 01 " programming state twists a little.The most important thing is that after getting rid of voltage deviation factor, along with bit-line voltage is changed into 1.6V, 2.3V and 3V by 1V, threshold voltage distribution is towards lower threshold voltage shift.Apparently, shown in Fig. 6 A, Fig. 6 B and Fig. 6 C, only the region of data storage with position " 1 " under second effect is influenced consumingly by the change of bit-line voltage.That is to say that only position " 1 " threshold voltage distribution under second effect will be offset significantly.Therefore, when threshold voltage during greater than reference voltage (electric current that is detected is less than reference current), the data message of region of data storage can by further apply different bit-line voltages come the detection of stored unit electric current variation and judge exactly.
Particularly, shown in Fig. 4 B, when second bit-line voltage greater than first bit-line voltage is applied to source/drain regions 104 (away from region of data storage to be read) and word line voltage and keeps identical, detect second electric current.If region of data storage to be read is a programming state, the variation of the electric current that is detected under different bit-line voltages is less than or equal to voltage deviation factor (by because of applying the reference current variation expression that different bit-line voltages produces).That is to say, shown in Fig. 4 A and Fig. 4 B, with regard to threshold voltage, threshold voltage distribution 406 among contrast Fig. 4 A, the threshold voltage distribution 406 ' of region of data storage offset voltage difference D1 (be less than or equal to reference voltage difference Dr, it changes about the reference current when applying different bit-line voltage) to the right under the programming state in Fig. 4 B.
If region of data storage to be read is the not programming state with second effect, the variation of the electric current that is detected under different bit-line voltages is greater than because of applying the voltage deviation factor that different bit-line voltages produces.In other words, shown in Fig. 4 A and Fig. 4 B, with regard to threshold voltage, threshold voltage distribution 404 among contrast Fig. 4 A, threshold voltage distribution 404 ' the offset voltage difference D2 (greater than reference voltage difference Dr, it changes about the reference current when applying different bit-line voltage) to the right of region of data storage that in Fig. 4 B, has the not programming state of second effect.
Therefore, as shown in Figure 5, when first electric current during, apply second bit-line voltage (being different from first bit-line voltage) to source/drain regions 104 (away from the first region of data storage 110a) less than reference current, and it is identical that word line voltage keeps, to detect second electric current (step S507).It should be noted that second bit-line voltage is greater than first bit-line voltage.Then, in step S509, difference between second electric current and first electric current and the reference current variation that produces because of the different bit-line voltages that are applied to storage unit 100 are compared.That is to say that by getting rid of because of applying the voltage deviation factor that different bit-line voltages produces, the true performance of threshold voltage distribution can be detected after applying different bit-line voltages.Therefore, when the difference between second electric current and first electric current is less than or equal to about first reference current of first bit-line voltage and during about the difference between second reference current of second bit-line voltage, the different bit-line voltages that the threshold voltage distribution of first region of data storage is not subjected to be applied influence.Therefore, the data message of the first region of data storage 110a is judged as logical zero, and the first region of data storage 110a is judged as programming state (step S511).
On the other hand, when the difference between second electric current and first electric current greater than about first reference current of first bit-line voltage and about the difference between second reference current of second bit-line voltage time, the different bit-line voltages that the threshold voltage distribution of first region of data storage can be applied have a strong impact on.Therefore, the data message of the first region of data storage 110a is judged as the logical one with second effect, and the first region of data storage 110a is judged as not programming state (step S505).
Fig. 7 is the flow chart of steps according to the definition process nargin that one embodiment of the invention illustrated.As shown in Figure 7, before the first region of data storage 110a or the second region of data storage 110b were read or programme, the present invention comprised that more the programming of the step (step S701) of the upper limit that the low threshold voltage of define storage units distributes and define storage units confirms the step (step S703) of voltage.Significantly, the difference between the upper limit of the low threshold voltage distribution of programming affirmation voltage and storage unit can be little of 600mV.In addition, step S701 and step S703 carry out order and can not change.
Fig. 8 is the flow chart of steps according to the read method of the storage unit of the storer that one embodiment of the invention illustrated.In another embodiment of the present invention, as shown in Figure 8, detect by caused first electric current of first bit-line voltage (step S801) that is applied to source/drain regions 104 (away from region of data storage to be read).Then, in step S803, with first electric current with simulate respectively about first bit-line voltage and first reference current that is applied to the word line voltage of storage unit 100 to digital conversion be the first current digital value and the first reference number value, to note down.In step S805, the first current digital value, the first reference number value is compared, to judge the programming state of region of data storage to be read.When the first current digital value during greater than the first reference number value, region of data storage to be read is judged as not programming state (step S807).On the other hand, when the first current digital value during less than the first reference number value, the not programming state that region of data storage can't positively be taken a decision as to whether programming state or have second effect.
In addition, as shown in Figure 8, in step S809, when the first electric current digit value during less than the first reference number place value, apply second bit-line voltage (being different from first bit-line voltage) to source/drain regions 104 (away from region of data storage to be read), and the word line voltage maintenance is identical, to detect second electric current.Then, in step S811, with second electric current with simulate respectively about second bit-line voltage and second reference current that is applied to the word line voltage of storage unit 100 to digital conversion be the second current digital value and the second reference number value, to carry out record.In addition, in step S813, judge the programming state of region of data storage to be read.That is to say, the difference between the second current digital value and the first current digital value and the reference number value that different bit-line voltage produced that is applied to storage unit 100 are changed comparing.If the difference between the second current digital value and the first current digital value is less than or equal to the difference between the first reference number value and the second reference number value, judge that then region of data storage to be read is programming state (step S815).If it is the not programming state (step S807) with second effect that the difference between the second current digital value and the first current digital value, is then judged region of data storage to be read greater than the difference between the first reference number value and the second reference number value.
In the present invention, when from each region of data storage reading of data of storage unit, will be under different bit-line voltages the performance of the threshold voltage distribution of target data storage area be used for judging the programming state of target data storage area.Therefore, even operation window is very little or even do not exist, when detecting electric current less than reference current, region of data storage with position " 1 " under second effect and the region of data storage with position " 0 " can correctly be distinguished.Therefore, for the size of dwindling storage unit, operation window will no longer be to hinder.In addition, second effect for memory cell operation also alleviated.In addition because alleviated second effect and operation window very little, therefore increased program speed, and the time that has shortened memory cells.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection domain of the present invention is as the criterion when looking the scope that claim defines.
Claims (16)
1. the method for an operation store unit, this storage unit has a region of data storage, it is characterized in that, and the method for this operation store unit comprises:
Apply one first electric current that one first bit-line voltage to this storage unit detects this storage unit; And
If this first electric current is less than one first reference current, apply one second electric current that one second bit-line voltage to this storage unit detects this storage unit, and one second difference between one first difference between this first electric current and this second electric current and this first reference current and one second reference current relatively is to judge the state of this region of data storage.
2. the method for operation store according to claim 1 unit, it is characterized in that, when this first difference during greater than this second difference, this region of data storage is judged as a programming state not, and when this first difference was less than or equal to this second difference, this region of data storage was judged as a programming state.
3. the method for operation store according to claim 1 unit is characterized in that, this second bit-line voltage is greater than this first bit-line voltage.
4. the method for operation store according to claim 1 unit is characterized in that, one first word line voltage that is used to detect this first electric current equals to be used to detect one second word line voltage of this second electric current.
5. the method for operation store according to claim 1 unit is characterized in that, an operation window of this storage unit is 600mV.
6. the method for operation store according to claim 1 unit is characterized in that, more comprises:
Define a upper limit of the low threshold voltage distribution of this storage unit; And
Voltage is confirmed in a programming that defines this storage unit.
7. the method for operation store according to claim 6 unit is characterized in that, the difference between this upper limit that this programming affirmation voltage and this low threshold voltage distribute is 600mV.
8. the method for operation store according to claim 1 unit is characterized in that, when this first electric current during greater than this first reference current, this region of data storage is judged as a programming state not.
9. the method for operation store according to claim 1 unit is characterized in that, more comprises:
After detecting this first electric current, it is the form of digital value that this first electric current and this first reference current are simulated respectively to digital conversion; And
After detecting this second electric current, it is the form of digital value that this second electric current and this second reference current are simulated respectively to digital conversion.
10. a storage arrangement is characterized in that, comprising:
One storer has a plurality of storage unit, and each storage unit has a region of data storage;
One testing circuit, be used for during a read step, applying one first electric current that one first bit-line voltage to these a plurality of storage unit detect these a plurality of storage unit, if and this first electric current applies one second electric current that one second bit-line voltage to these a plurality of storage unit detect these a plurality of storage unit during less than one first reference current; And
One controller, be used for each storage unit is carried out this read step, and be used for relatively one first difference between this first electric current and this second electric current and one second difference between this first reference current and one second reference current, to judge the state of this region of data storage.
11. storage arrangement according to claim 10 is characterized in that, this second bit-line voltage is different with this first bit-line voltage.
12. storage arrangement according to claim 10 is characterized in that, this second bit-line voltage is greater than this first bit-line voltage.
13. storage arrangement according to claim 10 is characterized in that, one first word line voltage that is used to detect this first electric current equals to be used to detect one second word line voltage of this second electric current.
14. storage arrangement according to claim 10 is characterized in that, an operation window of these a plurality of storage unit is 600mV.
15. storage arrangement according to claim 10 is characterized in that, when this first electric current during greater than this first reference current, this region of data storage is judged as a programming state not.
16. storage arrangement according to claim 10, it is characterized in that, more comprise an analog-to-digital converter, be used for after detecting this first electric current this first electric current and this first reference current are converted to respectively the form of digital value, and the form that after this second electric current of detection, this second electric current and this second reference current is converted to digital value respectively.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105760582A (en) * | 2016-01-29 | 2016-07-13 | 上海华虹宏力半导体制造有限公司 | Analog control method and device for flash unit logic states |
| CN110648714A (en) * | 2018-06-26 | 2020-01-03 | 北京兆易创新科技股份有限公司 | Data reading method and device, electronic equipment and storage medium |
| CN111863084A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Method and device for controlling performance of NOR flash memory |
| CN115084147A (en) * | 2021-03-10 | 2022-09-20 | 旺宏电子股份有限公司 | Memory device and manufacturing method and operating method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8223553B2 (en) * | 2005-10-12 | 2012-07-17 | Macronix International Co., Ltd. | Systems and methods for programming a memory device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105760582A (en) * | 2016-01-29 | 2016-07-13 | 上海华虹宏力半导体制造有限公司 | Analog control method and device for flash unit logic states |
| CN105760582B (en) * | 2016-01-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | The analog control method and device of flash cell logic state |
| CN110648714A (en) * | 2018-06-26 | 2020-01-03 | 北京兆易创新科技股份有限公司 | Data reading method and device, electronic equipment and storage medium |
| CN110648714B (en) * | 2018-06-26 | 2021-03-30 | 北京兆易创新科技股份有限公司 | Data reading method and device, electronic equipment and storage medium |
| CN111863084A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Method and device for controlling performance of NOR flash memory |
| CN115084147A (en) * | 2021-03-10 | 2022-09-20 | 旺宏电子股份有限公司 | Memory device and manufacturing method and operating method thereof |
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