CN105760582B - The analog control method and device of flash cell logic state - Google Patents
The analog control method and device of flash cell logic state Download PDFInfo
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- CN105760582B CN105760582B CN201610067372.5A CN201610067372A CN105760582B CN 105760582 B CN105760582 B CN 105760582B CN 201610067372 A CN201610067372 A CN 201610067372A CN 105760582 B CN105760582 B CN 105760582B
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- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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Abstract
A kind of analog control method and device of flash cell logic state, the described method includes: applying corresponding offset voltage in the control grid of the flash cell respectively, the corresponding logic state of the flash cell is simulated, the offset voltage is corresponding with the logic state of the flash cell.Using the method and device, it can accurately control flash cell in device model extraction process and be in different logic states, improve testing efficiency.
Description
Technical field
The present invention relates to memory technology fields, and in particular to a kind of analog control method of flash cell logic state and
Device.
Background technique
Flash memory (flash memory) is used as a kind of integrated circuit memory devices, since it stores information with electrically-erasable
Function, and the information that stores will not lose after powering off, thus be widely used in such as portable computer, mobile phone, digital audio
In the electronic products such as happy player.
Storage array for storing data, and the peripheral circuit for executing reading and writing operation are provided in flash memory.Its
In, several flash cells by array arrangement are provided in the storage array.Each flash cell may include: substrate, position
Target and at least one storage organization above substrate.Each storage organization can store at least one data.
In general, each storage organization may include: a bit line electrode, a control grid and a floating gate.The control of each flash cell
Grid, target and bit line electrode are connected to control grid line and wordline and bit line.Pass through the control grid line, wordline
Different driving voltages is loaded on each electrode of flash cell with bit line, is realized to each reading and writing and erasing operation.
It in practical applications, can be by the flash memory list according to the difference of the reading value of each storage organization of flash cell
Member is divided into a variety of logic states.For example, when flash cell only includes a storage organization, according to the reading of the flash cell
The flash cell is divided into " 1 " and " 0 " two kinds of logic states by value.When flash cell includes two storage organizations, press
According to the reading value of two flash cells, the flash cell can be divided into " 01 ", " 10 " and " 11 " three kinds of logics
State.Each logic state corresponds to a curent change section of the flash cell.
In the design phase, it usually needs carry out Computer Simulation test to the performance of each flash memory peripheral circuit, and emulate and survey
During examination, needs first to extract flash cell and be under different logic states the mathematical model for respectively holding curent change.
Currently, the mode that control executes the time of erasing and write operation to flash cell is generallyd use, to control flash memory list
Member is in different logic states.Specifically, erasing and write operation first are executed to a storage organization of the flash cell, and
Timing is carried out to the execution time of aforesaid operations simultaneously.When aforesaid operations reach preset time, flash cell is executed and reads behaviour
Make, determines whether the current logic state of the flash cell meets the requirements according to the result of read operation.It is wiped by changing,
The time write can control flash cell and be in different logic states.
However, in the above-mentioned methods, the time for executing erasing and write operation to flash cell is difficult to accurately control flash memory
Unit is in corresponding logic state, and when needing to simulate multiple logic states of flash cell, and the consuming time is longer, leads
It causes model extraction testing efficiency lower, is difficult to meet user's requirement.It can not determine in advance and reach some wiping for needing state, write behaviour
Make the time, need to obtain by experiment repeatedly, obtained wiping, write operation data also do not have versatility, change other one
A unit will find suitable time conditions again.
Summary of the invention
Technical problem solved by the present invention is how to accurately control flash memory list during electronic device model extraction
Member is in different logic states, improves testing efficiency.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of simulation controlling party of flash cell logic state
Method, the flash cell include an at least storage organization, the storage organization include: a bit line electrode, one control grid and
One floating gate, which comprises
Apply corresponding offset voltage in the control grid of the flash cell respectively, it is corresponding to simulate the flash cell
Logic state, the offset voltage is corresponding with the logic state of the flash cell.
Optionally, the offset voltage obtains in the following way:
When executing read operation to each storage organization, constantly adjustment is applied to each storage organization control grid
Voltage is adjusted, until the reading electric current of the flash cell is predetermined current, it is default by the reading electric current of the flash cell
When electric current, the difference of the corresponding driving voltage for adjusting voltage and corresponding control grid is current as the flash cell
Offset voltage corresponding to logic state, wherein the predetermined current is is practically in patrolling of being simulated in the flash cell
When the state of collecting, the reading electric current when only applying the driving voltage on each electrode, the logic state one with the flash cell
One is corresponding, and the driving voltage is the voltage that can independently drive the flash cell to execute read operation.
Optionally, the digit of the offset voltage and the storage organization storing data for being performed read operation, be currently applied to
The driving voltage of each electrode of storage organization for being performed read operation, the current of the storage organization for being performed read operation are patrolled
The state of collecting and the predetermined current are related.
The embodiment of the invention also provides a kind of analog control device of flash cell logic state, the flash cell packet
An at least storage organization is included, the storage organization includes: a bit line electrode, a control grid and a floating gate, described device packet
It includes:
Storage unit, is suitable for storage offset voltage, and the offset voltage is corresponding with the logic state of the flash cell；
Logic state control unit, suitable for applying the corresponding compensation electricity in the control grid of the flash cell respectively
Pressure, simulates the corresponding logic state of the flash cell.
Optionally, the offset voltage that the storage unit is stored obtains in the following way: described depositing to each
When storage structure executes read operation, constantly adjustment is applied to the adjusting voltage that each storage organization controls grid, until the sudden strain of a muscle
The reading electric current of memory cell be predetermined current, by the reading electric current of the flash cell be predetermined current when, corresponding adjusting
The difference of the driving voltage of voltage and corresponding control grid, as compensation corresponding to the flash cell present logic state
Voltage, wherein the predetermined current is when the flash cell is practically in simulated logic state, on each electrode only
Apply the reading electric current when driving voltage, is corresponded with the logic state of the flash cell, the driving voltage is
The flash cell can be independently driven to execute the voltage of read operation.
Optionally, the storage unit is stored offset voltage and the storage organization storing data that is performed read operation
Digit, described is performed read operation at the driving voltage that is currently applied to each electrode of storage organization for being performed read operation
The present logic state of storage organization and the predetermined current are related.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
Apply offset voltage by the control grid in flash cell, and then it is corresponding to simulate the flash cell
Logic state.Since the offset voltage is corresponding with the logic state of the flash cell, the embodiment of the present invention is being utilized
In method simulation flash cell logic state when, it is only necessary to adjustment adjustment apply flash cell control grid offset voltage be
Can, relative to by control erasing, the mode of write operation time controls the logic state of flash cell, can more rapidly and essence
True simulation control flash cell is in respective logical states, and is more convenient for implementing, and is especially needing to simulate flash cell
When multiple logic states, model extraction efficiency can effectively improve.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of flash cell in the prior art；
Fig. 2 is a kind of electrical block diagram of flash cell of the embodiment of the present invention；
Fig. 3 is a kind of implementation diagram of the analog control device of flash cell logic state in the embodiment of the present invention.
Specific embodiment
Below by taking Fig. 1 and flash cell shown in Fig. 2 as an example, during the simulation test of existing flash memory performance, how
Simulation control is carried out to the logic state of flash cell to be described in detail:
Fig. 1 is the schematic diagram of the section structure of existing flash cell M0 a kind of, and the flash cell M0 is that double separate gates are brilliant
Body pipe structure, including two symmetrical storage organizations, each storage organization stores a data.Specifically, the flash memory
Unit M0 includes: substrate 100；Target 103 above the substrate 100；It is symmetrically distributed in the target 103
The first storage organization and the second storage organization of two sides.Wherein, first storage organization includes the first bit line electrode 101, the
One control grid 104 and the first floating gate 105；Second storage organization includes that the second bit line electrode 102, second controls grid 106
And second floating gate 107.First bit line electrode 101 and second bit line electrode 102 are located inside the substrate 100,
The first control grid 104, first floating gate 105, the second control grid 106 and second floating gate 107
Above the substrate 100.
Multiple flash cells shown in FIG. 1 at array arrangement formed flash array, the control grid of each flash cell, in
Between electrode and bit line electrode be connected to control grid line, wordline and bit line.It is being dodged by the control grid line, wordline and bit line
Different driving voltages is loaded on each electrode of memory cell, realizes and position is stored to the first storage position and described second
Reading and writing and erasing operation.
Fig. 2 is the circuit diagram of the flash cell M0, and the flash cell M0 includes that the first storage organization M01 and second is deposited
Storage structure M02.The first bit line electrode 101 of the flash cell M0 connects the first bit line BL1, the sudden strain of a muscle combined with Figure 1 and Figure 2,
The target 103 of the first the first control of connection of control grid 104 grid line CG1, the flash cell M0 of memory cell M0 connects
The second bit line electrode 102 of wordline WL, the flash cell M0 connect the second control of the second bit line BL2, the flash cell M0
Second control of the connection of grid 106 grid line CG2 processed.
According to the difference of the reading value of each storage organization of flash cell, above-mentioned flash cell includes four kinds of logic states,
Respectively " 00 ", " 01 ", " 10 " and " 11 ".Currently, usually being adopted when the logic state to flash cell carries out simulation control
With control to each storage organization executes erasing, write operation time mode, and by each storage organization execution read operation come
Determine whether the current logic state of the flash cell meets the requirements.
However, in practical applications, being not only difficult by controlling the time for executing erasing and write operation to each storage organization
It accurately controls flash cell and is in corresponding logic state, moreover, every control flash cell is in a kind of logic state, all need
Erasing and the time reclocking of write operation are executed to each storage organization, when the multiple logic states for needing to simulate flash cell
When, the consuming time is longer, and the efficiency for causing model extraction to be tested is lower, is difficult to meet user's requirement.
In view of the above-mentioned problems, the embodiment of the invention provides a kind of analog control methods of flash cell logic state.Institute
It states method and corresponding offset voltage is applied by the control grid in flash cell, patrolled accordingly to simulate the flash cell
The state of collecting.Since the offset voltage is corresponding with the logic state of the flash cell, in specific implementation the method
When, it is only necessary to adjustment adjustment applies the offset voltage of flash cell control grid, and need not hold again to the flash cell
Row erasing and write operation not only can be more accurately there are no that must execute erasing and write operation progress timing to the flash cell
Control flash cell is in respective logical states, and is more convenient for implementing, especially in the multiple logics for needing to simulate flash cell
When state, testing efficiency can effectively improve.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention explains in detail.
The embodiment of the invention provides a kind of analog control methods of flash cell logic state.In the embodiment of the present invention
In, the flash cell may include at least one storage organization, and each storage organization may include: a bit line electrode, one
Control grid and a floating gate.
It should be noted that each storage organization separately includes two when the flash cell only includes a storage organization
A bit line electrode, when the flash cell includes more than two storage organizations, each storage organization separately includes a bit line electricity
Pole.Each storage organization can only store the data of a bit, also can store the data of dibit or dibit or more.It can be with
Understand, the storage organization is the unit module in the flash cell for storing data, no matter the storage organization
Specific structure how, not enough at limitation of the present invention, and within the scope of the present invention
By taking the flash cell includes N number of storage organization as an example, the method is as follows:
Apply corresponding offset voltage in the control grid of the flash cell respectively, it is corresponding to simulate the flash cell
Logic state.
In specific implementation, the offset voltage includes multiple groups voltage value, and every group of voltage value corresponds to the flash cell
A kind of logic state.Offset voltage corresponding to different logic states is different.Wherein, correspondence is separately included in every group of voltage value
The voltage value that the flash cell respectively controls grid is applied under logic state.Pass through each control grid in the flash cell
Apply the offset voltage, different potentials can be coupled on floating gate so that floating gate potential under different logic states
Potential it is consistent, therefore, be applied to the offset voltage that flash cell respectively controls grid by changing, the flash memory list can be simulated
Each logic state of member.
For example, flash cell as shown in Figures 1 and 2, the flash cell includes storage organization M01 and M02, accordingly
Ground, the offset voltage include four groups of voltage values L1, L2 and L3 and L4, and wherein L1 group voltage value is to apply under logic state " 00 "
In the driving voltage of each grid of flash cell, L2 group voltage value is the drive that each grid of flash cell is applied under logic state " 01 "
Dynamic voltage, L3 group voltage value are to the driving voltage for being applied to each grid of flash cell under logic state " 10 ", L4 group voltage value
For the driving voltage for being applied to each grid of flash cell under logic state " 11 ".
In specific implementation, the offset voltage can be obtained using a variety of methods.In one embodiment of this invention, may be used
With when executing read operation to each storage organization, constantly adjustment is applied to the adjusting electricity that each storage organization controls grid
Pressure, and the reading electric current of the flash cell is monitored simultaneously.When the reading electric current of the flash cell is predetermined current by institute
When the reading electric current for stating flash cell is predetermined current, the corresponding driving voltage for adjusting voltage and corresponding control grid
Difference, as offset voltage corresponding to the flash cell present logic state.Wherein, the predetermined current is in the sudden strain of a muscle
When memory cell is practically in simulated logic state, reading electric current when only applying the driving voltage on each electrode, with
The logic state of the flash cell corresponds.
In specific implementation, the driving voltage is the voltage that can independently drive the flash cell to execute read operation.
In other words, each electrode of the flash cell is when only loading the corresponding driving voltage, i.e., executable read operation.Wherein,
The driving voltage may include multiple groups voltage value, and every group of voltage value is corresponding with the storage organization for being performed read operation, also,
It include the voltage for being applied to each electrode of flash cell corresponding with the storage organization for being performed read operation in every group of voltage value
Value.
For example, flash cell as shown in Figures 1 and 2, the flash cell includes storage organization M01 and M02, accordingly
Ground, the driving unit include two groups of voltage values L5 and L6, and wherein L5 group voltage value is when executing read operation to storage organization M01
It is applied to the driving voltage of each electrode of flash cell, L6 group voltage value is to be applied to sudden strain of a muscle when executing read operation to storage organization M02
The driving voltage of each electrode of memory cell.
By flash cell M0 shown in Fig. 2 for logic state is 30mA for " 11 " corresponding predetermined current, in determination
It, can be when executing read operation to storage organization M01 when the corresponding offset voltage of storage organization M01, constantly adjustment is applied to each
The adjusting voltage of the storage organization control grid, until the reading electric current of the flash cell is 30mA, at this point, storage organization
The corresponding offset voltage of M01 is currently applied to the adjusting voltage on storage organization M01 with storage organization M01 in the logic state
Under corresponding driving voltage difference.When determining the corresponding offset voltage of storage organization M02, can be held to storage organization M02
When row read operation, constantly adjustment is applied to the adjusting voltage that each storage organization controls grid, until the flash cell
Reading electric current is 30mA, at this point, the corresponding offset voltage of storage organization M02 is currently applied to the adjusting on storage organization M02
The difference of voltage and storage organization the M02 corresponding driving voltage under the logic state.
In specific implementation, the offset voltage is related to the digit of storage organization storing data of read operation is performed,
The digit for being performed the storage organization storing data of read operation is different, and the offset voltage may be different.In addition to this, described
Offset voltage also to be currently applied to that described to be performed the driving voltage of each electrode of storage organization of read operation related.Namely
It says, the driving voltage for being currently applied to each electrode of storage organization for being performed read operation is different, patrols accordingly to reach
The state of collecting is applied to flash cell and respectively controls the offset voltage of grid also with regard to different.Certainly, the offset voltage also with the quilt
Present logic state and the predetermined current for executing the storage organization of read operation are related.Those skilled in the art are referred to be held
The digit of the storage organization storing data of row read operation is currently applied to each electrode of storage organization for being performed read operation
Driving voltage, the present logic state of the storage organization for being performed read operation and the predetermined current phase, described in setting
Offset voltage.
Below by taking Fig. 1 and flash cell shown in Fig. 2 as an example, the method in the embodiment of the present invention is illustrated:
The logic state for assuming initially that flash cell is " 11 ".Apply corresponding mend by respectively controlling grid in flash cell
Voltage is repaid, the logic state of flash cell is simulated.It is subsequent can to corresponding storage organization execute read operation when, by sudden strain of a muscle
Each electrode of memory cell applies corresponding driving voltage again, to determine whether the logic state of flash cell meets the requirements.Specifically:
As shown in Fig. 2, being applied to the driving voltage of each electrode of flash cell M0 when executing read operation to storage organization M01
As follows respectively: the driving voltage for applying 5V by the wordline WL is applied to target by the first control grid line CG1
The driving voltage of 0V to first control grid, by it is described second control grid line CG2 apply 5V driving voltage to second control
Grid applies the driving voltage of 0V to the first bit line electrode by the first bit line BL1.
When simulating logic state " 00 " of flash cell M0, it is obtained ahead of time and is applied to the first control grid and the second control
The offset voltage of grid is -5V, applies corresponding offset voltage respectively in the first control grid and the second control grid
Simulate the logic state of simulation flash cell M0 " 00 ".It is subsequent to storage organization M01 execute read operation when, institute can be passed through
The driving voltage of wordline WL application 5V is stated to target, passes through voltage (that is: the 0V of the first control grid line CG1 application -5V
Driving voltage and -5V offset voltage) to first control grid, pass through it is described second control grid line CG2 apply 0V voltage
(that is: the offset voltage of the driving voltage of 5V and -5V) applies the drive of 0V by the first bit line BL1 to the second control grid
Dynamic voltage by the second bit line electrode of the flash cell M0 and is read to the first bit line electrode by the second bit line BL2
Circuit connection.When executing read operation to storage organization M02, switching applies the driving voltage of other each electrodes, and passes through first
The first bit line electrode of the flash cell M0 is connect by bit line BL1 with reading circuit.According to the reading of storage organization M01 and M02
Value, judges whether simulated logic state meets the requirements.
When simulating logic state " 01 " of flash cell M0, the offset voltage for being applied to the first control grid is obtained ahead of time
Offset voltage for -5V, the second control grid is 0V, applies corresponding benefit respectively in the first control grid and the second control grid
Voltage is repaid, the logic state of simulation flash cell M0 " 01 " can be simulated.It is subsequent that read operation is being executed to storage organization M01
When, the driving voltage of 5V can be applied by the wordline WL to target, pass through the first control grid line CG1 application-
The voltage (that is: the offset voltage of the driving voltage of 0V and -5V) of 5V passes through the second control grid line to the first control grid
CG2 applies the voltage (that is: the offset voltage of the driving voltage of 5V and 0V) of 5V to the second control grid, passes through first bit line
BL1 applies the driving voltage of 0V to the first bit line electrode, by the second bit line BL2 by the second of the flash cell M0
Line electrode is connect with reading circuit.Switching applies the driving voltage of other each electrodes, and passes through the first bit line BL1 for the flash memory
The first bit line electrode of unit M0 is connect with reading circuit.It is simulated according to the reading value of storage organization M01 and M02, judgement
Whether logic state meets the requirements.
When simulating logic state " 10 " of flash cell M0, the offset voltage for being applied to the first control grid is obtained ahead of time
Offset voltage for 0V, the second control grid is -5V, applies corresponding benefit respectively in the first control grid and the second control grid
Voltage is repaid, the logic state of simulation flash cell M0 " 10 " can be simulated.It is subsequent that read operation is being executed to storage organization M01
When, the driving voltage of 5V can be applied by the wordline WL to target, 0V is applied by the first control grid line CG1
Voltage (that is: the offset voltage of the driving voltage of 0V and 0V) to first control grid, by it is described second control grid line CG2 apply
Add the voltage (that is: the offset voltage of the driving voltage of 5V and -5V) of 0V to the second control grid, passes through the first bit line BL1
Apply the driving voltage of 0V to the first bit line electrode, by the second bit line BL2 by the second bit line of the flash cell M0
Electrode is connect with reading circuit.When executing read operation to storage organization M02, switching applies the driving voltage of other each electrodes,
And the first bit line electrode of the flash cell M0 is connect with reading circuit by the first bit line BL1.According to storage organization M01
And the reading value of M02, judge whether simulated logic state meets the requirements.
When simulating logic state " 11 " of flash cell M0, it is obtained ahead of time and is applied to the first control grid and the second control
The offset voltage of grid is 0V, applies corresponding offset voltage respectively in the first control grid and the second control grid
Simulate the logic state of simulation flash cell M0 " 11 ".It is subsequent to storage organization M01 execute read operation when, institute can be passed through
The driving voltage of wordline WL application 5V is stated to target, passes through voltage (that is: the 0V that the first control grid line CG1 applies 0V
Driving voltage and 0V offset voltage) to first control grid, pass through it is described second control grid line CG2 apply 5V voltage
(that is: the offset voltage of the driving voltage of 5V and 5V) applies the driving of 0V by the first bit line BL1 to the second control grid
Voltage by the second bit line electrode of the flash cell M0 and reads electricity by the second bit line BL2 to the first bit line electrode
Road connection.When executing read operation to storage organization M02, switching applies the driving voltage of other each electrodes, and passes through first
The first bit line electrode of the flash cell M0 is connect by line BL1 with reading circuit.According to the reading of storage organization M01 and M02
Value, judges whether simulated logic state meets the requirements.
It should be noted that the analog control method in the embodiment of the present invention, in the specific implementation, however it is not limited to Fig. 1 and
Flash cell is shown in Fig. 2, can also using in the flash cell of other structures.It is specific no matter the structure of the flash cell
How, not enough at limitation of the present invention, and it is within the scope of the present invention.
As shown in the above, using the analog control method in the embodiment of the present invention, the flash cell is being simulated
When each logic state, directly adjustment is applied to each offset voltage for controlling grid, can simulate patrolling for the flash cell
The state of collecting, relative to by adjusting erasing, the mode for the time write is easier to accurately control the state of flash cell, save whole
The time of a test process, effectively improve testing efficiency.
In order to more fully understand those skilled in the art and realize the present invention, below to device corresponding to the above method
It is described in detail.
The embodiment of the invention also provides a kind of analog control device of flash cell logic state, the flash cell packet
An at least storage organization is included, the storage organization includes: a bit line electrode, a control grid and a floating gate.
Referring to Fig. 3, the analog control device 30 of the flash cell logic state may include: storage unit 31 and patrol
Collect status control unit 32.Wherein:
The storage unit 31 is suitable for storage offset voltage, the logic state of the offset voltage and the flash cell
It is corresponding；
The logic state control unit 32 applies suitable for respectively in the control grid of the flash cell corresponding described
Offset voltage simulates the corresponding logic state of the flash cell.
In specific implementation, the offset voltage that the storage unit 31 is stored obtains in the following way: right
When each storage organization executes read operation, constantly adjustment is applied to the adjusting voltage that each storage organization controls grid, directly
To the flash cell reading electric current be predetermined current, by the reading electric current of the flash cell be predetermined current when, institute it is right
That answers adjusts the difference of the driving voltage of voltage and corresponding control grid, right as the flash cell present logic state institute
The offset voltage answered, wherein the predetermined current is when the flash cell is practically in simulated logic state, each
Only apply the reading electric current when driving voltage on electrode, is corresponded with the logic state of the flash cell, the drive
Dynamic voltage is the voltage that can independently drive the flash cell to execute read operation.
In specific implementation, the offset voltage that the storage unit 31 is stored is deposited with the storage organization for being performed read operation
The digit for storing up data, described is performed the driving voltage for being currently applied to each electrode of storage organization for being performed read operation
The present logic state of the storage organization of read operation and the predetermined current are related.
In specific implementation, as described in Figure 3, the analog control device 30 of the flash cell logic state can be with flash memory
Unit 40 connects, and when simulating the Different Logic state of flash cell 40, is controlled by the simulation of the flash cell logic state
Device 30, which changes, is applied to the offset voltage that flash cell 40 respectively controls grid.Wherein, the specific change side of the offset voltage
Formula with no restriction, for example can be changed by program instruction.
Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of above-described embodiment is can
It is completed with instructing relevant hardware by program, which can be stored in a computer readable storage medium, storage
Medium may include: ROM, RAM, disk or CD etc..
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (6)
1. a kind of analog control method of flash cell logic state, the flash cell includes an at least storage organization, described
Storage organization includes: bit line electrode, control grid and floating gate characterized by comprising
Apply corresponding offset voltage in the control grid of the flash cell respectively, simulates the flash cell and patrol accordingly
The state of collecting, the offset voltage are corresponding with the logic state of the flash cell.
2. the analog control method of flash cell logic state as described in claim 1, which is characterized in that the offset voltage
It obtains in the following way:
When executing read operation to each storage organization, constantly adjustment is applied to the adjusting that each storage organization controls grid
Voltage, until the reading electric current of the flash cell is predetermined current, it is predetermined current by the reading electric current of the flash cell
When, the difference of the corresponding driving voltage for adjusting voltage and corresponding control grid, as the flash cell current logic
Offset voltage corresponding to state, wherein the predetermined current is is practically in simulated logic shape in the flash cell
When state, reading electric current when only applying the driving voltage on each electrode is a pair of with the logic state one of the flash cell
It answers, the driving voltage is the voltage that can independently drive the flash cell to execute read operation.
3. the analog control method of flash cell logic state as claimed in claim 2, which is characterized in that the offset voltage
With the digit of the storage organization storing data for being performed read operation, currently to be applied to the storage organization for being performed read operation each
The driving voltage of electrode, the present logic state of the storage organization for being performed read operation and the predetermined current are related.
4. a kind of analog control device of flash cell logic state, the flash cell includes an at least storage organization, described
Storage organization includes: bit line electrode, control grid and floating gate characterized by comprising
Storage unit, is suitable for storage offset voltage, and the offset voltage is corresponding with the logic state of the flash cell；
Logic state control unit, suitable for applying the corresponding offset voltage in the control grid of the flash cell respectively,
Simulate the corresponding logic state of the flash cell.
5. the analog control device of flash cell logic state as claimed in claim 4, which is characterized in that the storage unit
The offset voltage stored obtains in the following way:
When executing read operation to each storage organization, constantly adjustment is applied to the adjusting that each storage organization controls grid
Voltage, until the reading electric current of the flash cell is predetermined current, it is predetermined current by the reading electric current of the flash cell
When, the difference of the corresponding driving voltage for adjusting voltage and corresponding control grid, as the flash cell current logic
Offset voltage corresponding to state, wherein the predetermined current is is practically in simulated logic shape in the flash cell
When state, reading electric current when only applying the driving voltage on each electrode is a pair of with the logic state one of the flash cell
It answers, the driving voltage is the voltage that can independently drive the flash cell to execute read operation.
6. the analog control device of flash cell logic state as claimed in claim 5, which is characterized in that the storage unit
The digit of the offset voltage that is stored and the storage organization storing data for being performed read operation is currently applied to and described is performed reading
The driving voltage of each electrode of the storage organization of operation, the present logic state of the storage organization for being performed read operation and institute
State predetermined current correlation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610067372.5A CN105760582B (en) | 2016-01-29 | 2016-01-29 | The analog control method and device of flash cell logic state |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610067372.5A CN105760582B (en) | 2016-01-29 | 2016-01-29 | The analog control method and device of flash cell logic state |
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| Publication Number | Publication Date |
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| CN101887749A (en) * | 2009-05-13 | 2010-11-17 | 旺宏电子股份有限公司 | Storage device and operating method thereof |
| CN102867544A (en) * | 2012-09-19 | 2013-01-09 | 上海宏力半导体制造有限公司 | Method of testing storage array and control device |
| CN103824593A (en) * | 2014-03-07 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Operating method for flash memory unit |
| CN104599716A (en) * | 2015-01-31 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | Judgment method for logic state read-out value of flash memory unit |
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| US8503252B2 (en) * | 2011-05-31 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sense amplifier circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101887749A (en) * | 2009-05-13 | 2010-11-17 | 旺宏电子股份有限公司 | Storage device and operating method thereof |
| CN102867544A (en) * | 2012-09-19 | 2013-01-09 | 上海宏力半导体制造有限公司 | Method of testing storage array and control device |
| CN103824593A (en) * | 2014-03-07 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Operating method for flash memory unit |
| CN104599716A (en) * | 2015-01-31 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | Judgment method for logic state read-out value of flash memory unit |
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