CN102867544A - Method of testing storage array and control device - Google Patents
Method of testing storage array and control device Download PDFInfo
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- CN102867544A CN102867544A CN2012103498289A CN201210349828A CN102867544A CN 102867544 A CN102867544 A CN 102867544A CN 2012103498289 A CN2012103498289 A CN 2012103498289A CN 201210349828 A CN201210349828 A CN 201210349828A CN 102867544 A CN102867544 A CN 102867544A
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Abstract
The invention discloses a method of testing a storage array and a control device. In the storage array, storage units in a same line share a bit line, storage units in a same row share a word line, and the storage units in every two rows share a same source line. The testing method comprises the following steps of: applying a source line testing voltage to all source lines connected with the storage units; applying a bit line testing voltage which is not equal to 0V to all bit lines connected with the storage units; applying a 0V voltage to all word lines connected with the storage units; after preset testing time, removing the applied testing voltage, reading a testing current of each storage unit, comparing the testing current with a reference current, and outputting a comparison result; and according to the comparison result, judging whether each storage unit is qualified or not, wherein the bit line testing voltage is smaller than the source line testing voltage. With the adoption of the method of testing the storage array and the control device provided by the technical scheme of the invention, the testing time of the storage array formed by storage units in a small size is reduced.
Description
Technical field
The present invention relates to the memory technology field, relate in particular to and be easy to produce method and the control device that is listed as the storage unit of crosstalking in a kind of test storage array.
Background technology
But owing to having high speed, high density micro, still can keep the plurality of advantages such as data after cutting off the power supply, nonvolatile memory (NVM, Nonvolatile memory) as a kind of integrated circuit memory devices, is widely used in as in the electronic products such as portable computer, mobile phone, digital music player.Usually, difference according to the transistor grid structure that consists of storage unit, the non-volatile memory cells structure is divided into two kinds: piled grids and splitting grid structure, wherein splitting grid memory cell was because effectively avoided crossing erasure effect and have higher programming efficiency and be widely applied.
Fig. 1 is a kind of structural representation of splitting grid storage array, described splitting grid storage array comprises a plurality of storage unit that are arranged in array (being memory transistor), and is used for selecting described storage unit and many word lines, bit line and the source line that drives signal being provided.Particularly, this splitting grid storage array comprise k+1 bar word line (WL0, WL1, WL2, WL3 ..., WLk-1, WLk), the n+1 bit lines (BL0, BL1 ..., BLn) and m+1 bar source line (SL0, SL1 ..., SLm).The grid of each splitting grid memory cell, drain electrode, source electrode are connected with word line, bit line, source line respectively, wherein, the storage unit of same row shares a bit lines, storage unit with delegation shares a word line, and the storage unit of per two row shares a source line, for example, from the first row storage unit, the first row and the second line storage unit common source line SL0, the third line and fourth line storage unit common source line SL1, by that analogy.
To a storage unit a(in the described storage array of Fig. 1 referred to as Destination Storage Unit) be programmed for example, the Control of Voltage process of each signal wire is comprised: apply word line program voltage Vgp to the word line WL0 that is connected with storage unit a; Apply source line program voltage Vsp to the source line SL0 that is connected with storage unit a; Apply program current Id to the bit line BL0 that is connected with storage unit a, produce bit line program voltage Vdp at bit line BL0 simultaneously; Apply 0V voltage to all word lines of residue except WL0 (WL1, WL2, WL3 ..., WLk-1, WLk); Apply source line bias voltage Vsbs to the active line of residue except SL0 (SL1 ..., SLm); Apply bit line pre-programmed voltage Vinh to all bit lines of residue except BL0 (BL1 ..., BLn).In actual applications, can determine according to circuit structure and device property etc. the value of described word line program voltage, source line program voltage, program current, source line bias voltage, bit line pre-programmed voltage.
In the above-mentioned programming operation, owing to reasons such as manufacturing process, may there be defective in the non-Destination Storage Unit (for example storage unit b) of not programming with storage unit a shared bit line, when program current Id injects bit line BL0, non-Destination Storage Unit a large amount of electronics under the effect of internal electric field flow to the source region by the drain region, produce row and crosstalk, affect the normal programming of storer.Therefore, need to test the storage array that new system is produced, pick out and exist defective to be easy to produce the storage unit that row are crosstalked, compensate with the row or column of the redundancy of storage unit, crosstalk if too much storage unit exists defective to be easy to produce row, so whole storage array will be dropped.
In the prior art, storage array is easy to produce the conventionally test method that is listed as the storage unit of crosstalking, take the described storage array of Fig. 1 as example, test process comprises: apply source line test voltage Vp to the active line that is connected with storage unit (SL0, SL1 ... SLm), apply 0V voltage to all bit lines (BL0, the BL1 that are connected with storage unit,, BLn), apply 0V voltage to all word line (WL0 that are connected with storage unit, WL1, WL2, WL3,, WLk-1, WLk).In actual applications, can be according to the value of definite source line test voltages such as circuit structure and device property.After applying test voltage, read the measuring current of each storage unit, compare by measuring current and the predefined reference current that each storage unit is produced, judge being easy to produce and being listed as the storage unit of crosstalking of existing in the storage array.
Yet, storage array for small size storage unit (channel length that is memory cell transistor reduces) composition, because drain-induced barrier reduces (DIBL, Drain induction barrier lower) existence of effect, if adopt above-mentioned method of testing, the source region is injected into the electron amount increase of raceway groove during test, the test result that will lead to errors, and soon difficult generation is listed as the normal memory cell of crosstalking and thinks that easy generation is listed as the defective storage unit of crosstalking by mistake.In such cases, the test of the storage array that the small size storage unit is formed has adopted user model to carry out, namely certain storage unit is programmed, read the electric current with other storage unit of this storage unit shared bit line, electric current and the reference current of each storage unit are compared, judge exist in the storage array be easy to produce the storage unit that row are crosstalked.The method of testing of this storage array that the small size storage unit is formed is lost time very much, has greatly increased testing cost.
Summary of the invention
What the present invention solved is the long problem of storage array test duration that test small size storage unit forms.
For addressing the above problem, the invention provides a kind of method of test storage array, in the described storage array, the storage unit of same row shares a bit lines, storage unit with delegation shares a word line, per two line storage units share a source line, and described method of testing comprises: apply source line test voltage to the active line that is connected with storage unit; Apply not bitline test voltage for 0V to all bit lines that are connected with storage unit; Apply 0V voltage to all word lines that are connected with storage unit; After time, remove the test voltage that applies through presumptive test, read the measuring current of each storage unit, described measuring current and reference current are compared, the output comparative result; According to described comparative result, judge whether each storage unit is qualified; Wherein, described bitline test voltage is less than described source line test voltage.
Optionally, the span of described source line test voltage is 4V to 6V.
Optionally, the span of described bitline test voltage is 0.1V to 0.6V.
Optionally, the span of described presumptive test time is 1ms to 100ms.
Optionally, the span of described reference current is 4 μ A to 10 μ A.
For addressing the above problem, the present invention also provides a kind of control device of test storage array, in the described storage array, the storage unit of same row shares a bit lines, storage unit with delegation shares a word line, per two line storage units share a source line, and the control device of described test storage array comprises: line traffic control unit, source is used for applying source line test voltage to the active line that is connected with storage unit; The bit line control module is used for applying bitline test voltage for 0V to all bit lines that are connected with storage unit; Word line traffic control unit is used for applying 0V voltage to all word lines that are connected with storage unit; Read comparing unit, be used for reading the measuring current of each storage unit, described measuring current and reference current are compared, the output comparative result; Judging unit is used for judging according to described comparative result whether each storage unit is qualified; Wherein, described bitline test voltage is less than described source line test voltage.The control device of described test storage array comprises that also bitline test voltage provides the unit, for generation of described bitline test voltage.
Optionally, described bitline test voltage provides the unit to comprise: reference voltage source, for generation of reference voltage; The output buffer cell is used for amplifying the reference voltage that described reference voltage source produces, and obtains described bitline test voltage.
Optionally, described reference voltage source is the first band gap reference.
Optionally, described reference voltage source comprises: the second band gap reference comprises reference voltage output end; The voltage follow unit comprises control voltage input end and reference voltage output terminal, and described control voltage input end is connected with described reference voltage output end.
Optionally, described voltage follow unit comprises NMOS pipe and reference current source, described reference current source one end ground connection, the other end is connected with the source electrode of a described NMOS pipe and as described reference voltage output terminal, the grid of a described NMOS pipe is described control voltage input end, and the drain electrode of a described NMOS pipe connects supply voltage.
Optionally, described reference voltage source is virtual array.
Compared with prior art, technical scheme of the present invention has the following advantages: the test of the storage array that the small size storage unit is formed is user's pattern not, but adopts the method after conventionally test improved.Can not adopt the conventionally test method to the storage array that the small size storage unit forms is because there is the DIBL phenomenon in undersized storage unit, affect the threshold voltage of storage unit, threshold voltage is reduced, when using the conventional method test, the electron amount that larger subthreshold current makes the source region be injected into raceway groove increases, the measuring current of the storage unit that reads can be bigger than normal, the test result that leads to errors.Storage array as described in Figure 1 have a difference between memory cell gate, drain electrode pressure reduction and the threshold voltage, and subthreshold current is index variation with described difference, and the variation that namely described difference is very little will cause the acute variation of subthreshold current.Technical scheme of the present invention, when the storage array that the small size storage unit is formed is tested, apply source line test voltage to the active line that is connected with storage unit, apply not bitline test voltage for 0V to all bit lines that are connected with storage unit, apply 0V voltage to all word lines that are connected with storage unit, make memory cell gate, difference between drain electrode pressure reduction and the threshold voltage changes, reduce subthreshold current, so that the measuring current of the storage unit that reads can reflect truly whether the storage unit of testing exists defective to be easy to produce row and crosstalk, and has effectively shortened the test duration of the storage array that the small size storage unit is formed.
Description of drawings
Fig. 1 is a kind of structural representation of splitting grid storage array;
Fig. 2 is the method flow schematic diagram of the test storage array of embodiment of the present invention;
Fig. 3 is the structural representation of control device of the test storage array of embodiment of the present invention;
Fig. 4 is the structural representation of control device of the test storage array of the embodiment of the invention.
Fig. 5 is the structural representation of the reference voltage source of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with drawings and Examples the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background art, the storage array that the small size storage unit is formed is easy to produce the test that row are crosstalked, prior art is undertaken by user model, because this method of testing need to be tested respectively every array storage unit, compares very with the method for testing of routine and loses time.Therefore, the inventor considers whether the method for testing of routine can be improved, and is used for the test of the storage array of small size storage unit composition, shortens the test duration.
Fig. 2 is the schematic flow sheet of method of the test storage array of embodiment of the present invention, this method is used for the storage array that described small size storage unit forms is easy to produce the test that row are crosstalked, in the described storage array, the storage unit of same row shares a bit lines, storage unit with delegation shares a word line, and per two line storage units share a source line; The method of described test storage array comprises:
Step S21: apply source line test voltage to the active line that is connected with storage unit;
Step S22: apply not bitline test voltage for 0V to all bit lines that are connected with storage unit, described bitline test voltage is less than described source line test voltage;
Step S23: apply 0V voltage to all word lines that are connected with storage unit;
Step S24: after the time, remove the test voltage that applies through presumptive test, read the measuring current of each storage unit, described measuring current and reference current are compared, the output comparative result;
Step S25: according to described comparative result, judge whether each storage unit is qualified.
Need to prove, in the above-mentioned steps voltage of each signal wire being applied is when storage array is carried out test operation, time sequential routine by test is applied to each voltage on the corresponding signal wire, in general, above-mentionedly each signal wire is executed alive operation can carry out simultaneously.
Method corresponding to the test storage array of embodiment of the present invention, embodiment of the present invention also provides a kind of control device of test storage array, see also the structural representation of control device of the test storage array of embodiment of the present invention shown in Figure 3, in the described storage array 30, the storage unit of same row shares a bit lines, storage unit with delegation shares a word line, and per two line storage units share a source line; The control device of described test storage array comprises:
Line traffic control unit, source 31 is used for applying source line test voltage to the active line that is connected with storage unit;
Bit line control module 32 is used for applying bitline test voltage for 0V to all bit lines that are connected with storage unit;
Word line traffic control unit 33 is used for applying 0V voltage to all word lines that are connected with storage unit;
Read comparing unit 34, be used for reading the measuring current of each storage unit, described measuring current and reference current are compared, the output comparative result;
Wherein, described bitline test voltage is less than described source line test voltage.
Below in conjunction with drawings and Examples technical solution of the present invention is described in detail, in the present embodiment, suppose that storage array as shown in Figure 1 is comprised of the small size storage unit, describe as example as shown in Figure 1 storage array is easy to produce test that row crosstalk.
At first, tested storage array is applied test voltage, i.e. execution in step S21 ~ step S23.Particularly, by line traffic control unit, source 31 control, the active line that is connected with storage unit (SL0, SL1 ..., apply source line test voltage Vp on SLm); By bit line control module 32 control, all bit lines that are connected with storage unit (BL0, BL1 ..., apply bitline test voltage Vx on BLn); By word line traffic control unit 33 control, all word lines that are connected with storage unit (WL0, WL1, WL2, WL3 ..., WLk-1, WLk) on apply 0V voltage.
Described source line test voltage Vp, bitline test voltage Vx can preset according to circuit structure and device property etc.Wherein, line test voltage Vp is same as the prior art in the source, and bitline test voltage Vx need satisfy: Vx＜Vp.In the present embodiment, the span of described source line test voltage Vp is 4V to 6V, and the span of described bitline test voltage Vx is 0.1V to 0.6V.
Execution in step S24 after the time, removes the test voltage that applies through presumptive test, reads the measuring current of each storage unit, described measuring current and reference current is compared the output comparative result.Particularly, pass through presumptive test after the time, remove the test voltage that applies, realize reading of storage unit measuring currents and comparison by reading comparing unit 34.In the present embodiment, the span of described presumptive test time is 1ms to 100ms, and the described comparing unit 34 that reads can be sense amplifier.Sense amplifier can read the measuring current of each storage unit, and described measuring current and reference current are compared, output comparative result binary condition 0 or 1.Described reference current is less than the electric current that storage array is carried out programming operation storage unit when normally reading binary condition 1, in the present embodiment, the span of described reference current is 4 μ A to 10 μ A, if described measuring current is less than described reference current, then export binary condition 0, otherwise output binary condition 1.
Those skilled in the art should be appreciated that the described comparing unit that reads also can by other forms of circuit structure realization, for example contain the reading circuit of computing comparer.
Execution in step S25 according to described comparative result, judges whether each storage unit is qualified.Particularly, realized by judging unit 35.In the present embodiment, if described comparative result is binary condition 0, prove that then tested storage unit is difficult for producing the electronics that is flowed to the source region by the drain region, storage unit is judged as qualified, is not to exist defective easily to produce the storage unit that row are crosstalked; If described comparative result is binary condition 1, then tested storage unit is judged as defective.
Further, as shown in Figure 4, the bitline test voltage Vx of the present embodiment can also provide unit 36 to provide by bitline test voltage.
Particularly, described bitline test voltage provides unit 36 to comprise: reference voltage source 41, for generation of reference voltage Vx-p; Output buffer cell 42 is used for amplifying the reference voltage Vx-p that described reference voltage source produces, and obtains described bitline test voltage Vx.
Optionally, described reference voltage source 41 is the first band gap reference, produces a temperature independent reference voltage Vx-p.
Optionally, as shown in Figure 5, described reference voltage source 41 comprises: the second band gap reference 51 comprises reference voltage output end; Voltage follow unit 52 comprises control voltage input end and reference voltage output terminal, and described control voltage input end is connected with described reference voltage output end.
In the present embodiment, described voltage follow unit 52 comprises NMOS pipe MN1 and reference current source, described reference current source one end ground connection, the other end is connected with the source electrode of described NMOS pipe MN1 and as described reference voltage Vx-p output terminal, the grid of described NMOS pipe MN1 is described control voltage input end, and the MN1 drain electrode of a described NMOS pipe connects supply voltage VDD.Because raising with temperature, reduces the threshold voltage of the pipe of the NMOS in the voltage follow unit 52 MN1, be consistent with the temperature variant situation of the threshold voltage of storage unit in the storage array, when test, can reduce because the impact that temperature variation is brought test result.Namely when temperature raise, the threshold voltage of storage unit reduced, and subthreshold current increases thereupon, and the source region is injected into corresponding the increasing of electronics of raceway groove.On the other hand, the threshold voltage of NMOS pipe MN1 in the voltage follow unit 52 also reduces with the rising of temperature, the reference voltage Vx-p of output increases thereupon, the corresponding increase of bitline test voltage Vx, can effectively reduce the subthreshold current in the storage unit, reduce by the temperature variation impact that test brings to storage unit.
Optionally, described reference voltage source 41 is virtual array.The structure of the storage unit in the structure of the storage unit in the described virtual array and the storage array 30 is identical, the memory capacity of described virtual array is much smaller than the memory capacity of storage array 30, by described virtual array being carried out programming operation generating reference voltages Vx-p.Particularly, apply word line voltage Vg, the source line of described virtual array is applied source line voltage Vd, the bit line of described virtual array is injected bias current I to produce bit-line voltage by the word line to described virtual array.The bit-line voltage of described virtual array is reference voltage Vx-p, and described reference voltage Vx-p can follow the variation of storage unit threshold voltage in the storage array 30, reduces the impact that test result is brought by bitline test voltage Vx.Described word line voltage Vg, source line voltage Vd, bias current I can preset according to circuit structure and device property etc.In the present embodiment, the span of described word line voltage Vg is 1.2V to 2V, and the span of described source line voltage Vd is 4V to 6V, and the span of described bias current I is 1 μ A to 5 μ A.
To sum up, technique scheme by apply source line test voltage to the active line of institute that is connected with storage unit, apply not all bit lines that the bitline test voltage for 0V extremely is connected with storage unit, apply all word lines that 0V voltage extremely is connected with storage unit, the storage array that the small size storage unit is formed not user's pattern is tested, effectively shortened the test duration, overcome because the disconnected problem of test result erroneous judgement that the DIBL phenomenon that the small size storage unit exists causes.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.
Claims (15)
1. the method for a test storage array, in the described storage array, the storage unit of same row shares a bit lines, shares a word line with the storage unit of delegation, and per two line storage units share a source line, it is characterized in that, comprising:
Apply source line test voltage to the active line that is connected with storage unit;
Apply not bitline test voltage for 0V to all bit lines that are connected with storage unit;
Apply 0V voltage to all word lines that are connected with storage unit;
After time, remove the test voltage that applies through presumptive test, read the measuring current of each storage unit, described measuring current and reference current are compared, the output comparative result;
According to described comparative result, judge whether each storage unit is qualified;
Wherein, described bitline test voltage is less than described source line test voltage.
2. the method for test storage array according to claim 1 is characterized in that, the span of described source line test voltage is 4V to 6V.
3. the method for test storage array according to claim 1 is characterized in that, the span of described bitline test voltage is 0.1V to 0.6V.
4. the method for test storage array according to claim 1 is characterized in that, the span of described presumptive test time is 1ms to 100ms.
5. the method for test storage array according to claim 1 is characterized in that, the span of described reference current is 4 μ A to 10 μ A.
6. the control device of a test storage array, in the described storage array, the storage unit of same row shares a bit lines, shares a word line with the storage unit of delegation, and per two line storage units share a source line, it is characterized in that, comprising:
Line traffic control unit, source is used for applying source line test voltage to the active line that is connected with storage unit;
The bit line control module is used for applying bitline test voltage for 0V to all bit lines that are connected with storage unit;
Word line traffic control unit is used for applying 0V voltage to all word lines that are connected with storage unit;
Read comparing unit, be used for reading the measuring current of each storage unit, described measuring current and reference current are compared, the output comparative result;
Judging unit is used for judging according to described comparative result whether each storage unit is qualified;
Wherein, described bitline test voltage is less than described source line test voltage.
7. the control device of test storage array according to claim 6 is characterized in that, also comprises: bitline test voltage provides the unit, for generation of described bitline test voltage.
8. the control device of test storage array according to claim 7 is characterized in that, described bitline test voltage provides the unit to comprise:
Reference voltage source is for generation of reference voltage;
The output buffer cell is used for amplifying the reference voltage that described reference voltage source produces, and obtains described bitline test voltage.
9. the control device of test storage array according to claim 8 is characterized in that, described reference voltage source is the first band gap reference.
10. the control device of test storage array according to claim 8 is characterized in that, described reference voltage source comprises:
The second band gap reference comprises reference voltage output end;
The voltage follow unit comprises control voltage input end and reference voltage output terminal, and described control voltage input end is connected with described reference voltage output end.
11. the control device of test storage array according to claim 10, it is characterized in that, described voltage follow unit comprises NMOS pipe and reference current source, described reference current source one end ground connection, the other end is connected with the source electrode of a described NMOS pipe and as described reference voltage output terminal, the grid of a described NMOS pipe is described control voltage input end, and the drain electrode of a described NMOS pipe connects supply voltage.
12. the control device of test storage array according to claim 8 is characterized in that, described reference voltage source is virtual array.
13. the control device of test storage array according to claim 6 is characterized in that, the span of described source line test voltage is 4V to 6V.
14. the control device of test storage array according to claim 6 is characterized in that, the span of described bitline test voltage is 0.1V to 0.6V.
15. the control device of test storage array according to claim 6 is characterized in that, the span of described reference current is 4 μ A to 10 μ A.
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| CN111816241A (en) * | 2020-08-21 | 2020-10-23 | 上海燧原科技有限公司 | Memory and test method thereof |
| WO2023168806A1 (en) * | 2022-03-09 | 2023-09-14 | 长鑫存储技术有限公司 | Memory failure testing method and apparatus, and storage medium and electronic device |
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