JP2004164700A - Nonvolatile semiconductor storage device and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the rewriting durability of a memory cell and to remarkably improve the reliability for reading data. <P>SOLUTION: A verify sense amplifier circuit 7 is arranged in a flash memory. The verify sense amplifier circuit 7 produces a discrimination current at verifying in accordance with the gate voltage Vgi produced by a voltage generating circuit. The level of this discrimination current is the current level at the same degree as those of respective memory currents of the memory cell S, capable of discriminating that the current at reading is flowing or not. Thus, by securing the memory current required for reading at verifying, the reliability of data reading is improved even for the memory cell S deteriorated by rewriting of data. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for verifying a nonvolatile memory, and more particularly to a technology effective when applied to ensuring the reliability of data reading due to deterioration of a memory cell caused by data rewriting.
[0002]
[Prior art]
Conventionally, EEPROMs and flash memories have been known as electrically rewritable nonvolatile memories.
[0003]
The EEPROM has, as a charge storage layer, a nitride film having a plurality of local charge trapping regions in an insulating region, and performs writing / erasing to rewrite data. This EEPROM changes the threshold voltage by trapping charges in the charge trapping region and enables data storage. However, since the number of charge trapping regions is finite, the change in the threshold voltage can be reduced. Therefore, when writing / erasing a memory cell, a high voltage for injecting electrons into the charge storage layer or performing a hot hole write must be applied to the memory cell for a predetermined period of time. Then, the writing / erasing is completed. The rewriting operation in the EEPROM is described in Patent Document 1.
[0004]
A flash memory is a nonvolatile memory that has a conductive floating gate as a charge storage layer and is electrically rewritable by injecting or extracting charge into or from the floating gate, and performs writing / erasing to rewrite data. . In a flash memory, since the floating gate is conductive, the threshold voltage of a memory cell varies more widely than in an EEPROM. The procedure for writing / erasing this flash memory will be described below.
[0005]
First, a high voltage causing a write / erase operation is applied to a memory array or the like for a predetermined time. Next, verify is performed, and if the write / erase level has reached a predetermined value, the write / erase ends.
[0006]
If the write / erase level has not reached the predetermined value, a high voltage causing a write / erase operation is applied again for a predetermined time, verified, and the operation is repeated until the write / erase level reaches the predetermined level. As described above, the verification is performed to set the write / erase level to a predetermined value.
[0007]
In this verification, for example, a voltage applied to a control gate (hereinafter, referred to as a memory gate) when a drain current of about 1 μA flows when a drain voltage of the memory cell is set to about 1 V is set as a threshold voltage, The verification is performed by detecting the threshold voltage (for example, see Patent Document 1). That is, the write / erase level is controlled by verifying the threshold voltage detection.
[0008]
FIG. 17 is a memory current characteristic diagram showing the concept of verification in a flash memory studied by the present inventors. In FIG. 17, the vertical axis indicates the memory current, and the horizontal axis indicates the memory gate voltage, and indicates the I (current) -V (voltage) characteristic of the memory cell.
[0009]
The IV characteristics in the figure indicate that the threshold voltage of the flash memory cell is of two types, "low level" and "high level", and that the threshold voltage of the flash memory cell is between the initial state and after the data is rewritten (for example, about 10,000 times). Respectively.
[0010]
As shown in the figure, the memory gate voltage at the time of reading is the voltage Vr, and the readable memory current is the current Irl or more at the time of the low level and the current Irl or less at the time of the high level.
[0011]
Since the verify operation of the flash memory is performed by threshold voltage management, the memory gate voltage is low when the memory gate voltage is Vvl, the memory gate voltage is high when the memory gate voltage is high, and the verify determination current is low level and high level both at the time of low level and high level. The current Iv. That is, the verify determination current is different from the memory current required for reading.
[0012]
Further, when the temperature differs between writing, erasing, and reading, there is a device that performs temperature dependence on the memory gate voltage at the time of verification in order to prevent erroneous reading due to a change in threshold voltage distribution (for example, , Patent Document 2).
[0013]
[Patent Document 1]
JP-A-62-99996
[0014]
[Patent Document 2]
JP-A-8-339693
[0015]
[Problems to be solved by the invention]
However, the present inventor has found that the verifying technique using the semiconductor integrated circuit device has the following problems.
[0016]
That is, as in the memory cell after data rewriting shown in FIG. 17, when the IV characteristics are degraded (the saturation current of the memory is reduced, the threshold voltage is increased), at the time of reading data, the memory is at a low level. Since the current is equal to or less than the current Irl and is equal to or greater than the current Irh at the high level, the reading cannot be performed.
[0017]
That is, when the memory cell characteristics are degraded due to data rewriting, the threshold voltage has reached a predetermined value in the verification performed by detecting the threshold voltage, but the memory current required for reading must always be secured. Erroneous reading may occur.
[0018]
An object of the present invention is to provide a nonvolatile semiconductor memory device and a semiconductor integrated circuit device capable of improving the rewriting durability of a nonvolatile memory cell and significantly improving the reliability of data reading.
[0019]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0020]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
(1) A nonvolatile semiconductor memory device according to the present invention includes a sense amplifier unit that generates a determination current of two current levels for determining a threshold voltage of a nonvolatile memory cell at the time of verification.
[0021]
An outline of another invention of the present application will be briefly described.
[0022]
The determination current of one level generated by the sense amplifier is about the same as the memory current in the nonvolatile memory which can determine that the current has flowed during the read operation, and the determination current of the other level generated by the sense amplifier is: It is about the same as the memory current in the nonvolatile memory from which it can be determined that no current flows during the read operation.
[0023]
The non-volatile semiconductor memory device may be a temperature compensating circuit that changes the two levels of determination currents depending on the temperature, or a verify power supply that changes the memory gate voltage of the non-volatile memory cell depending on the temperature at the time of verification. It has a generating circuit.
(2) It has a nonvolatile storage unit and a central processing unit, and the central processing unit can execute predetermined processing and issue an operation instruction to the nonvolatile storage unit. A semiconductor integrated circuit device having a plurality of nonvolatile memory cells for storing information, wherein two levels of determination currents for determining a threshold voltage of the nonvolatile memory cells at the time of verification are stored in the nonvolatile storage unit. It has a sense amplifier section for generating.
(3) In a nonvolatile memory having a nitride film having a plurality of local charge trapping regions in an insulating region as a charge storage layer and capable of writing / erasing data for rewriting, a threshold voltage during a writing operation is reduced. This performs a verify operation for detection.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0025]
FIG. 1 is a block diagram of a flash memory according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a verify sense amplifier circuit provided in the flash memory of FIG. 1, and FIG. 3 is a memory cell showing the concept of verify. 4, FIG. 4 is a current characteristic diagram of a memory cell showing a problem at the time of verification in FIG. 3, FIG. 5 is a current characteristic diagram of a memory cell when a temperature gradient is provided in a verify determination current, FIG. 6 is a current characteristic diagram of a memory cell showing another example in which a temperature gradient is provided in a verify determination current, and FIG. 7 is a memory cell voltage when a temperature gradient is provided in a memory gate voltage at the time of verification. FIG. 8 is a current characteristic diagram of a memory cell showing another example when a temperature gradient is provided to a memory gate voltage at the time of verification, and FIG. 9 is a memory cell diagram provided in the flash memory of FIG. 10 is a circuit diagram showing another configuration example of a verify sense amplifier circuit (sense amplifier section) provided in the flash memory of FIG. 1, and FIG. FIG. 12 is an explanatory diagram showing an example for providing a gradient, FIG. 12 is a circuit diagram showing an example of a circuit configuration of the temperature compensation circuit in FIG. 11, and FIG. 13 is a circuit of a voltage generating circuit for providing a temperature gradient to a memory gate voltage FIG. 14 is a circuit diagram showing an example of a configuration, FIG. 14 is a block diagram of a single-chip microcomputer with a built-in flash memory according to an embodiment of the present invention, and FIG. 15 is another configuration of a memory cell according to an embodiment of the present invention. FIG. 16 is an explanatory diagram showing an example, and FIG. 16 is an explanatory diagram of a write / erase operation in the memory cell of FIG.
[0026]
In this embodiment, as shown in FIG. 1, a flash memory (nonvolatile semiconductor memory device) 1 includes a control circuit 2, an input / output circuit 3, an address buffer 4, a row decoder 5, a column decoder 6, a verify sense amplifier circuit. 7, a high-speed read sense amplifier circuit 8, a write latch 9, a flash memory array 10, a power supply circuit 11, and the like.
[0027]
The control circuit 2 temporarily stores a control signal input from a host such as a microcomputer to be connected, and controls operation logic. Various signals such as data read from the flash memory array 10 and program data are input / output to the input / output circuit 3. The address buffer 4 temporarily stores an externally input address.
[0028]
A row decoder 5 and a column decoder 6 are connected to the address buffer 4, respectively. The row decoder 5 performs decoding based on the column (row) address output from the address buffer 4, and the column decoder 6 performs decoding based on the row (column) address output from the address buffer 4.
[0029]
The verify sense amplifier circuit 7 is a sense amplifier for erase / write verification, and the high-speed read sense amplifier circuit 8 is a read sense amplifier used at the time of data reading. The write latch 9 latches the write data input via the input / output circuit 3.
[0030]
In the flash memory array 10, memory cells, which are the minimum units of storage, are regularly arranged in an array. The memory cells provided in the flash memory array 10 are electrically rewritable and do not require a power supply for storing data.
[0031]
The power supply circuit 11 includes a voltage generation circuit that generates various voltages used for data writing, erasing, verifying, and the like.
[0032]
The circuit configuration of the verify sense amplifier circuit 7 will be described with reference to FIG.
[0033]
The verify sense amplifier circuit 7 includes an amplifier 12, a comparator 13, transistors M1 to M3, and the like. The transistor M1 is an N-channel MOS, and the transistors M2 and M3 are P-channel MOSs.
[0034]
The output of the amplifier 12 is connected to the gate of the transistor M2, and the positive input terminal (+) and one connection of the transistor M1 are connected to the gate and drain of the transistor M3, respectively.
[0035]
The negative input terminals (-) of the amplifier 12 and the comparator 13 are connected so that an input voltage vin, which is a certain reference voltage, is input thereto. The power supply circuit 11 is generated at the gate of the transistor M1. Are connected such that the gate voltage vgi is input.
[0036]
The transistor M1 is a MOS transistor serving as a current source, and the amplifier 12 controls the gate of the transistor M2, that is, the potential of the node N2 in the figure, so that the potential of the node N1 in the figure is equal to the input voltage Vin.
[0037]
The power supply voltage is connected to one connection of the transistor M3, the positive input terminal of the comparator 13 is connected to the other connection of the transistor M3, and the bit line yd < The memory cells (non-volatile memory cells) S provided in the flash memory array 10 are connected via m>. Then, the output unit of the comparator 13 outputs a comparison result signal outv <m>.
[0038]
As described above, the comparator 13 compares the current flowing through the transistors M1 and M3 constituting the current mirror circuit with the current flowing through the memory cell S, thereby verifying the memory cell S.
[0039]
Note that the verify sense amplifier unit 7 described above is not limited to the use of the verify, and may be used for reading. In that case, the high-speed read sense amplifier 8 need not be provided in the flash memory 1.
[0040]
Next, the operation of the flash memory 1 according to the present embodiment will be described.
[0041]
First, write, erase, and read operations in the flash memory 1 will be described with reference to FIG.
[0042]
First, the write operation will be described below.
[0043]
When an address is input to the address buffer 4, the row decoder 5 and the column decoder 6 select at least one memory cell S from the flash memory array 10.
[0044]
When data is input to the input / output circuit 3, the data is stored in the write latch 9 and connected to the memory cell S to be written. Thereafter, the current of the memory cell S is reduced by applying a high-voltage write pulse generated by the power supply circuit 11 to the selected memory cell S.
[0045]
In the erase operation, when an address is input to the address buffer 4, the row decoder 5 and the column decoder 6 select a plurality of memory cells S from the flash memory array 10. Then, the current of the memory cell S is increased by applying the erase pulse generated by the power supply circuit 11 to the selected memory cell S.
[0046]
Further, in the read operation, when an address is input to the address buffer 4, the row decoder 5 and the column decoder 6 select at least one memory cell S from the flash memory array 10.
[0047]
The magnitude of the current value of the selected memory cell S is detected by the verify sense amplifier circuit 7 and the high-speed read sense amplifier circuit 8, and the result is output via the input / output circuit 3.
[0048]
Here, the current characteristics of the memory cell representing the concept of the verify in the present invention will be described with reference to FIGS.
[0049]
3 to 8, for example, when the threshold voltage is a low level, an erasing operation is performed, and when the threshold voltage is a high level, a data writing is performed. However, these are not particularly limited. The reverse is also possible.
[0050]
In FIG. 3, the vertical axis represents the memory current and the horizontal axis represents the memory gate voltage, and shows the IV characteristics of the memory cell S. The left curve in the figure shows the IV characteristics when the threshold voltage of the memory cell S is low level, and the right curve shows the IV characteristics when the threshold voltage of the memory cell S is high level. Also, at each threshold voltage, the IV characteristics of the memory cell S in the initial state and after rewriting (for example, about 10,000 times) are shown.
[0051]
Further, the memory gate voltage is shown as a memory gate voltage Vr at the time of reading, a memory gate voltage Vvl at the time of verifying when the threshold voltage is low level, and a memory gate voltage Vvh at the time of verifying when the threshold voltage is high level. I have.
[0052]
The memory current required for reading is the memory current Irl when the threshold voltage is low level, and is shown as the memory current Irh when the threshold voltage is high level.
[0053]
The verifying determination current is the determining current Ivl when the threshold voltage is low level, and is shown as the determining current Ivh when the threshold voltage is high level.
[0054]
According to the present invention, the verifying current is set to be approximately the same as the memory currents Irl and Irh required for reading (determination current Ivl ≒ memory current Irl, determining current Ivh ≒ memory current Irh, where memory current Irl ≦ determination). Current Ivl, memory current Irh ≧ determination current Ivh).
[0055]
That is, when the threshold voltage is low level, the determination current Ivl is used to secure the memory current Irl at the time of reading. When the threshold voltage is at a high level, the determination current Ivh is used to secure the memory current Irh at the time of reading.
[0056]
The relationship between the memory gate voltage Vr at the time of reading and the memory gate voltages Vvl and Vvh at the time of verification is set so that memory gate voltage Vvl ≦ memory gate voltage Vr ≦ memory gate voltage Vvh in order to ensure read reliability.
[0057]
Here, FIG. 4 shows a problem that can occur when the verify method studied by the present inventor to make the verify determination current approximately the same as the memory currents Irl and Irh necessary for reading is adopted.
[0058]
In FIG. 4, the vertical axis is the memory current, and the horizontal axis is the memory gate voltage, showing the IV characteristics of the memory cell. The curve on the left side in the figure shows the IV characteristics when the threshold voltage of the memory cell is low level, and the curve on the right side shows the IV characteristics when the threshold voltage of the memory cell is high level. It is. Further, the left and right curves show the IV characteristics at the temperature Ta and the temperature Tb, respectively. Here, it is assumed that the temperature Ta <the temperature Tb.
[0059]
In FIG. 4, for example, when verification is performed at a temperature Ta and reading is performed at a temperature Tb (however, the memory gate voltage for reading uses the memory gate voltage Vr at all temperatures), the threshold voltage is low level. At this time, if the verification is performed with the memory gate voltage Vvl, the reading becomes impossible at the time of reading at the temperature Tb because the memory current becomes lower than the memory current Irl.
[0060]
Therefore, a technique for solving the problem shown in FIG. 4 by providing a temperature gradient to the verification determination current will be described with reference to FIG.
[0061]
Also in FIG. 5, the vertical axis is the memory current and the horizontal axis is the memory gate voltage, showing the IV characteristics of the memory cell. The curve on the left side in the figure shows the IV characteristics when the threshold voltage of the memory cell is low level, and the curve on the right side shows the IV characteristics when the threshold voltage of the memory cell is high level. It is. These left and right curves show IV characteristics at the temperature Ta and the temperature Tb, respectively.
[0062]
As shown in the figure, when the threshold voltage is low level, at the temperature Ta, the verifying is performed with the determining current as the determining current Ivlta, and at the temperature Tb, the verifying is performed using the determining current Ivltb.
[0063]
When the threshold voltage is high level, verification is performed by the determination current Ivhta at the temperature Ta, and verification is performed by the determination current Ivhtb at the temperature Tb.
[0064]
In FIG. 5, the memory gate voltages Vvl and Vvh at the time of verification are the same as the memory gate voltage Vr at the time of reading. However, as shown in FIG. 3, the memory gate voltages Vvl and Vvh at the time of verification and the memory gate voltage at the time of reading are shown. It may be different from Vr. However, these three voltages are set so that memory gate voltage Vvl ≦ memory gate voltage Vr ≦ memory gate voltage Vrh in order to ensure read reliability.
[0065]
FIG. 6 is a diagram showing another example of the IV characteristic depending on the temperature of the memory cell in the technique to be solved by providing a temperature gradient to the verify determination current shown in FIG. In FIG. 6, unlike the IV characteristic shown in FIG. 5, the IV characteristic crosses upward.
[0066]
In this case, when the threshold voltage is low level, at the temperature Ta, the verification is performed by the determination current Ivltb, and at the temperature Tb, the verification is performed by the determination current Ivltb. The determination current Ivltb has a large current value.
[0067]
When the threshold voltage is high level, verification is performed by the determination current Ivhta at the temperature Ta, and verification is performed by the determination current Ivhtb at the temperature Tb.
[0068]
FIG. 7 is a diagram showing memory current characteristics when the problem shown in FIG. 4 is solved by providing a temperature gradient to the memory gate voltage at the time of verification.
[0069]
Also in FIG. 7, the vertical axis represents the memory current, the horizontal axis represents the memory gate voltage, and the left curve in the figure represents the IV characteristics when the threshold voltage of the memory cell is low level, and the right curve. The curve of FIG. 14 shows the IV characteristic when the threshold voltage of the memory cell is at a high level. These left and right curves show IV characteristics at the temperature Ta and the temperature Tb, respectively.
[0070]
In this case, at the temperature Ta when the threshold voltage is at the low level, the verification is performed with the memory gate voltage being the memory gate voltage Vvlta, and at the temperature Tb, the verification is performed with the memory gate voltage being the memory gate voltage Vvltb.
[0071]
On the other hand, at the temperature Ta when the threshold voltage is at the high level, the memory gate voltage is set to the memory gate voltage Vvhta to perform the verification, and at the temperature Tb, the memory gate voltage is set to the memory gate voltage Vvhtb to perform the verification.
[0072]
FIG. 8 is a diagram showing another example of the IV characteristic depending on the temperature of the memory cell in the technique of providing a temperature gradient to the memory gate voltage at the time of verification shown in FIG. Also in FIG. 8, unlike the IV characteristics shown in FIG. 7, the IV characteristics intersect at the upper side.
[0073]
At the temperature Ta when the threshold voltage is at the low level, the verification is performed by the memory gate voltage Vvlta, and at the temperature Tb, the verification is performed by the memory gate voltage Vvltb.
[0074]
On the other hand, at the temperature Ta when the threshold voltage is at the high level, verification is performed by the memory gate voltage Vvhta, and at the temperature Tb, verification is performed by the memory gate voltage Vvhtb.
[0075]
In this case, as shown, the memory gate voltage Vvlta is higher than the memory gate voltage Vvltb.
[0076]
Next, the operation of the verify sense amplifier circuit 7 for performing the above-described verify will be described.
[0077]
First, write and erase operations in the memory cells S of the flash memory array 10 will be described.
[0078]
The memory cell S is, for example, of a one-transistor stack gate type having a two-layer polysilicon structure. As shown in FIG. 9, the memory cell S includes a diffusion layer including a source SC and a drain D, and a floating gate FG and a memory gate MG on a semiconductor substrate W between the source SC and the drain D via a gate oxide film. Are configured in a stacked structure.
[0079]
FIG. 9A is a diagram illustrating a write operation in the memory cell S.
[0080]
When, for example, about 10 V is applied to the memory gate MG, about 5 V is applied to the drain D, and about 0 V is applied to the source SC and the semiconductor substrate W, for example, a current flows between the drain D and the source SC to cause hot electron injection. As a result, charges are accumulated in the floating gate FG, and the current of the memory cell S decreases.
[0081]
FIG. 9B is a diagram illustrating an erasing operation of the memory cell S.
[0082]
When, for example, about -10 V is applied to the memory gate MG, and about -10 V is applied to the source SC and the semiconductor substrate W, and the drain D is opened, the electrons accumulated in the floating gate FG are emitted to the semiconductor substrate W. , The current of the memory cell S increases.
[0083]
When the memory cell S is read in the verify sense amplifier circuit 7 of FIG. 2, the potential of the bit line yd <m> (FIG. 2) depends on the magnitude relationship between the current flowing through the transistor M3 as the determination current and the current flowing through the memory cell S. Is determined, and the comparator 13 detects the potential, and outputs the detected signal outv <m> to verify whether the current value of the memory cell S has a desired value.
[0084]
Under the boundary condition where the signal outv <m> output from the comparator 13 transitions from the Lo level to the Hi level, the gate voltage of the transistor M2 and the gate voltage of the transistor M3 are the same, so that the current flowing through the transistor M1 = the transistor M2 The relationship of current flowing through the transistor M3 = current flowing through the transistor M3 = current flowing through the memory cell S holds.
[0085]
Therefore, the current value of the transistor M3 is determined by the current value of the transistor M1. Therefore, by varying the gate voltage vgi applied to the gate of the transistor M1, the value of the current flowing through the transistor M1 can be set to the above-described determination currents Ivl and Ivh.
[0086]
Instead of adjusting the value of the current flowing through the current source transistor (M1) by the gate voltage vgi, for example, two current source transistors may be prepared, and each may be switched depending on the mode. This is the same even when there are two or more determination currents.
[0087]
FIG. 10 is a circuit diagram showing another configuration example of the verify sense amplifier circuit 7. As shown in FIG.
[0088]
In the verify sense amplifier circuit 7 of FIG. 10, current mirror circuits 15 and 16, switching transistors M4 and M5, and a transistor M6 are newly added to the circuit configuration shown in FIG.
[0089]
The current mirror circuit 15 includes P-channel MOS transistors M11 and M12 and N-channel MOS transistors M10, M13 and M14.
[0090]
The current mirror circuit 16 includes P-channel MOS transistors M21 and M22 and N-channel MOS transistors M20, M23 and M24.
[0091]
The transistors M10 and M20 are connected so that a gate voltage vgi is applied thereto. The transistor M10 and the transistor M20 are transistors for a current source having substantially the same transistor size, and a reference current flows according to the gate voltage Vgi. Then, from the reference current, verify determination currents Ivl and Ivh are generated by a current mirror.
[0092]
That is, the current ratio between the current mirror circuits 15 and 16 (the transistor size ratio between the transistor M11 and the transistor M12, the transistor size ratio between the transistor M21 and the transistor M22) is determined by the output current (transistor M13, M1, And the current values flowing through the transistors M23 and M6) are set to the determination currents Ivl and Ivh.
[0093]
These determination currents Ivl and Ivh are respectively switched by transistors M4 and M5 based on control signals sel0 and sel1 output from control circuit 2 (FIG. 1), for example.
[0094]
With this configuration, it is only necessary to adjust one reference current value instead of the two determination currents Ivl and Ivh, and the adjustment time of the determination current can be reduced.
[0095]
Although an example of the circuit configuration of the verify sense amplifier circuit is shown in FIGS. 2 and 10, the circuit configuration of the verify sense amplifier circuit is not limited to this.
[0096]
FIG. 11 is a diagram illustrating an example for providing a temperature gradient to the determination current. The illustrated temperature compensation circuit 20 is a circuit that outputs a temperature-dependent voltage. This temperature compensation circuit 20 is provided, for example, in the power supply circuit 11 (FIG. 1) and is connected to the verify sense amplifier circuit 7 (FIGS. 2 and 10).
[0097]
When a voltage vg including a certain reference voltage is input to the input unit of the temperature compensation circuit 20, a voltage vgi having a temperature gradient is output from the output unit.
[0098]
By inputting the voltage vgi generated by the temperature compensation circuit 20 to the verify sense amplifier circuit 7, the current flowing through the current source transistor, that is, the determination currents Ivlta, Ivltb, Ivhta, and Ivhtb depend on the temperature. .
[0099]
Further, the temperature compensation circuit 20 may be provided in the verify sense amplifier circuit 7.
[0100]
FIG. 12 is a diagram showing an example of a circuit configuration of the temperature compensation circuit 20 of FIG.
[0101]
The temperature compensation circuit 20 includes transistors M30 to M34. The transistors M30, M31 and M34 are formed of N-channel MOS, and the transistors M32 and M33 are formed of P-channel MOS.
[0102]
A power supply voltage is connected to one connection of the transistors M32 and M33, and one connection of the transistor M30 is connected to the other connection of the transistor M32.
[0103]
The other connection portion of the transistor M33 is connected to one connection portion and the gate of the transistor M31. One connection of the transistor M34 is connected to the other connection of the transistors M30 and M31, and a reference potential is connected to the other connection of the transistor M34.
[0104]
The gate of the transistor M33 is connected to the gate of the transistor M32 and the other connection portion. The gate of the transistor M30 is connected so that the voltage Vg is input, and the gate of the transistor M31 outputs the gate voltage Vgi.
[0105]
In the temperature compensation circuit 20 having such a configuration, by controlling the input side transistor M30 and the output side transistor M31 so that the same current flows in the subthreshold region, the output potential is α (ΔT) log (transistor A temperature gradient of (channel width of M30 / channel width of transistor M31) can be provided. Here, ΔT: a temperature range in which dependency is provided.
[0106]
FIG. 13 is a diagram showing an example of a circuit configuration of the voltage generation circuit 30 for providing a temperature gradient to the voltage (memory gate voltage) applied to the word line x <n>. The voltage generation circuit 30 for providing a temperature gradient to the memory gate voltage is provided, for example, in the power supply circuit 11 (FIG. 1) and outputs an output voltage vout.
[0107]
A certain word line x <n> is selected by a row decoder 5 (FIG. 1) according to an address. The selection state in FIG. 13 is a state in which the P-channel MOS transistor of the CMOS inverter constituting the driver drv of the row decoder 5 is conducting, and the voltage value of the word line x <n> at this time is the power supply of the driver drv. , That is, the output voltage vout.
[0108]
The voltage generation circuit 30 includes a charge pump 31, a temperature compensation circuit 33, a comparator 34, a ladder resistor 35, and the like.
[0109]
The input of the temperature compensation circuit 33 is connected so as to receive the reference voltage vref1 generated by the power supply circuit 11, and the output of the temperature compensation circuit 33 is connected to the negative input terminal of the comparator 34. ing.
[0110]
The input of the charge pump 31 is connected to the output of the comparator 34, and a ladder resistor 35 is connected between the output of the charge pump 31 and the reference potential. The positive input terminal of the comparator 34 is connected to an intermediate tap which is an output part of the divided voltage of the ladder resistor 35.
[0111]
A switching circuit 32 is connected to an output section of the charge pump 31. The switching circuit 32 switches output of voltages output from a plurality of voltage generating circuits such as the voltage generating circuit 30 or the voltage generating circuit 40 based on a control signal output from the control circuit 2 (FIG. 1). .
[0112]
The voltage generation circuit 40 and the like generate, for example, a voltage at the time of data writing, a voltage at the time of data erasing, and the like. Examples of the internal circuit configuration include a charge pump 41, a temperature compensation circuit 43, a comparator 44, and a ladder resistor 45. The configuration is the same as that of the voltage generation circuit 30, and the description is omitted. Further, in the voltage generation circuit 40, the temperature compensation circuit 43 may be omitted. Further, the voltage generation circuit 30 and the voltage generation circuit 40 are not limited to the charge pump, and may be any circuits that generate a voltage such as a step-down power supply circuit.
[0113]
In the voltage generation circuit 30, the voltage boosted by the charge pump 31 is divided by a ladder resistor 35 and input to a positive input terminal of a comparator 34. On the other hand, the reference voltage vref1 is converted into a reference voltage having a temperature gradient by the temperature compensation circuit 33, and is input to the negative input terminal of the comparator. Here, the temperature compensation circuit 33 has, for example, the same circuit configuration as the temperature compensation circuit 20 shown in FIG.
[0114]
The comparator 34 compares the voltage divided by the ladder resistor 35 with the reference voltage having a temperature gradient output from the temperature compensating circuit 33, and controls ON / OFF of the charge pump 31 according to the comparison result. , Output voltage vout. Thus, a temperature gradient can be provided to the output voltage vout of the charge pump 31.
[0115]
The voltage generating circuit for providing a temperature gradient to the memory gate voltage is not limited to this. For example, the voltage generating circuit 30 may be connected to the P-channel MOS transistor of the driver drv, or the two voltage generating circuits 30 May be provided and connected to the P-channel MOS transistor and the N-channel MOS transistor of the driver drv, respectively.
[0116]
FIG. 14 is a block diagram of a single-chip microcomputer (semiconductor integrated circuit device) MC with a built-in flash memory, which is an example of the semiconductor integrated circuit device according to the present invention.
[0117]
The microcomputer MC is a system LSI having on-chip a flash memory (non-volatile storage unit) 1a having the same configuration as the flash memory 1 (FIG. 1), and a CPU (central information processing unit) 50 , CPG 51, DMAC 52, timer 53, SCI 54, ROM 55, BSC 56, RAM 57, input / output ports IOP1 to IOP9, and the like.
[0118]
The CPU (Central Processing Unit) controls all the controls of the microcomputer MC based on a program or the like stored in the ROM 55.
[0119]
A ROM (Read Only Memory) 55 stores programs to be executed by the CPU 50, fixed data, and the like. A RAM (Random Access Memory) 57 stores a calculation result by the CPU 50 and provides a work area of the CPU 50.
[0120]
A DMAC (Direct Memory Access Controller) 52 controls the transfer of data between the ROM 56 and the RAM 57 and the externally connected main memory in predetermined block units.
[0121]
An SCI (Serial Communication Interface) 54 performs serial communication with an external device. The timer 53 counts a set time, and sets a flag or generates an interrupt request when the set time is reached.
[0122]
A CPG (Clock Pulse Generator) 51 generates a clock signal of a certain frequency and supplies a system clock as an operation clock. The input / output ports IOP1 to IOP9 are input / output terminals for externally connecting the macro computer.
[0123]
In the microcomputer MC, the CPU 50, the flash memory 1, the ROM 55, the RAM 57, the DMAC 52, and some of the input / output ports IOP1 to IOP5 are interconnected by a main address bus IAB and a main data bus IDB.
[0124]
Further, peripheral circuits such as the timer 53 and the SCI 54 and the input / output ports IOP1 to IOP9 are interconnected by a peripheral address bus PAB and a peripheral data bus PDB.
[0125]
The BSC 56 controls signal transfer between the main address bus IAB, the main data bus IDB and the peripheral address bus PAB, and the peripheral data bus PDB, and controls the state of each bus.
[0126]
Further, in the present embodiment, the case where memory cell S (FIG. 9) is of a stack gate type has been described. However, the memory cell is not limited to this. For example, an EEPROM (Electrically) as shown in FIG. A memory cell (non-volatile memory cell) S1 or the like used for an Erasable Programmable ROM or the like may be used.
[0127]
As shown, the memory cell S1 has a structure in which one memory cell is constituted by two transistors, that is, a selection MOS transistor and a charge storage MOS transistor.
[0128]
A bit line yd <m> is connected to the memory cell S1, a word line xc <n> is connected to one gate (control gate) of the memory cell S1, and the other gate (memory gate). Is connected to a word line x <n>.
[0129]
In the memory cell S1, a control gate voltage is applied to the control gate via the word line xc <n>, and a memory gate voltage is applied to the memory gate via the word line x <n>.
[0130]
In the memory cell S1, as shown in FIG. 16, a diffusion layer including a source SC and a drain D is formed. On the semiconductor substrate W between the source SC and the drain D, a charge storage layer DC and a memory gate MG are formed in a stacked structure via a gate oxide film, and a control gate CG is formed on the adjacent side. It has a two-transistor configuration.
[0131]
FIG. 16A is a diagram showing a write operation in the memory cell S1.
[0132]
In the memory cell S1, a nitride film having a plurality of local charge trapping regions in the insulating region is used as the charge storage layer DC.
[0133]
When, for example, about 8 V is applied to the memory gate MG, about 1.5 V to the control gate CG, about 5 V to the source SC, about 0 V to the drain D, and about 0 V to the semiconductor substrate W, the drain D-source SC The hot electrons generated by the current flowing therebetween cause the electrons to be stored in the charge storage layer DC by the source side injection, and the current of the memory cell S1 decreases.
[0134]
FIG. 16B is a diagram showing an erasing operation of the memory cell S1.
[0135]
When, for example, about 10 V is applied to the memory gate MG, about 1.5 V is applied to the control gate CG, and about 0 V is applied to the source SC, the drain D, and the semiconductor substrate W, for example, the charge is accumulated in the charge storage layer DC. Electrons are emitted to the memory gate MG, and the current of the memory cell S1 increases.
[0136]
Also in this memory cell S1, the memory gate voltage at the time of verification with a temperature gradient is applied to memory gate MG. The application of the memory gate voltage having the temperature gradient is not particularly limited, and the memory gate voltage may be applied to the control gate CG.
[0137]
Thus, according to the present embodiment, at the time of reading data from the flash memory 1, the memory current required for reading is secured in the verify operation, so that even if the memory cell S has deteriorated due to data rewriting, the data reading is not performed. Reliability can be improved.
[0138]
Further, even in a memory cell having a nitride film having a plurality of local charge trapping regions in an insulating region as a charge storage layer, a change in threshold voltage is obtained by performing a verify operation in each of a write operation and an erase operation. It is possible to determine whether or not the writing has been completed, and it is no longer necessary to continuously apply the write voltage / erase voltage even though the change in the threshold voltage of the memory cell has been completed. The operation can be speeded up, stress due to the voltage being continuously applied to the charge storage region of the memory cell can be reduced, and power consumption can be reduced.
[0139]
When a write operation / erase operation is performed on a plurality of memory cells in parallel, a verify operation is performed to reduce a potential difference between a source and a drain for a memory cell whose threshold voltage has been completely changed. Power consumption can be reduced by preventing a memory cell current from flowing.
[0140]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.
[0141]
For example, in the above embodiment, the case where the memory cell of the flash memory is a stack gate type in which the memory cell is formed by one transistor and two transistors is described, but the configuration of the memory cell is not limited to this. Instead, any configuration may be used as long as it is a nonvolatile memory.
[0142]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed by the present application will be briefly described as follows.
[0143]
(1) By ensuring a readable memory current in the verify operation, the reliability of data reading can be improved, and the number of times of data rewriting can be greatly improved.
[0144]
(2) According to the above (1), the reliability of the nonvolatile semiconductor memory device and the semiconductor integrated circuit device using the same can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram of a flash memory according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a verify sense amplifier circuit provided in the flash memory of FIG. 1;
FIG. 3 is a current characteristic diagram of a memory cell showing the concept of verification.
FIG. 4 is a current characteristic diagram of a memory cell showing a problem at the time of verification in FIG. 3;
FIG. 5 is a current characteristic diagram of a memory cell in a case where a temperature gradient is provided for a verify determination current.
FIG. 6 is a current characteristic diagram of a memory cell showing another example in the case where a temperature gradient is provided to a verification determination current.
FIG. 7 is a current characteristic diagram of a memory cell when a temperature gradient is provided to a memory gate voltage during verification.
FIG. 8 is a current characteristic diagram of a memory cell showing another example when a temperature gradient is provided to a memory gate voltage at the time of verification.
FIG. 9 is an explanatory diagram of a write / erase operation in a memory cell provided in the flash memory of FIG. 1;
FIG. 10 is a circuit diagram showing another configuration example of the verify sense amplifier circuit provided in the flash memory of FIG. 1;
FIG. 11 is an explanatory diagram showing an example for providing a temperature gradient to a determination current.
FIG. 12 is a circuit diagram showing an example of a circuit configuration of the temperature compensation circuit of FIG.
FIG. 13 is a circuit diagram showing an example of a circuit configuration of a voltage generation circuit for providing a temperature gradient to a memory gate voltage.
FIG. 14 is a block diagram of a single-chip microcomputer with a built-in flash memory according to an embodiment of the present invention.
FIG. 15 is an explanatory diagram showing another configuration example of the memory cell according to the embodiment of the present invention;
16 is an explanatory diagram of a write / erase operation in the memory cell of FIG.
FIG. 17 is a memory current characteristic diagram showing the concept of verification in a flash memory studied by the present inventors.
[Explanation of symbols]
1 Flash memory (non-volatile semiconductor storage device)
1a Flash memory (non-volatile storage unit)
2 Control circuit
3 I / O circuit
4 Address buffer
5 row decoder
6 column decoder
7. Verify sense amplifier circuit
8 High-speed read sense amplifier circuit
9 Write latch
10 Flash memory array
11 Power supply circuit
12 amplifier
13 Comparator
15, 16 Current mirror circuit
20 Temperature compensation circuit
30 Voltage generation circuit
31 charge pump
32 Switching circuit
33 Temperature compensation circuit
34 Comparator
35 Ladder resistance
40 Voltage generation circuit
41 Charge pump
43 Temperature compensation circuit
44 Comparator
45 Ladder resistance
M1-M3 transistor
S, S1 memory cell (non-volatile memory cell)
Vr Memory gate voltage
Vvl Memory gate voltage
Vvh memory gate voltage
Irl memory current
Irh memory current
Iv judgment current
Ivl judgment current
Ivh judgment current
Ivlta judgment current
Ivltb Judgment current
Ivhta determination current
Ivhtb Judgment current
Vvlta memory gate voltage
Vvltb Memory gate voltage
Vvhta memory gate voltage
Vvhtb Memory gate voltage
SC source
D drain
DC charge storage layer
W semiconductor substrate
MG memory gate
FG floating gate
CG control gate
Ta, Tb temperature
N1, N2 nodes
vg, vgi voltage
Vin input voltage
sel0, sel1 control signal
vref1, vref2 reference voltage
yd <m> bit line
X <n>, xc <n> Word line
drv driver
vout output voltage
M4-M6 transistor
M10-M14 transistor
M20-M24 transistor
M30-M34 transistor
MC microcomputer (semiconductor integrated circuit device)
50 CPU (Central Information Processing Unit)
51 CPG
52 DMAC
53 timer
54 SCI
55 ROM
56 BSC
57 RAM
IOP1 to IOP9 I / O ports
IAB main address bus
IDB main data bus
PAB peripheral address bus
PDB peripheral data bus
CK clock line

Claims (18)

At the time of verification, a sense amplifier unit that generates a determination current for determining a threshold voltage of the nonvolatile memory cell is provided,
The nonvolatile semiconductor memory device according to claim 1, wherein the determination current generated by the sense amplifier unit has two current levels. The nonvolatile semiconductor memory device according to claim 1,
The determination current of one level generated by the sense amplifier is about the same as the memory current in the nonvolatile memory cell that can determine that the current has flowed during the read operation, and the determination of the other level generated by the sense amplifier is performed. The nonvolatile semiconductor memory device according to claim 1, wherein a current is substantially equal to a memory current in said nonvolatile memory which can determine that no current flows during a read operation. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said sense amplifier unit includes a temperature compensation circuit for changing each of said two levels of determination current depending on a temperature. Storage device. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising: a verifying power supply generating circuit for changing a memory gate voltage of said nonvolatile memory cell depending on a temperature at the time of verifying. Storage device. A non-volatile storage unit, including a central processing unit, the central processing unit executes a predetermined process, it is possible to give an operation instruction to the non-volatile storage unit, the non-volatile storage unit, A semiconductor integrated circuit device having a plurality of nonvolatile memory cells for storing information,
2. The semiconductor integrated circuit device according to claim 1, wherein the nonvolatile storage unit includes a sense amplifier unit that generates a two-level determination current for determining a threshold voltage of the nonvolatile memory cell at the time of verification. The semiconductor integrated circuit device according to claim 5,
The determination current of one level generated by the sense amplifier is about the same as the memory current in the nonvolatile memory cell that can determine that the current has flowed during the read operation, and the determination of the other level generated by the sense amplifier is performed. A semiconductor integrated circuit device, wherein a current is approximately the same as a memory current in the nonvolatile memory from which a current does not flow during a read operation. 7. The semiconductor integrated circuit device according to claim 5, wherein the sense amplifier unit includes a temperature compensation circuit that changes each of the two levels of the determination current depending on a temperature. . 7. The semiconductor integrated circuit device according to claim 5, wherein the non-volatile storage unit includes a verifying power supply generating circuit that changes a memory gate voltage of the non-volatile memory cell depending on a temperature at the time of verification. A semiconductor integrated circuit device characterized by the following. One memory cell is constituted by two transistors, a selection MOS transistor and a charge storage MOS transistor,
The selection MOS transistor and the charge storage MOS transistor are configured on a common channel region;
A first diffusion region on the select MOS transistor side;
In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells each having a structure having a second diffusion region on the charge storage MOS transistor side,
The charge storage MOS transistor has a nitride film having a plurality of trap regions as a charge storage region,
A nonvolatile semiconductor memory device, wherein a write verify operation is performed when writing to the nonvolatile memory cell. 10. The nonvolatile semiconductor memory device according to claim 9, wherein write operations to a plurality of said nonvolatile memory cells are performed in parallel, and said nonvolatile memory cell which has detected write completion by said write verify operation is said nonvolatile memory. A nonvolatile semiconductor memory device in which writing to a cell is not performed. The nonvolatile semiconductor memory device according to claim 10,
Writing to the nonvolatile memory cell is performed by applying a write voltage to a gate electrode of the charge storage MOS transistor and trapping hot electrons generated by a current flowing through the channel region into the charge storage region,
Non-volatile semiconductor memory, wherein current is not allowed to flow through the channel region to a memory cell that has detected completion of writing by the write verify operation, thereby preventing writing to the memory cell. apparatus. 12. The nonvolatile semiconductor memory device according to claim 11, wherein a current is prevented from flowing through said channel region by reducing a potential difference between said first diffusion region and said second diffusion region. Semiconductor memory device. 13. The nonvolatile semiconductor memory device according to claim 12, wherein an erasing operation for erasing information stored in a plurality of predetermined memory cells is possible, and whether the information stored in the memory cells is erased in the erasing operation. A non-volatile semiconductor memory device, which performs an erase verify operation for determining whether or not a non-volatile semiconductor memory device is used. A nonvolatile storage unit, and a central processing unit;
The central processing unit can execute a predetermined process and issue an operation instruction to the nonvolatile storage unit,
The nonvolatile storage unit forms one memory cell with two transistors, a selection MOS transistor and a charge storage MOS transistor,
The selection MOS transistor and the charge storage MOS transistor are configured on a common channel region;
A first diffusion region on the select MOS transistor side;
In a semiconductor integrated circuit device having a plurality of nonvolatile memory cells each having a structure having a second diffusion region on the charge storage MOS transistor side,
The charge storage MOS transistor has a nitride film having a plurality of trap regions as a charge storage region,
A semiconductor integrated circuit device, wherein a write verify operation is performed when writing to the memory cell. 15. The semiconductor integrated circuit device according to claim 14, wherein a write operation to a plurality of said memory cells is performed in parallel, and a write operation to said memory cell is performed for a memory cell which has detected write completion by said write verify operation. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 15,
Writing to the memory cell is performed by applying a writing voltage to a gate electrode of the charge storage MOS transistor and trapping hot electrons generated by a current flowing through the channel region into the charge storage region,
A semiconductor integrated circuit device wherein writing to the memory cell is prevented from being performed by preventing current from flowing through the channel region to a memory cell which has detected completion of writing by the write verify operation. . 17. The semiconductor integrated circuit device according to claim 16, wherein a current is prevented from flowing through the channel region by reducing a potential difference between the first diffusion region and the second diffusion region. Circuit device. 18. The semiconductor integrated circuit device according to claim 17, wherein an erase operation for erasing information stored in a predetermined plurality of memory cells is possible, and whether or not information stored in the memory cells is erased in the erase operation. A semiconductor integrated circuit device, which performs an erase verify operation for judging whether or not the semiconductor integrated circuit is in a state.

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