JP2011118982A - Flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a temperature compensation circuit of a flash memory which stores a plurality of threshold voltages in non-volatile memory cells, and reads the threshold voltages using a plurality of word line select level voltages applied to word lines. <P>SOLUTION: A power supply circuit which generates a reference voltage is provided. A plurality of voltage generation circuits which generate a plurality of word line select level voltages include a comparator, a charge pump circuit, and a voltage division circuit including a plurality of diffused resistors connected in series. The reference voltage is connected to the negative-side input terminal of the comparator. The output terminal of the comparator is connected to the input terminal of the charge pump circuit. An output voltage boosted by the charge pump is connected to the word line and the voltage division circuit. A divided voltage drawn out from the voltage division circuit is connected to the positive-side input terminal of the comparator. Voltage change rates with temperature (temperature gradients) of the divided voltages of the plurality of voltage generation circuits are made equal to each other. The power supply circuit generates the reference voltage having the temperature gradient. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a flash memory in which a change in voltage of a voltage generation circuit due to temperature is compensated.

  Conventionally, an electrically rewritable flash memory is known. A flash memory is a non-volatile memory that has a conductive floating gate as a charge storage layer and can be electrically rewritten by injecting or extracting charges from the floating gate, and performs writing / erasing to rewrite data. . In the flash memory, since the floating gate is conductive, the threshold voltage of the nonvolatile memory cell can be widely changed.

  For this reason, as disclosed in Patent Document 1, a flash memory in which a plurality of threshold voltages are stored in a nonvolatile memory cell and the threshold voltages are read using a plurality of word line selection level voltages has been developed and used.

JP 2004-164700 A

  However, in the flash memory, in order to eliminate the temperature change of the plurality of word line selection level voltages, the use of the plurality of temperature compensation circuits installed for each word line selection level voltage makes the circuit complicated and reduces the manufacturing cost of the flash memory. There was a problem of raising it.

  An object of the present invention is to simplify the temperature compensation circuit for the word line selection level voltage of the flash memory and to reduce the manufacturing cost of the flash memory.

  In order to solve the above problems, the present invention provides a flash memory that stores a plurality of threshold voltages in a nonvolatile memory cell and reads the threshold voltages using a plurality of word line selection level voltages applied to word lines. A plurality of voltage generation circuits having a power supply circuit for generating a reference voltage and generating a plurality of word line selection level voltages, wherein a comparator, a charge pump circuit, and a plurality of diffusion resistance elements are connected in series. A voltage circuit, the reference voltage is connected to the negative input terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the charge pump circuit, and the output voltage boosted by the charge pump is A word line is connected to the voltage dividing circuit, a divided voltage drawn from the voltage dividing circuit is connected to a positive side input terminal of the comparator, and a temperature of the divided voltage of the plurality of voltage generating circuits is determined. Equal voltage change rate (temperature gradient), a flash memory, wherein the power supply circuit generates said reference voltage having the temperature gradient.

  The flash memory of the present invention adjusts the ratio of the divided voltages corresponding to the plurality of word line selection level voltages so that the divided voltage temperature gradients are equalized by the plurality of voltage generation circuits, and has a common temperature gradient. By supplying the reference voltage from the power supply circuit to the input terminal of the comparator of the voltage generation circuit, there is an effect that the temperature compensation circuit can be simplified, and thereby the manufacturing cost of the flash memory can be reduced.

1 is a block diagram of a flash memory according to an embodiment of the present invention. It is a circuit diagram showing an example of a circuit configuration of a voltage generation circuit for generating a word line selection level voltage of the present invention. It is a cross-sectional schematic diagram which shows an example of a structure of the non-volatile memory cell of this invention. It is a circuit diagram which shows one non-volatile memory cell and peripheral circuit of this invention. It is a cross-sectional schematic diagram of a non-volatile memory cell.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a flash memory 1 according to an embodiment of the present invention, FIG. 2 is a diagram showing a circuit configuration for generating a plurality of word line selection level voltages VDDH applied to a word line WL, and FIG. 4 is a cross-sectional view of a nonvolatile memory cell 11 used in the flash memory 1, FIG. 4 is a circuit diagram of one nonvolatile memory cell 11 and peripheral circuits in the flash memory array 10, and FIG. 5 is a voltage dividing resistor used in the voltage generation circuit. It is a cross-sectional schematic diagram of the diffused resistive element which comprises.

  In the present embodiment, the flash memory 1 (nonvolatile semiconductor memory device) includes a control circuit 2, an input / output circuit 3, an address buffer 4, a row decoder 5, a column decoder 6, a high-speed read sense amplifier, as shown in FIG. The circuit 7 includes a write latch 8, a power supply circuit 9, and a flash memory array 10.

  The control circuit 2 temporarily stores a control signal input from a host such as a connected microcomputer, and controls the operation logic. Various signals such as data read from the flash memory array 10 and program data are input to and output from the input / output circuit 3. The address buffer 4 temporarily stores an address input from the outside.

  In the flash memory array 10, nonvolatile memory cells 11, which are the minimum storage unit, are regularly arranged in an array. The nonvolatile memory cell 11 provided in the flash memory array 10 can electrically rewrite data, and a power source is not required for storing data.

  FIG. 3 shows a cross-sectional structure of the nonvolatile memory cell 11 used in the flash memory 1. In the nonvolatile memory cell 11, as shown in the figure, diffusion layers are formed on the semiconductor region (well region) 100 in the source electrode 108 and drain electrode 109 portions. A channel region is formed between the two electrodes, the non-volatile memory cell 11 is formed by two transistors that are configured as the selection MOS transistor Ta near the source electrode 108 and the charge storage MOS transistor Tm near the drain electrode 109. It has a two-transistor configuration.

  The selection MOS transistor Ta has an assist gate 106 via a gate oxide film 104 on the channel region. The charge storage MOS transistor Tm has a stacked structure having a floating gate 107 via a gate oxide film 101 on a channel region and a memory gate electrode 103 serving as a control gate via a gate oxide film 102 thereon.

FIG. 4 illustrates one nonvolatile memory cell 11 of the flash memory array 10 and its peripheral circuit. The nonvolatile memory cells 11 are arranged in a matrix. The assist gate 106 of the nonvolatile memory cell 11 is switch-controlled by a control signal AG. The word line WL for each row of the flash memory array 10 is connected to the memory gate electrode 103 of the nonvolatile memory cell 11, and the voltage generation circuit 20 is connected to the word line WL. Data lines DL 1 and DL 2 for each column of the flash memory array 10 are connected to two nodes of the source electrode 108 and the drain electrode 109 of the nonvolatile memory cell 11.

  Source selection MOS transistors TS0 and TS1 of the nonvolatile memory cell 11 are provided at one end of the data lines DL1 and DL2, and drain selection MOS transistors TD1 and TD0 of the nonvolatile memory cell 11 are provided at the other end of the data lines DL1 and DL2. Is provided. The MOS transistors TS0 and TS1 individually connect the source electrode 108 on the side of the selection MOS transistor Ta of the nonvolatile memory cell 11 to the corresponding bit line BL, and the MOS transistors TD0 and TD1 are charge storage MOS transistors of the nonvolatile memory cell 11. The drain electrode 109 on the Tm side is commonly connected to the common data line CDL. That is, by the control signals SS0, SS1, SD0, and SD1, the source electrode 108 is connected to the bit line BL and the drain electrode 109 is connected to the common mode data line CDL in the write operation, and the source electrode 108 is connected in the read operation. An operation is performed to connect the drain electrode 109 to the bit line BL by connecting to the common mode data line CDL.

  Data stored in the nonvolatile memory cell 11 utilizes the fact that the threshold voltage of the nonvolatile memory cell 11 changes according to the amount of charge stored in the floating gate 107. At this time, the threshold voltage of the nonvolatile memory cell 11 is limited to a desired range according to the value of the stored data. For example, one non-volatile memory cell 11 stores information of 2 bits, and four types of memory threshold voltages corresponding to “01, 00, 10, 11” data stored are determined. That is, the information storage state of one nonvolatile memory cell 11 includes the erase state (“11”) as the fourth threshold voltage state, the first write state (“10”) as the first threshold voltage state, and the second The second write state (“00”) as the threshold voltage state and the third write state (“01”) as the third threshold voltage state are selected. A total of four information storage states are determined by 2-bit data. In order to set the memory threshold voltage, the write voltage applied to the word line WL during the write operation after erasure is set to three kinds of voltages, and these three kinds of voltages are sequentially switched and divided into three times. Perform a write operation.

Next, write, erase, and read operations in the flash memory 1 according to the present embodiment will be described with reference to FIG.
(Erase operation)
In the erase operation for the nonvolatile memory cell 11, when an address is input to the address buffer 4, the row decoder 5 and the column decoder 6 select a plurality of nonvolatile memory cells 11 from the flash memory array 10. Thereafter, a voltage of −16 V for erasing generated by the power supply circuit 9 is applied to the word line WL and connected to the memory gate electrode 103 of the nonvolatile memory cell 11. 2 V is applied to the assist gate 106. The storage data in the nonvolatile memory cell 11 is erased by applying 0 V to the source electrode 108, the drain electrode 109, and the well region 100, and discharging electrons from the floating gate 107 to the well region 100 through the FN tunnel.

(Write operation)
In the write operation, when an address is input to the address buffer 4, the row decoder 5 and the column decoder 6 select at least one nonvolatile memory cell 11 from the flash memory array 10. A bit line BL is connected to the source electrode 108 of the nonvolatile memory cell 11, and 0 V is applied to the bit line BL when writing is selected and 0.8 V is applied when writing is not selected. A common data line CDL to which 5 V is applied is connected to the drain electrode 109 of the nonvolatile memory cell 11, and a write selection voltage, for example, 15 V is applied to the word line WL and connected to the memory gate electrode 103. At this time, the selection level of the control signal AG applied to the assist gate 106 is set to a voltage lower than 0.8V of the voltage applied to the source electrode 108 in the case of non-write selection, for example, 0.6V. Accordingly, in the write selection memory cell, the selection MOS transistor Ta is turned on, and a drain current flows. As a result, hot electrons are generated at the boundary between the selection MOS transistor Ta and the charge storage MOS transistor Tm. Data is written in the nonvolatile memory cell 11 by being injected and causing a change in the threshold voltage of the nonvolatile memory cell 11. In the unselected memory cell for writing, since the selection MOS transistor Ta remains in the off state, hot electrons are not generated and writing is prevented.

  The threshold voltages of the three types of nonvolatile memory cells 11 are controlled by controlling the time of such a high voltage state and further by controlling the level of the high voltage applied to the word line WL.

(Read operation)
Further, in the read operation, when an address is input to the address buffer 4, the word line WL is selected by the row decoder 5, and the voltage is set to the word line selection level voltage VDDH of the voltage generation circuit 20. Then, the data stored in the nonvolatile memory cell 11 selected from the flash memory array 10 is read by the row decoder 5 and the column decoder 6. At that time, three types of word line selection level voltages VDDH to be applied to the word lines WL are set, and the three types of word line selection level voltages VDDH are sequentially applied to the memory gate electrode 103 via the word lines WL, The read operation of the stored data is performed up to three times, and the 2-bit stored data is determined based on the binary (1 bit) value read from the nonvolatile memory cell 11 in each read operation.

  In the read operation of the nonvolatile memory cell 11 sharing the selected word line WL, the drain electrode 109 of the nonvolatile memory cell 11 is connected to the bit line BL and the source electrode 108 is connected to the common data line CDL by a control signal of a selection level. Connect to. Then, a read word line selection level voltage VDDH, for example, 1.5 V to 3.5 V is applied to the word line WL connected to the memory gate electrode 103, and 0 V is applied to the source electrode 108 of the nonvolatile memory cell 11. The common data line CDL is connected, and the drain electrode 109 is connected to the bit line BL precharged to 0.8V. At this time, if the word line selection level voltage VDDH is higher than the threshold voltage of the nonvolatile memory cell 11, a drain current flows, and a change in the drain current is detected by the high-speed read sense amplifier circuit 7 provided in the bit line BL. Thus, the stored data written in the nonvolatile memory cell 11 is read.

(Voltage generation circuit)
FIG. 2 is a diagram showing a circuit of voltage generation circuits 20 and 30 that generate a plurality of word line selection level voltages VDDH to be applied to the word lines WL. A voltage generation circuit 20 that generates one word line selection level voltage VDDH is composed of a charge pump 21, a comparator 24, and a voltage dividing circuit 25 including a diffusion resistance element array. The same applies to the voltage generation circuit 30 that generates another word line selection level voltage VDDH. The outputs of the plurality of voltage generation circuits 20, 30 and the like are switched by the switching circuit 22 based on a control signal output from the control circuit 2 (FIG. 1) and connected to the word line WL.

The power supply circuit 9 outputs reference voltages Vref1 and Vref2 having a temperature gradient and connects them to the negative input terminals of the comparator 24 of the voltage generation circuit 20 and the comparator 34 of the voltage generation circuit 30. The output part of the comparator 24 is connected to the input part of the charge pump 21, and the word line selection level voltage VDDH is generated from the output part of the charge pump 21, and the voltage dividing circuit 25 configured by a diffused resistor array. Connect to the output voltage terminal. The zero level connection terminal of the voltage dividing circuit 25 is connected to the zero level reference potential. FIG. 5 shows a schematic cross-sectional view of the diffusion resistance element 12 constituting the voltage dividing circuit 25. An intermediate terminal 23 for outputting a _divided voltage V _ref is provided between the voltage dividing circuits 25, and the intermediate terminal 23 is connected to the positive side input terminal of the comparator 24.

Thus, in the voltage generation circuit 20, the divided voltage V _ref obtained by dividing the word line selection level voltage VDDH boosted by the charge pump 21 by the voltage dividing circuit 25 is input to the positive side input terminal of the comparator 24. The reference voltage Vref1 is input to the negative side input terminal of the comparator 24.

The comparator 24 compares the divided voltage V _ref divided by the voltage dividing circuit 25 with the reference voltage Vref1, and performs ON / OFF control of the charge pump 21 according to the comparison result, whereby the divided voltage V _A word line selection level voltage VDDH is generated where _ref is equal to the reference voltage Vref1.

(Voltage dividing circuit)
As shown in FIG. 5, the diffusion resistance element 12 constituting the voltage dividing circuit 25 forms an N-well on a P-type semiconductor substrate P-SUB, forms a P-well therein, and the inside of the P-well. N-type diffusion is performed to form a resistance element. Since the diffusion resistance element 12 is formed by performing N-type diffusion in the P-type epitaxial layer, a parasitic diode exists between the resistance itself (N-type) and the epitaxial layer (P-type). . For this reason, the parasitic diode is normally prevented from operating by connecting the epitaxial layer to a potential higher than the voltage applied to the diffusion resistance element 12 and applying a reverse bias voltage to the voltage dividing circuit 25.

The resistance value of the diffusion resistance element 12 changes depending on the reverse bias voltage applied thereto. The resistance value of the _kth diffusion resistance element 12 in the voltage dividing circuit 25 is represented by R _k , the reverse bias voltage on the zero level reference potential side is represented by V _k, and the reverse bias voltage on the word line selection level voltage VDDH side is represented by V _k. When expressed as V _{k + 1} , the resistance value R _k of the k-th diffused resistance element 12 is expressed by the following Equation 1.
(Formula 1) _Rk = {( _Vk + _{Vk + 1} ) / 2} * a + b
Here, the coefficient a represents the rate of change of the resistance value of the diffusion resistance element 12 due to the reverse bias voltage, and the coefficient b represents the resistance value of the diffusion resistance element 12 when the reverse bias voltage is 0 volts. As for these coefficients a and b, for example, the coefficient b is 1700 Ω · μm × (channel width), and the coefficient a is (213 Ω · μm / (volt)) × (channel width). The coefficient (b / a) is about 8 volts. Here, the diffusion resistance element 12 usually has a positive temperature coefficient. For example, when the temperature rises from 25 ° C. to 85 ° C., the resistance value R _k of the diffusion resistance element 12 increases by about 15%.

It is assumed that the same current i flows through the voltage dividing circuit 25. Then, the voltage drop (V _{k + 1} −V _k ) generated in the k-th diffused resistance element 12 is expressed by the following formula 2.
(Equation _{2) V k + 1 -V k} = iR k
When V1 = 0 volt and calculation is performed from Equation 1 and Equation 2, the reverse bias voltage V _{k + 1} on the word line selection level voltage VDDH side of the kth diffusion resistance element 12 is expressed by Equation 3 below.
(Formula 3)
V _{k + 1} = (b / a) [− 1 + {(1 + i · a / 2) / (1-i · a / 2)} ^k ]

Here, it is assumed that the reverse bias voltage Vn + 1 on the side of the word line selection level voltage VDDH of the nth diffusion resistance element 12 is taken out from the intermediate terminal 23 as the _divided voltage _Vref . Then, the following Expression 4 in which V _ref is expressed by the current i is obtained.
(Formula 4)
V _ref = (b / a) [− 1 + {(1 + i · a / 2) / (1−i · a / 2)} ⁿ ]
If the voltage dividing circuit 25 has n + m number of diffusion resistance elements 12, the word line selection level voltage VDDH is expressed by the following equation (5).
(Formula 5) VDDH = (b / a) [-1 + {(1 + i.a / 2) / (1-i.a / 2)} ^{(n + m)} ]
When Expression 4 is substituted into Expression 5 and VDDH is expressed by the divided voltage V _ref , the following Expression 6 is obtained. (Expression 6) VDDH = (b / a) [− 1 + {(a / b) V _ref +1} ^{((n + m) / n)} ]
Conversely, when the divided voltage V _ref is expressed as VDDH, the following Expression 7 is obtained.
(Expression 7) V _ref = (b / a) [− 1 + {(a / b) VDDH + 1} ^{(n / (n + m))} ]
Based on Expression 6 or Expression 7, the number m + n of the diffusion resistance elements 12 constituting the voltage dividing circuit 25 for applying the divided voltage V _ref and VDDH, and between the intermediate terminal 23 for extracting the divided voltage and the zero level connection terminal The number n of the diffusion resistance elements 12 is obtained.

When the word line selection level voltage VDDH is kept constant, if the equation 7 is differentiated by (b / a), the divided voltage V _{ref with} respect to the minute change amount Δ (b / a) of (b / a) due to the minute temperature change. The following formula 8 representing the minute change amount Δ (V _ref ) of the above is obtained.
(Expression 8) Δ (V _ref ) / Δ (b / a)
= −1+ {1 + Q · m / (n + m)} / {(1 + Q) ^{(m / (n + m))} }
(Formula 9) Q≡VDDH · a / b

The value of Q is, for example, about 0.44 and less than 1 when VDDH is 3.5V. Therefore, from Expression 8, the following approximate expressions 10 and 11 (when Q is sufficiently smaller than 1) are obtained.
(Expression 10) Δ (V _ref ) / Δ (b / a) ≈ (1/2) (n · m / (m + n) ² ) · Q ²
(Formula 11) {Δ (V _ref ) / V _ref } / Δ (b / a)
≈ (1/2) (VDDH · m / (m + n)) · (a / b) ²
Here, Δ (b / a) represents the amount of change in (b / a) due to temperature and is generally within 0.2.

From the equations 8, 10, and 11, the change rate of the resistance value _Rk of the diffusion resistance element 12 is within 15%. In the case of a temperature change from 25 ° C. to 85 ° C., the change in Q is also to that extent. In this case, the value of the proportionality coefficient Δ (V _ref ) / Δ (b / a) hardly changes in the temperature range, and the voltage change Δ (V _ref ) is approximately Δ (b / a). The _divided voltage V _ref changes linearly with respect to the temperature change.

From Equation 11, Δ (V _ref ) / V _ref is different if the value of VDDH is different, and is different if the value of (m / (m + n)) is different. The power supply circuit 9 changes the reference voltages Vref1 and Vref2 of the voltage generation circuits 20 and 30 with the same temperature gradient as the divided voltage _Vref , so that the word line selection level voltage VDDH of each voltage generation circuit is constant. Can keep. However, when the voltage generation circuits 20 and 30 commonly set the _divided voltage V _ref and change the voltage dividing ratio to generate different VDDH, the change Δ (V _ref ) of the _divided voltage V _{ref due to} the temperature is: Different word line selection level voltages VDDH have different temperature gradients according to equations 8 and 10.

In order to improve this, the ratio of n and m is adjusted for each word line selection level voltage VDDH, and the voltage change rate (temperature gradient) Δ (V _ref ) / V _{ref due} to temperature is adjusted to the same value. That is, the reference voltages Vref1 and Vref2 having a voltage change rate (temperature gradient) due to a common temperature are used even if the voltage of the _divided voltage _Vref is different. By doing so, the power supply circuit 9 generates the temperature gradient of each reference voltage generated for the plurality of voltage generation circuits with a common value, so that the temperature compensation circuit of the flash memory can be simplified. . Thereby, the word line selection level voltage VDDH of each voltage generation circuit is stabilized and output at a constant value regardless of the temperature change, and the accuracy of the word line selection level voltage VDDH can be increased.

DESCRIPTION OF SYMBOLS 1 ... Flash memory 2 ... Control circuit 3 ... Input / output circuit 4 ... Address buffer 5 ... Row decoder 6 ... Column decoder 7 ... High-speed read sense amplifier circuit 8 ... Write latch 9 ... Power supply circuit 10 ... Flash memory array 11 ... Nonvolatile memory cell 12 ... Diffusion resistance elements 20, 30 ... Voltage generation circuits 21, 31 ... Charge pump 22 ... Switching circuits 23, 33 ... intermediate terminals 24, 34 ... comparators 25, 35 ... voltage dividing circuit 100 ... semiconductor region (well region)
101, 102, 104 ... gate oxide film 103 ... memory gate electrode 106 ... assist gate 107 ... floating gate 108 ... source electrode 109 ... drain electrodes AG, SS0, SS1, SD0, SD1 ... control signal BL ... bit line CDL ... common data lines DL1, DL2 ... data lines P-SUB ... P-type semiconductor substrate R _k , R _{k + 1} ... resistance value Ta ... Selection MOS transistor Tm: Charge storage MOS transistors TS0, TS1 ... Source selection MOS transistors TD0, TD1 ... Drain selection MOS transistors _Vref ... Divided voltages Vref1, Vref2 ... Reference voltage VDDH ... the word line selection level voltage _{V k, V k + 1,} V k + 2 ··· reverse bias voltage WL · Word line

Claims (1)

  A flash memory that stores a plurality of threshold voltages in a nonvolatile memory cell and reads the threshold voltages using a plurality of word line selection level voltages applied to a word line, and has a power supply circuit that generates a reference voltage, The plurality of voltage generation circuits for generating the plurality of word line selection level voltages are configured by a comparator, a charge pump circuit, and a voltage dividing circuit in which a plurality of diffusion resistance elements are connected in series, and the reference voltage is compared with the comparison voltage. Connected to the negative input terminal of the comparator, the output terminal of the comparator is connected to the input terminal of the charge pump circuit, the output voltage boosted by the charge pump is connected to the word line and the voltage dividing circuit, The divided voltage drawn from the voltage dividing circuit is connected to the positive side input terminal of the comparator, and the voltage change rate (temperature gradient) due to the temperature of the divided voltage of the plurality of voltage generating circuits is equalized. Flash memory, wherein a serial power source circuit for generating the reference voltage with the temperature gradient.

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