JPH08235886A - Nonvolatile semiconductor storage device and its rewriting method - Google Patents

Abstract

PURPOSE: To perform the rewriting of correct data electrically and to increase the number of rewritings by providing a program control circuit, a high voltage generating circuit and a readout circuit. CONSTITUTION: Data being equal to or more than ternary levels are mode to be stored in memory cells provided with charge accumulation layers like a floating gate type or an MNOS type EEPROM and a flash memory. In a data rewriting, stored data prior to the rewriting of the memory cells are read out by a readout circuit 6 and the read out data are compared with write data to be newly written by a program control circuit 8. The combination of voltages to be applied to sources, drains and control gates of memory cells is determined in accordance with the compared result to be applied from a high voltage generating circuit 7 to memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device and a method for rewriting the same, and more particularly to a multi-value level non-volatile semiconductor memory device in which one memory cell stores data of three or more values. And its rewriting method.

[0002]

EE capable of electrically rewriting and erasing
PROM (Electrically Erasable and Programmable R
In order to increase the storage capacity of a non-volatile semiconductor memory device such as a flash memory that can be erased electrically, a so-called multi-level data is stored in one memory cell. A level method has been proposed (Preliminary Proceedings of the 53rd JSAP Autumn Meeting, Autumn 1992, p.653).

[0003]

However, only the data storage method of such a multi-level level nonvolatile semiconductor memory device has been proposed in the above-mentioned lecture proceedings, and the method of rewriting the stored data will be described. Is not suggested.

Therefore, an object of the present invention is to provide a multilevel nonvolatile semiconductor memory device capable of rewriting data accurately and a rewriting method thereof.

Another object of the present invention is to provide a multi-level level non-volatile semiconductor memory device and a rewriting method thereof which can improve the number of times of rewriting.

[0006]

A nonvolatile semiconductor memory device of the present invention for solving the above-mentioned problems has a charge storage layer between a control gate and a semiconductor substrate, and stores charges in the charge storage layer. And a memory erased by the data erasing means, which is a nonvolatile semiconductor memory device including a memory cell for storing three-valued data or more, thereby erasing the data stored in the memory cell. Data rewriting means for storing the predetermined write data in the memory cell by accumulating an amount of charge corresponding to predetermined write data of three or more write data in the charge storage layer of the cell.

A nonvolatile semiconductor memory device according to another aspect of the present invention has a charge storage layer provided between a control gate and a semiconductor substrate, and a source and a drain formed in the semiconductor substrate. A non-volatile semiconductor memory device having a memory cell for storing three-valued data or more by accumulating charges in the charge accumulation layer, the detecting means detecting a storage state of the memory cell before data rewriting. And comparing means for comparing the storage state before the data rewriting detected by the detecting means with the storage state after the data rewriting to obtain a difference between the storage state before the data rewriting and the storage state after the data rewriting. And applying a predetermined voltage to the source, the drain, and the control gate of the memory cell according to the difference obtained by the comparison means. And a, and a data rewriting means for rewriting the memory state of the memory cell.

In one aspect of the present invention, the charge storage layer is an oxide film / nitride film interface.

In one aspect of the present invention, the data rewriting means includes a changing means for changing the application time of the voltage.

In one aspect of the present invention, the changing means changes an application time of a voltage applied to the control gate.

In one aspect of the present invention, the detection means includes means for measuring the amount of charges accumulated in the charge storage layer.

According to one aspect of the present invention, when three or more levels of data are arranged in a staircase pattern, the value of the voltage applied to the control gate electrode is the same in order to increase one step of the data step.

Further, the rewriting method of the nonvolatile semiconductor memory device of the present invention has a charge storage layer between the control gate and the semiconductor substrate, and by storing charges in the charge storage layer, data having three or more values is stored. A method for rewriting a non-volatile semiconductor memory device having a memory cell for storing a memory cell, comprising: erasing data stored in the memory cell, and writing three or more values to the charge storage layer of the erased memory cell. The predetermined write data is stored in the memory cell by accumulating a charge amount corresponding to predetermined write data of the data.

A method of rewriting a nonvolatile semiconductor memory device according to another aspect of the present invention is a charge storage layer provided between a control gate and a semiconductor substrate, and a source and a drain formed in the semiconductor substrate. A method of rewriting a non-volatile semiconductor memory device, comprising: a memory cell for storing three-valued data or more by accumulating charges in the charge accumulation layer, the method comprising: Comparing a storage state before data rewriting detected in the detecting step and a storage state after data rewriting detected in the detecting step with a storage state before the data rewriting and a storage state after the data rewriting And a difference between the source and the drain of the memory cell according to the difference obtained in the comparing step. Determining the emission and voltage respectively applied to the control gate, the source voltage determined here,
A rewriting step of rewriting the memory state of the memory cell by applying the voltage to the drain and the control gate, respectively.

In one aspect of the present invention, the charge storage layer is an oxide / nitride film interface.

In one aspect of the present invention, the rewriting step includes a changing step of changing the applied time of the determined voltage.

In one aspect of the present invention, the changing step changes an application time of the voltage applied to the control gate.

In one aspect of the present invention, the detecting step includes a measuring step of measuring the amount of charges accumulated in the charge accumulation layer.

According to one aspect of the present invention, when three or more levels of data are arranged in a stepwise manner, the value of the voltage applied to the control gate electrode is the same in order to raise one step of the data step.

A nonvolatile semiconductor memory device according to another aspect of the present invention has a charge storage layer provided between a control gate and a semiconductor substrate, and a source and a drain formed in the semiconductor substrate. A non-volatile semiconductor memory device having a memory cell for storing three or more values of data by accumulating charges in the charge accumulation layer, the data erasing means erasing the data stored in the memory cell. , The source, the drain and the control gate of the memory cell erased by the data erasing means,
A data rewriting unit that rewrites the storage state of the memory cell by applying a voltage corresponding to predetermined write data among write data of three or more values.

In one aspect of the present invention, the data rewriting means includes a changing means for changing the voltage application time.

In one aspect of the present invention, the changing means changes the application time of the voltage applied to the control gate.

A non-volatile semiconductor memory device according to another aspect of the present invention has a charge storage layer between a control gate and a semiconductor substrate, and charges are stored in the charge storage layer so that three or more values are stored. A non-volatile semiconductor memory device having a memory cell for storing data, comprising: a detection unit that detects a storage state of the memory cell before data rewriting; and a storage state before the data rewriting detected by the detection unit. Comparing means for obtaining a difference between the storage state before the data rewriting and the storage state after the data rewriting as compared with the storage state after the data rewriting; and the memory according to the difference obtained by the comparing means. Data rewriting means for rewriting the storage state of the memory cell by increasing or decreasing the amount of charge stored in the charge storage layer of the cell.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below according to preferred embodiments.

FIG. 1 is a block diagram showing the configuration of the main part of a floating gate type flash memory according to the first embodiment of the present invention.

As shown in the figure, the floating gate type flash memory of this embodiment includes a memory cell array 51, a column decoder 52, a row decoder 53, an address buffer 55, a read circuit 56, a program control circuit 58 and a high voltage generation circuit 57. .

The memory cell array 51 comprises memory cells 100 shown in FIG. 2 arranged in a matrix.
As shown in FIG. 2, in each memory cell 100, a drain 102 and a source 103 each made of an n-type impurity diffusion layer are formed in a surface region of a p-type silicon substrate 101, and a channel region 104 is formed between them. . Drain 1
A bit line 105 is connected to 02, and a source line 106 is connected to the source 103. A tunnel insulating film 107 made of a SiO ₂ film having a thickness of about 10 nm is formed on the channel region 104, and a floating gate 108 made of low resistance polysilicon, an interlayer insulating film 109 and low resistance polysilicon are formed on the tunnel insulating film 107. The control gate 110 is sequentially formed.

FIG. 3 shows a connection diagram of the memory cell 100 shown in FIG. In FIG. 3, reference numeral 111 indicates a word line, and other reference numerals correspond to those in FIG.

The high voltage generating circuit 57 shown in FIG. 1 generates voltages to be applied to the bit line 105, the source line 106 and the word line 111 of the memory cell 100 shown in FIG. The row decoder 53 receives the word line 1 of the memory cell array 51 in accordance with the address input from the address buffer 55.
11 is selected, and the voltage from the high voltage generation circuit 57 is applied to the selected word line 111. The column decoder 52 selects the bit line 105 of the memory cell array 51 according to the address input input via the address buffer 55,
The voltage from the high voltage generation circuit 57 is applied to the selected bit line 105. In addition, the source line 1 of each memory cell 100
A voltage is also applied to the 06 from the high voltage generation circuit 57.
The read circuit 56 reads the storage data of the selected memory cell 100 in the memory cell array 51 and outputs it to the outside in the read mode. Program control circuit 5
8 controls the high voltage generating circuit 57 in the rewriting mode to control the bit line 105 of the selected memory cell 100,
The voltages applied to the source line 106 and the word line 111 are generated. The high voltage generation circuit 57 generates the voltage described above under the control of the program control circuit 58, and the column decoder 52, the row decoder 53, and the memory cell array 5 are generated.
1 bit line 105 is supplied to each.

The row decoder 53 also grounds the selected word line 111 according to the output signal of the high voltage generating circuit 57. The column decoder 52 also selects the selected bit line 1 according to the output signal of the high voltage generation circuit 57.
May open 05. Further, the high voltage generation circuit 57
Also opens the source line 106 of each memory cell 100 under the control of the program control circuit 58.

Next, a method of writing four-value data of "00" to "11" in the memory cell 100 shown in FIG. 2 and a method of reading four-value data stored in the memory cell 100 will be described.

For example, data "1" is stored in the memory cell 100.
When writing 1 ”, a signal corresponding to the write data“ 11 ”is externally input to the program control circuit 58. The program control circuit 58 includes the high voltage generation circuit 57.
The bit line 105 to the ground to control the memory cell 1
00 source line 106 is opened, and a pulse voltage of about 10 to 15 V is applied to the control gate 110 of the memory cell 100 via the word line 111. As a result, a potential is induced in the floating gate 108 of the memory cell 100, and according to the potential difference between the floating gate 108 and the drain 102, the floating gate 108 is drained from the silicon substrate 101 near the drain 102 by Fowler-Nordheim (FN) tunneling. A predetermined amount of electric charge is injected into.
As a result, the threshold voltage of the memory cell 100 rises to, for example, about 7V, and the data “11” is stored in the memory cell 1
00 is written.

On the other hand, data "10" is stored in the memory cell 100.
When writing, the program control circuit 58 controls the high voltage generation circuit 57 to apply a voltage of 1 V to the bit line 105 of the memory cell 100, open the source line 106 of the memory cell 100, and Cell 10
0 to control gate 110 via word line 111
A pulse voltage of about 15V is applied. As a result, the threshold voltage of the memory cell 100 becomes, for example, 5 V, and the data “10” is written in the memory cell 100.

Data "01" is stored in the memory cell 100.
When writing, the program control circuit 58 controls the high voltage generation circuit 57 to apply a voltage of 2 V to the bit line 105 of the memory cell 100, open the source line 106 of the memory cell 100, and Cell 10
0 to control gate 110 via word line 111
A pulse voltage of about 15V is applied. As a result, the threshold voltage of the memory cell 100 becomes, for example, 3 V, and the data “01” is written in the memory cell 100.

Further, the data "00" is stored in the memory cell 100.
When writing, the program control circuit 58 controls the high voltage generation circuit 57 to apply a voltage of 3 V to the bit line 105 of the memory cell 100, open the source line 106 of the memory cell 100, and Cell 10
0 to control gate 110 via word line 111
A pulse voltage of about 15V is applied. As a result, the threshold voltage of the memory cell 100 becomes, for example, 1 V, and the data “00” is written in the memory cell 100.

When reading the data stored in the memory cell 100 as described above, the program control circuit 58 controls the high voltage generation circuit 57 to control the memory cell 1.
A voltage of 1V is applied to the bit line 105 of 00, the source line 106 of the memory cell 100 is grounded, and voltages of 2V, 4V, and 6V are sequentially applied to the control gate 110 of the memory cell 100 via the word line 111. . Then, when a voltage of 2V is applied to the control gate 110 and a current flows between the source 103 and the drain 102, the read circuit 56 determines that the threshold voltage of the memory cell 100 at this time is 1V. , "00" data is output. Further, when a voltage of 2V was applied to the control gate 110, no current flowed between the source 103 and the drain 102. However, when a voltage of 4V was applied to the control gate 110, a current flow occurred between the source 103 and the drain 102. , The read circuit 56 determines that the threshold voltage of the memory cell 100 at this time is 3V, and “0
1 "data is output. Furthermore, 2 is output to the control gate 110.
A current did not flow between the source 103 and the drain 102 when a voltage of V and 4 V was applied, but a current flowed between the source 103 and the drain 102 when a voltage of 6 V was applied to the control gate 110. In this case, the read circuit 56 determines that the threshold voltage of the memory cell 100 at this time is 5V and outputs "10" data. Furthermore, when no current flows between the source 103 and the drain 102 even when a voltage of 6 V is applied to the control gate 110, the read circuit 56 causes the memory cell 10 at this time to operate.
It is determined that the threshold voltage of 0 is 7V and the data of "11" is output.

Next, a method of erasing the data stored in the memory cell 100 will be described.

When erasing the data stored in the memory cell 100, the program control circuit 58 controls the high voltage generation circuit 57 to open the bit line 105 of the memory cell 100 and to open the bit line 105 of the memory cell 100. Source line 10
6 is applied with a high voltage (12 V) pulse voltage, and the control gate 110 of the memory cell 100 is connected to the word line 1
Ground via 11 As a result, the memory cell 10
The electric charges are extracted from the floating gate 108 of 0 by FN tunneling, and the memory cell 100 is set to the electrical erase level (the storage state of the data “00”), so that the data stored in the memory cell 100 is erased. .
This erase operation is completed in almost the same time regardless of which data storage state the memory cell 100 has.

The subsequent writing of the data "00" is performed by the above-mentioned erasing operation (the above-mentioned writing operation of the data "00" is usually performed from the ultraviolet erasing level at the time of product shipment or after the ultraviolet erasing. This is executed when setting the storage state of "00".).

Next, a method of rewriting the data stored in the memory cell 100 will be described with reference to the flowchart shown in FIG.

As an example, the case where the data "10" stored in the memory cell 100 is rewritten to the data "11" will be described. When the write data "11" is input to the program control circuit 58 (step S11). The program control circuit 58 temporarily erases the data “10” stored in the memory cell 100 by the above-described erase method (step S12). After that, the program control circuit 58 controls the high voltage generation circuit 57 to select the voltage combination corresponding to the write data “11” (step S13). That is, the bit line 105 is grounded, the source line 106 of the memory cell 100 is opened, and a pulse voltage of about 10 to 15 V is applied to the control gate 110 of the memory cell 100 via the word line 111. As a result, the data “11” is written in the memory cell 100 as described in the write operation (step S14).

As described above, in this embodiment, the data stored in the memory cell 100 can be rewritten by once erasing the data stored in the memory cell 100 and then writing the write data in the memory cell 100. Done. As an example, data stored in the memory cell 100 is changed from “10” → “11” → “01” → “00” → “11” →
FIG. 5 shows a sequence for rewriting in the order of “10”.

Although the above description is for the case of storing four-value (that is, two-bit) data in one memory cell, the data can be rewritten in the same manner even when four-value or more data is stored. It can be performed.

FIG. 6 is a block diagram showing the configuration of the main part of a floating gate type flash memory according to the second embodiment of the present invention.

As shown in the figure, the floating gate type flash memory of this embodiment has a memory cell array 1, a column decoder 2, a row decoder 3, an address buffer 5, a read circuit 6 (detection means), a program control circuit 8 and a high voltage generator. Including circuit 7.

The memory cell array 1 comprises the memory cells 100 shown in FIG. 2 arranged in a matrix. The high voltage generation circuit 57 generates voltages to be applied to the bit line 105, the source line 106 and the word line 111 of the memory cell 100 of FIG. The row decoder 53 selects the word line 111 of the memory cell array 51 according to the address input inputted via the address buffer 55, and applies the voltage from the high voltage generation circuit 57 to the selected word line 111. The column decoder 52 selects the bit line 105 of the memory cell array 51 according to the address input input via the address buffer 55, and selects the selected bit line 10
The voltage from the high voltage generating circuit 57 is applied to 5. Also,
A voltage is applied to the source line 106 of each memory cell 100 from the high voltage generation circuit 57.

The read circuit 6 reads the storage data of the selected memory cell 100 in the memory cell array 1, outputs the read storage data to the outside as a read output in the read mode, and reads the storage data in the rewrite mode. The data is supplied to the program control circuit 8.

In the rewrite mode, the program control circuit 8 compares the storage data supplied from the read circuit 6 with the write data supplied from the outside, and controls the high voltage generation circuit 7 according to the comparison result. The voltages applied to the bit line 105, the source line 106, and the word line 111 of the selected memory cell 100 are generated.

The high voltage generation circuit 7 generates the above-mentioned voltage under the control of the program control circuit 8 and supplies it to the column decoder 2, the row decoder 3 and the bit line 105 of the memory cell array 1, respectively.

The row decoder 3 includes a high voltage generation circuit 7
The selected word line 111 is also grounded in accordance with the output signal of. Further, the column decoder 2 also opens the selected bit line 105 according to the output signal of the high voltage generation circuit 7. Further, the high voltage generation circuit 7 may open the source line 106 of each memory cell 100 under the control of the program control circuit 8.

Next, the rewriting operation of the flash memory of this embodiment will be described with reference to the flowchart shown in FIG. Note that each memory cell 100 has "00"
It is assumed that 4-valued (2-bit) data of "11" is stored.

When the write data is externally input to the program control circuit 8 (step S1), the program control circuit 8 determines whether the write data is "00" (step S2). When the write data is "00", the erase operation of the data stored in the memory cell 100 is performed regardless of the content of the data stored in the memory cell 100 in which the data is rewritten ( Step S3). This erase operation is performed in the same manner as in the case of the above-described first embodiment. That is, the program control circuit 8 controls the high voltage generation circuit 7 to rewrite data.
The word line 111 (control gate 110) of 0 is grounded through the row decoder 3, the bit line 105 is opened through the column decoder 2, and a high voltage (12V) pulse is applied to the source line 106. As a result, charges are extracted from the floating gate 108 of the memory cell 100 in which data is rewritten by FN tunneling, and the memory cell 100 is brought to the electrical erase level (“00”).

If the write data is other than "00" in step S2, the read data is read by the read circuit 6 stored in the memory cell 100 for rewriting the data (step S4). The read storage data is sent from the read circuit 6 to the program control circuit 8 and then compared with the write data in the program control circuit 8 (step S5). As a result of this comparison, if the stored data and the write data are the same (that is,
If the memory state before and after rewriting of the memory cell 100 in which data is rewritten becomes the same), it is not necessary to perform the write operation, so the process ends (step S
6).

On the other hand, as a result of the comparison in step S5,
If the stored data and the written data are different (that is, the memory state before and after the rewriting of the memory cell 100 for rewriting the data is different), the program control circuit 8
Is based on the comparison result, the source (source line 106), drain (bit line 105) and control gate 110 (word line 1) of the memory cell 100 for rewriting data.
The combination of the voltages (including ground and open) to be applied to each of 11) is determined (step S7). This voltage combination is a combination of storage states before and after rewriting of the memory cell 100 that rewrites data "00" → "0".
1 ”,“ 00 ”→“ 10 ”,“ 00 ”→“ 11 ”,“ 0 ”
1 ”→“ 10 ”,“ 01 ”→“ 11 ”,“ 10 ”→“ 0 ”
There are 9 patterns corresponding to 1 ”,“ 10 ”→“ 11 ”,“ 11 ”→“ 01 ”and“ 11 ”→“ 10 ”.

Of these nine combinations of voltages,
When the write data becomes larger than the stored data, that is, the combination of the storage states before and after the rewriting of the memory cell 100 that rewrites the data is “00” → “01”,
“00” → “10”, “00” → “11”, “01” →
“10”, “01” → “11” and “10” → “11”
In the case of six types corresponding to the above, the amount of charges corresponding to each of these six types is injected into the floating gate 108 of the memory cell 100 in which data is rewritten, and the threshold voltage of the memory cell 100 is changed. A rewriting operation of increasing the amount by a predetermined amount is performed (step S8).

In this rewriting operation, the source line 106 of the memory cell 100 in which data is rewritten is opened by the high voltage generation circuit 7, and the voltage of 10 is applied to the word line 111 connected to the control gate 110 of the memory cell 100.
A pulse voltage having a pulse width of about 10 to 100 msec at about 15 V is applied by the high voltage generating circuit 7, and
The high voltage generating circuit 7 applies the voltage shown in the following [Table 1] to the bit line 105 connected to the drain 102 of the memory cell 100.

[0057]

[Table 1]

The voltage applied to the bit line 105 shown in [Table 1] is the difference between the amount of charge accumulated in the floating gate 108 before data rewriting and the amount of charge to be accumulated after data rewriting. Is the voltage determined from

As another example, in the rewriting operation described above, the source line 106 of the memory cell 100 for rewriting data is opened by the high voltage generating circuit 7 and connected to the drain 102 of the memory cell 100. A voltage of 0 V is applied to the bit line 105 by the high voltage generation circuit 7, and the word line 111 connected to the control gate 110 of the memory cell 100 has a voltage value shown in the following [Table 2] and a pulse width of 10 msec. The pulse voltage may be applied by the high voltage generating circuit 7.

[0060]

[Table 2]

Further, as another example, in the above-mentioned rewriting operation, the source line 106 of the memory cell 100 for rewriting data is opened by the high voltage generating circuit 7 and connected to the drain 102 of the memory cell 100. A voltage of 0V is applied to the bit line 105 by the high voltage generation circuit 7, and the word line 111 connected to the control gate 110 of the memory cell 100 has a voltage value of 12V and has a pulse width shown in Table 3 below. The pulse voltage may be applied by the high voltage generating circuit 7.

[0062]

[Table 3]

On the other hand, among the nine combinations described above, when the write data is smaller than the stored data, that is, the combination of the storage states before and after the rewriting of the memory cell 100 for rewriting the data “10” → “0”.
In the case of three types corresponding to 1 ”,“ 11 ”→“ 01 ”and“ 11 ”→“ 10 ”, the floating gate 108 of the memory cell 100 for rewriting data corresponds to each of these three types. A rewriting operation is performed in which a certain amount of charge is extracted and the threshold voltage of the memory cell 100 is lowered by a predetermined amount (step S8).

This rewriting operation is a modification of the erasing operation, and the bit line 105 connected to the drain 102 of the memory cell 100 for rewriting data is opened by the high voltage generating circuit 7 to control the memory cell 100. The voltage shown in the following [Table 4] is applied to the word line 111 connected to the gate 110 by the high voltage generation circuit 7, and the source line 106 of the memory cell 100 has a voltage value of 12 V and a pulse width of 100 msec. This is performed by applying a high voltage pulse by the high voltage generation circuit 7.

[0065]

[Table 4]

The program control circuit 8 selects a corresponding one from the combinations of 6 types + 3 types = 9 types of voltages described above and controls the high voltage generation circuit 7 to generate a required voltage. Then, using the voltage, the writing process of the memory cell as described above is performed. The data of the combination of the above 9 kinds of voltages is, for example, as a table,
It is stored in a relatively simple memory (not shown) such as a mask ROM formed in the same chip.

In FIG. 8, the same "10" as described with reference to FIG.
A sequence according to the present embodiment of rewriting “11” → “01” → “00” → “11” → “10” is shown. In the present embodiment, erasing to “00” is performed except when rewriting to “00”. Is not performed, the previous data is directly rewritten to the next data. Therefore, in the method shown in FIG. 5, the tunnel insulating film 10 of the memory cell 100 shown in FIG. 2 is used both when the previous data is erased to “00” and when the next data is written.
The current passes through the tunnel insulating film 107, and as a result, the amount of current passing through the tunnel insulating film 107 increases, whereas in the method of this embodiment, only the current required to rewrite the previous data to the next data is tunneled. It does not pass through the insulating film 107. Therefore, in the method of this embodiment, the deterioration of the tunnel insulating film 107 can be significantly reduced, and the number of times of rewriting can be significantly improved.

Although the present invention has been described above according to the preferred embodiments, the present invention is not limited to the above embodiments. For example, in each of the above-described embodiments, four-value (2-bit) data is stored in each memory cell,
The present invention can be applied to the case where three-valued data, five-valued data or more are stored in each memory cell.

Further, in each of the above-described embodiments, the case where the charge storage layer of each memory cell 100 is the floating gate 108 has been described. However, as shown in FIG. 9, the charge storage layers are the silicon oxide film 304 and the silicon nitride film. MN, which is the interface with the membrane 305
The present invention can be applied to a multilevel nonvolatile semiconductor memory device having the memory cell 300 of the OS structure. As shown in FIG. 9, the memory cell 30 having the MNOS structure is provided.
0 is a p-type silicon substrate 301 and a p-type silicon substrate 3
01 and n-type impurity diffusion layer 302 (source) and n-type impurity diffusion layer 303 (drain) respectively formed in the channel region 01 between the n-type impurity diffusion layer 302 and the n-type impurity diffusion layer 303. The silicon oxide film 304 formed on the surface of the p-type silicon substrate 301 and the silicon oxide film 3
04, and a control gate 306 formed on the silicon nitride film 305.

[0070]

According to the nonvolatile semiconductor memory device and the rewriting method thereof of the present invention, after erasing the data stored in the memory cell to be rewritten, the charge storage layer of the memory cell is written with three or more write data. By accumulating the charge amount according to the value, it is possible to accurately rewrite the data of three values or more.

Further, the memory state before rewriting of the memory cell to be rewritten is detected, the detected memory state before rewriting is compared with the memory state after rewriting, and the source and drain of the memory cell are based on the comparison result. Also, by determining the voltages to be applied to the control gates and rewriting the memory cells using these voltages, it becomes unnecessary to erase the stored data in the memory cells each time the rewriting is performed. As a result, the amount of current passing through the tunnel insulating film or the like can be suppressed to a necessary minimum and deterioration of the tunnel insulating film or the like can be suppressed, so that the number of times of rewriting can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a floating gate type flash memory according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a structure of a memory cell of the floating gate type flash memory according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram showing a wire connection state of memory cells of the floating gate type flash memory according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a data rewriting process procedure of the floating gate type flash memory according to the first embodiment of the present invention.

FIG. 5 is a graph showing an example of a data rewriting sequence of the floating gate type flash memory according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a floating gate type flash memory according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing a data rewrite processing procedure of the floating gate type flash memory according to the second embodiment of the present invention.

FIG. 8 is a graph showing an example of a data rewriting sequence of the floating gate type flash memory according to the second embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a memory cell having an MNOS structure.

[Explanation of symbols]

 1, 51 memory cell array 2, 52 column decoder 3, 53 row decoder 5, 55 address buffer 6, 56 read circuit 7, 57 high voltage generation circuit 8, 58 program control circuit 100 memory cell 101 p-type silicon substrate 102 drain 103 source 104 channel region 105 bit line 106 source line 107 tunnel insulating film 108 floating gate 109 interlayer insulating film 110 control gate 111 word line

Claims (18)

[Claims] 1. A non-volatile semiconductor memory device including a memory cell having a charge storage layer between a control gate and a semiconductor substrate and storing three or more values of data by storing charges in the charge storage layer. A data erasing means for erasing the data stored in the memory cell, and a predetermined writing of three or more write data to the charge storage layer of the memory cell erased by the data erasing means. A non-volatile semiconductor memory device comprising: a data rewriting unit that stores the predetermined write data in the memory cell by accumulating a charge amount corresponding to the data. 2. A charge storage layer provided between a control gate and a semiconductor substrate, and a source and a drain formed in the semiconductor substrate. By storing charges in the charge storage layer, A non-volatile semiconductor memory device comprising a memory cell for storing data of a value or more, the detecting means for detecting a storage state of the memory cell before data rewriting, and the data before rewriting the data detected by the detecting means. Comparing the memory state with the memory state after data rewriting to obtain a difference between the memory state before the data rewriting and the memory state after the data rewriting, and according to the difference obtained by the comparing means. , A data for rewriting the storage state of the memory cell by applying a predetermined voltage to the source, the drain and the control gate of the memory cell, respectively. A non-volatile semiconductor memory device having a data rewriting unit. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage layer is an oxide film nitride film interface. 4. The nonvolatile semiconductor memory device according to claim 2, wherein the data rewriting unit includes a changing unit that changes an application time of the voltage. 5. The nonvolatile semiconductor memory device according to claim 4, wherein the changing unit changes an application time of a voltage applied to the control gate. 6. The non-volatile semiconductor memory device according to claim 2, wherein the detection unit includes a unit that measures the amount of charge accumulated in the charge accumulation layer. 7. The value of the voltage applied to the control gate electrode in order to increase one step of the data step when arranging data of three or more values in a stepwise manner is the same. The non-volatile semiconductor memory device described in 1. 8. A non-volatile semiconductor memory device comprising a charge storage layer between a control gate and a semiconductor substrate, and a memory cell storing data of three or more values by storing charges in the charge storage layer. And erasing the data stored in the memory cell, wherein the charge storage layer of the erased memory cell has a charge amount corresponding to a predetermined write data of write data of three or more values. Is stored in the memory cell to store the predetermined write data in the non-volatile semiconductor memory device. 9. A charge storage layer provided between a control gate and a semiconductor substrate, and a source and a drain formed in the semiconductor substrate, wherein charge is stored in the charge storage layer. A method for rewriting a non-volatile semiconductor memory device comprising a memory cell storing data of a value or more, the detecting step of detecting a storage state of the memory cell before data rewriting, and the data detected in the detecting step. Comparing a memory state before rewriting with a memory state after rewriting data to obtain a difference between the memory state before the data rewriting and the memory state after the data rewriting, and the difference obtained in the comparing step. The voltages to be applied to the source, the drain and the control gate of the memory cell, respectively. A rewriting step of rewriting the memory state of the memory cell by applying a voltage to the source, the drain and the control gate, respectively. 10. The method for rewriting a nonvolatile semiconductor memory device according to claim 8, wherein the charge storage layer is an oxide film nitride film interface. 11. The method of rewriting a nonvolatile semiconductor memory device according to claim 9, wherein the rewriting step includes a changing step of changing the determined application time of the voltage. 12. The method of rewriting a nonvolatile semiconductor memory device according to claim 11, wherein the changing step changes an application time of the voltage applied to the control gate. 13. The method of rewriting a nonvolatile semiconductor memory device according to claim 9, wherein the detecting step includes a measuring step of measuring the amount of charges accumulated in the charge accumulation layer. 14. The value of the voltage applied to the control gate electrode is the same in order to raise one step of the data step when arranging data of three or more values in a stepwise manner. A method for rewriting the nonvolatile semiconductor memory device according to 1. 15. A charge storage layer provided between a control gate and a semiconductor substrate, and a source and a drain formed in the semiconductor substrate, wherein charge is stored in the charge storage layer. A non-volatile semiconductor memory device comprising a memory cell for storing data having a value or more, the data erasing means for erasing data stored in the memory cell, and the memory cell erased by the data erasing means A data rewriting unit that rewrites the storage state of the memory cell by applying a voltage corresponding to predetermined write data of three or more write data to the source, the drain, and the control gate, respectively. A characteristic non-volatile semiconductor memory device. 16. The nonvolatile semiconductor memory device according to claim 15, wherein the data rewriting unit includes a changing unit that changes an application time of the voltage. 17. The nonvolatile semiconductor memory device according to claim 16, wherein the changing unit changes an application time of a voltage applied to the control gate. 18. A non-volatile semiconductor memory device comprising a charge storage layer between a control gate and a semiconductor substrate, and a memory cell storing data of three or more values by storing charges in the charge storage layer. Comparing the storage state before the data rewriting detected by the detection means with the storage state before the data rewriting of the memory cell with the storage state after the data rewriting, Comparison means for obtaining a difference between the previous storage state and the storage state after the data rewriting, and to increase or decrease the amount of charge accumulated in the charge storage layer of the memory cell according to the difference obtained by the comparison means. Accordingly, the nonvolatile semiconductor memory device is provided with a data rewriting unit that rewrites the storage state of the memory cell.