CN110633544A - Modeling method for system-in-package module and electronic device - Google Patents
Modeling method for system-in-package module and electronic device Download PDFInfo
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Abstract
The application relates to the technical field of semiconductor reliability analysis and discloses a modeling method for a system-in-package module. Establishing a printed circuit board model according to the design of the printed circuit board; modeling the pins, the bonding pads and the solder according to the pin layout and the molding standard; the printed circuit board model is connected with other devices through pins and solder to form a board-level model. The method has the advantages that the printed circuit board model is established to provide a fixed connection foundation for other parts, the pins, the welding pads and the welding flux are modeled, and the printed circuit board model is connected with other devices through the pins and the welding flux, so that the detail degree of the model is improved, and the problem of low local reliability analysis precision caused by over-simplified modeling of the system-in-package module in the prior art can be solved. The application also discloses an electronic device for the system-in-package module.
Description
Technical Field
The present disclosure relates to the field of semiconductor reliability analysis technologies, and in particular, to a modeling method for a system-in-package module and an electronic device.
Background
System In Package (SiP) technology is an integrated Package form that mixes components with different functions into the same Package through different technologies, and thus provides System level or subsystem level functions.
With the rapid development of technologies such as aerospace electronics and military electronics, semiconductor devices, which are key cores of modern information technologies, are required to be miniaturized, lightweight, and highly densified to the maximum extent and to satisfy high reliability.
High reliability is the guarantee that the semiconductor device operates stably and plays a role, so reliability analysis is an important link in the design stage of the semiconductor device. Numerical simulation is a main means of reliability analysis, a three-dimensional model of a device is used as a research object of numerical simulation, and the accuracy and fineness of the device are the premise that a simulation result is reliable or not. Meanwhile, if the internal structure of the device is to be studied, compared with an expensive real object which needs a test means, a Computer-Aided Design (CAD) three-dimensional model has low cost, and is convenient and visual. Therefore, in the process of developing semiconductor devices, it is necessary and very important to establish a three-dimensional detailed model.
The existing modeling method generally omits many details, and in order to reduce the complexity of the model, each structure is generally processed approximately. Therefore, the reliability analysis result can only qualitatively reflect the overall stress distribution, weak links and failure tendency of the device, but the quantitative analysis result of local stress has larger error with the actual result, and even the purpose of qualitative analysis can not be achieved if the model is too simplified. This is undoubtedly disadvantageous for high reliability analysis of semiconductor devices, and even results in a large amount of manpower and material resources in practical application of the devices.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. The foregoing summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended to be a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a modeling method for a system-in-package module, which improves the detail of a model by increasing the modeling of a detail part so as to solve the problem of low local reliability analysis precision caused by over-simplified modeling of the system-in-package module in the prior art.
In some embodiments, a modeling method for a system-in-package module includes: establishing a printed circuit board model according to the design of the printed circuit board; modeling the pins, the bonding pads and the solder according to the pin layout and the molding standard; the printed circuit board model is connected with other devices through pins and solder to form a board-level model.
The modeling method for the system-in-package module provided by the embodiment of the disclosure can achieve the following technical effects:
the method has the advantages that the printed circuit board model is established to provide a fixed connection foundation for other parts, the pins, the welding pads and the welding flux are modeled, and the printed circuit board model is connected with other devices through the pins and the welding flux, so that the detail degree of the model is improved, and the problem of low local reliability analysis precision caused by over-simplified modeling of the system-in-package module in the prior art can be solved.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
fig. 1 is a flow chart diagram of a modeling method for a system-in-package module provided by an embodiment of the present disclosure;
FIG. 2 is a pin and solder material physical model diagram of a metallographic section of a device provided by an embodiment of the disclosure;
FIG. 3 is a simplified model diagram of a device provided by an embodiment of the present disclosure;
FIG. 4 is a detailed block diagram of a device provided by an embodiment of the present disclosure;
FIG. 5 is a board level model provided by embodiments of the present disclosure;
fig. 6 is a SiP module provided by an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a bonding region provided by an embodiment of the present disclosure;
fig. 8 is a bonding wire lead profile provided by embodiments of the present disclosure;
FIG. 9 is a bonding model provided by an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of an electronic device for system-in-package module modeling according to an embodiment of the present disclosure.
Reference numerals:
21: a physical pin; 22 physical solder; 23 physical pads; 31: simplifying the model pins; 32 simplifying the model solder; 33: simplifying the model pad; 41: a detailed model pin; 42: a detailed model solder; 43: a detailed model pad; 51: a pin; 52: a PCB; 53: a SiP module; 61: a chip and conductive adhesive; 62: reinforcing ribs; 63: an alloy cover plate and a solder ring; 64: kovar ring; 65: parallel seam welding cover plates/step cover plates; 66: a bonding region; 71: a bonding finger; 72: copper coating; 73: a via hole; 74: a first bond site; 75: a second bond site; 76: a first bonding wire; 77: a chip PAD; 78: a second bonding wire; 91: a first bonding point ball-shaped welding spot; 92: a second bonding point wedge-shaped welding spot; 100: a processor; 101: a memory; 103: a bus; 102: a communication interface.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
Printed Circuit Boards (PCBs) are important electronic components, support electronic components, and carriers for electrical connection of electronic components.
The reliability analysis platform software Ansys Workbench integrates a modeling platform, a single physical field analysis platform and a multi-physical field coupling analysis platform, is reliability analysis software which is most used in the industry, and compared with the method of importing the Ansys Workbench for analysis after modeling through CAD software such as Pro/Engineer and the like, the method for directly establishing the three-dimensional model by using the Ansys Workbench can avoid the incompatibility problem caused by model import and improve the modeling efficiency.
High Frequency Structure simulation software (HFSS) can efficiently design various High Frequency structures and programs. The method is electromagnetic simulation software which is used more in the industry, and a bonding wire modeling module is integrated inside the method. A wire bonding modeling tool is embedded in the HFSS, the HFSS comprises 3 types, namely a solid state technology association four-point control model (JEDEC 4-point, Joint Electron Device Engineering Council 4-point), a JEDEC 5-point and a low, wherein the JEDEC 5-point control model is most accurate, and a bonding wire model can be generated by inputting key parameters such as the arch height, the span, the diameter and the like of a bonding wire.
The HFSS supports the output of three-dimensional models with various formats, such as stp, x _ t and the like, and can realize data exchange with ANSYS workbench.
As shown in fig. 1, an embodiment of the present disclosure provides a modeling method for a system-in-package module, including:
step 11, establishing a PCB model according to PCB design of a printed circuit board;
The method has the advantages that the printed circuit board model is established to provide a fixed connection foundation for other parts, the pins, the welding pads and the welding flux are modeled, and the printed circuit board model is connected with other devices through the pins and the welding flux, so that the detail degree of the model is improved, and the problem of low local reliability analysis precision caused by over-simplified modeling of the system-in-package module in the prior art can be solved.
In some embodiments, the SiP module is fixedly connected to the PCB through pins to form a board level model, and the PCB model is established according to the actual PCB size of the SiP module.
In some embodiments, building a pin, pad, and solder model according to pin layout and molding criteria includes: the method comprises the steps of establishing pins according to parameters of bending radius, distance from a board and beam length in a pin forming standard, adding pins, welding flux and welding pads according to pin layout parameters, and establishing pin, welding pad and welding flux models. Wherein, the pad includes: chip side pads and PCB side pads.
In some embodiments, the shaped pins are soldered to the PCB by solder, enabling board level application of the SiP module. In general, a device user specifies parameter ranges influencing the mechanical properties of the pins, such as bending radius, distance from a board, beam length and the like in a pin forming standard, and the device gives pin layout parameters in a packaging design stage, so that a pin model meeting requirements can be established according to the pin layout and the forming standard.
Fig. 2 is a physical model diagram of a pin and solder of a metallographic section of a device provided in an embodiment of the present disclosure, fig. 3 is a simplified model diagram of the device provided in the embodiment of the present disclosure, and fig. 4 is a detailed model diagram of the device provided in the embodiment of the present disclosure. From a comparison of fig. 2, 3 and 4, it can be seen intuitively that the precision of the device detailed model provided by the embodiment of the present disclosure is extremely high. The solder joint failure mode is that cracks or even fractures are usually generated on solder, and the thermal stress of a device is usually concentrated on the root of a pin, so that the establishment of an accurate pin, a pad and a solder model can accurately reflect an area with high failure probability, further, weak links can be accurately evaluated, early failure prediction is realized, and the development cost of the device is reduced.
The modeling method for the system-in-package module provided by the embodiment of the disclosure is different from the existing modeling method in simplifying processing of the root of the formed pin and the solder at the root, combines a failure case, aims to improve reliability analysis reliability, and accurately models the pin and the solder according to a metallographic sectioning result to provide a model basis for strength checking.
In some embodiments, before establishing the PCB model, the method further comprises: and establishing a solder ring model according to the design of the sealing cap.
In some embodiments, hermetic capping of the housing cavity is an essential part of SiP module packaging, and the capping is usually performed by both a close seam sealing and a parallel seam welding, as shown in fig. 6, the upper cavity is sealed by an alloy cover plate and a solder ring, and the lower cavity is subjected to parallel seam welding by a step cover plate. A solder ring is established between the alloy cover plate and the ceramic envelope, typically 25 μm thick. Optionally, the solder ring is a gold-tin solder ring.
In some embodiments, the sealing cap is designed by two modes of alloy sealing and parallel seam welding, wherein the alloy sealing refers to the connection between the cover plate and the tube shell through welding materials, and the parallel seam welding refers to the connection between the cover plate and the tube shell through joule heat to locally melt the cover plate into welding points to form a continuous welding line.
In some embodiments, before establishing the PCB model, the method further comprises: and establishing a bonding model.
In some embodiments, the order of modeling the solder ring model and the bonding model prior to modeling the PCB is not limited herein. Optionally, the order is, build solder ring model, build bonding model, build PCB model. Another alternative sequence is to build a bonding model, build a solder ring model, build a PCB model.
In some embodiments, further comprising: and establishing a shell model according to the shell design. After the pipe shell model is built, a solder ring model is built or a bonding model is built.
In some embodiments, the ceramic package is the base of the SiP module, and the package is first modeled. The tube shell is formed by laminating a plurality of layers of ceramic sheets printed with circuits, and the overall dimension and the thickness of each layer of the tube shell are determined during the packaging design stage. Therefore, according to the shell Design file, a coordinate system is selected from Model Design (DM, Design Model) of Ansys Workbench to establish each layer of shell Model in sequence, and then the multilayer shell Model can be generated. As shown in FIG. 6, the ceramic tube shell has 10 layers, which are sequentially named as L1-L10, wherein the thickness of L1 is 1mm, and the thicknesses of L2-L9 are all 0.2 mm. For a double-sided double-cavity ceramic shell, the upper cavity is formed by digging a cavity in the ceramic body, and the lower cavity is formed by adding a kovar ring.
In some embodiments, the cartridge model refers to a cartridge that is formed by laminating a plurality of ceramic printed boards, and the production process of the cartridge generally includes: casting, blanking, punching, hole filling, printing, laminating, hot cutting, sintering, nickel plating, brazing and gold plating, wherein the punching refers to the generation of a via hole, and the hole filling refers to the filling of the via hole by using conductive slurry, so that the signal connection between different layers of ceramic substrates is realized.
In some embodiments, establishing a bonding model comprises: conducting modeling on the conductive adhesive and the chip; modeling a chip PAD and a bonding finger; modeling a bonding point and a bonding wire; and carrying out copper coating and via hole modeling.
In some embodiments, conducting adhesive and chip modeling is performed according to the bare chip data and the patch design; in the SiP module, a chip is fixed in a ceramic cavity through a conductive adhesive. The bare chip data gives the chip size, and the patch design gives the layout of each chip and the thickness of the conductive adhesive. As shown in fig. 6, the upper and lower cavities are uniformly distributed with chips and corresponding conductive adhesives.
In some embodiments, chip PAD and bond finger modeling is performed, including: and establishing a chip PAD and bonding finger model according to the bare chip data and the bonding finger design.
In some embodiments, die PAD and bond finger modeling is performed based on die data and bond finger design. The chips of the SiP module form a system through a certain interconnection relationship, and the interconnection relationship between the two chips is realized through "first chip PAD-bonding wire-bonding finger-case surface layer-each layer of routing wire-bonding finger-bonding wire-second chip PAD", as shown in fig. 7. And according to the coordinates and the sizes of all the PADs of the surface layer of the bare chip provided in the bare chip data, the corresponding relation between the PADs of the chip and the bonding fingers provided in the bonding finger design and the positions and the sizes of the bonding fingers, carrying out modeling on the PADs of the chip and the bonding fingers in Ansys Workbench.
In some embodiments, the bond site and the bond wire are modeled according to a bond design and JEDEC five-site control model. The SiP module determines the bonding method, the type of bonding wire and the diameter of the bonding wire during packaging. The bonding means is optionally ball bonding or wedge bonding. The bonding wire type is optionally gold wire or aluminum wire. And the JEDEC 5-point provided in the HFSS obtains coordinates of five key points of the bonding wire through inputting parameters, namely, the modeling of the bonding wire can be realized through fitting. As shown in fig. 6, is a SiP module formed using a common 25 μm gold wire ball bond.
As shown in fig. 8, the lead profile and the parameters required for modeling the bonding wire are: the number of polygonal sides for equivalent circular cross-section is No. of faces 6; the Diameter of the gold wire is 0.025 mm; arch height h1 is 0.2 mm; the height difference h2 of the bonding point is 0.38 mm; bonding point inclination angle Alpha is 80 deg; the bonding point inclination angle Beta is 5 deg; d is the linear distance of the bonding point, and can be set by those skilled in the art as required.
As shown in fig. 7, embodiments of the present disclosure provide a first bond wire 76: arch height H10.32mm, height difference H of bonding point2The first bonding point inclination angle alpha is 80 degrees, the first bonding point inclination angle beta is 18 degrees, and the bonding point straight-line distance D is 2.1 mm; second bonding wire 78: arch height H10.32mm, height difference H of bonding point20.38mm, the second bonding point inclination angle alpha is 80 degrees, the second bonding point inclination angle beta is 30 degrees, and the bonding point straight-line distance D is 1.25 mm.
As shown in fig. 9, in the modeling of the PAD and the bonding finger of the chip according to the embodiment of the disclosure, a bonding mode in which the first bonding point is spherical and the second bonding point is wedge-shaped is adopted.
The embodiment of the disclosure adopts a bonding mode that the first bonding point is spherical and the second bonding point is wedge-shaped, which is the most common and mature bonding mode in the industry. Therefore, the bonding point modeling method provided by the embodiment of the disclosure has certain universality.
In some embodiments, the bond wire modeling is performed in the high frequency structure simulation software HFSS using the solid state technology association five point control model, and other modeling is performed in the reliability analysis platform software Ansys Workbench.
The modeling method for the system-in-package module provided by the embodiment of the disclosure is completed in the Ansys Workbench except that the bonding wire model is established in the HFSS. The joint modeling is realized through HFSS and Ansys Workbench, and the modeling efficiency is improved.
In some embodiments, the modeling of the bonding wire by using the Ansys Workbench requires that a cross section and a motion track of the bonding wire are firstly established, and then a bonding wire model is generated by scanning.
In some embodiments, the results of modeling the bonding wire are imported into the reliability analysis platform software Ansys Workbench according to coordinate transformation.
In some embodiments, the bond wire model is built in the default coordinate system of HFSS, derived in x _ t format. When introducing the Ansys Workbench, the current working coordinate system of the Ansys Workbench is ensured to be coincident with the HFSS default coordinate system. For example, the origin of coordinates in HFSS is usually the starting point of the bonding wire, as shown in fig. 7, the starting point of the first bonding wire 76 should be at the center of the upper surface of the first bonding point 74, and therefore the origin of the current working coordinates of Ansys Workbench must be at the center of the upper surface of the first bonding point 74 and the directions are consistent, so as to ensure that the bonding wire model in HFSS is guided to the correct position in Ansys Workbench, otherwise, the bonding wire model needs to be moved after being guided.
In some embodiments, copper metallization and via modeling is performed as a function of the layer routing of the package. Fig. 7 shows a model of bond fingers, copper metallization and vias with the model parameters of 0.275 x 0.1mm bond fingers, 0.1mm bond finger spacing, 0.2mm via diameter, and 0.015mm copper metallization thickness.
According to the modeling method for the system-in-package module provided by the embodiment of the disclosure, the solder ring, the chip PAD, the bonding finger, the bonding point, the bonding wire, the via hole, the copper coating, the bonding PAD and other detailed parts are modeled, so that the model fineness is improved, the board-level detailed modeling of the system-in-package module is realized, and a research object is provided for the device reliability analysis.
According to the modeling method for the system-in-package module provided by the embodiment of the disclosure, the modeling is performed on the solder ring, the chip PAD, the bonding finger, the bonding point, the bonding wire, the via hole, the copper coating, the bonding PAD and other detailed parts, so that the internal structure of the model can be more accurately reflected, and a more powerful guarantee is provided for the accurate analysis of high reliability.
According to the modeling method for the system-in-package module, provided by the embodiment of the disclosure, each part of modeling is based on a certain design basis or control standard, so that the modeling process is well documented and meets the specification.
As shown in fig. 10, an embodiment of the present disclosure provides an electronic device for system-in-package module modeling, including: a processor (processor)100 and a memory (memory)101 that store program instructions may also include a Communication Interface 102 and a bus 103. The processor 100, the communication interface 102, and the memory 101 may communicate with each other via a bus 103. The communication interface 102 may be used for information transfer. The processor 100 may call logic instructions in the memory 101 to perform the modeling method for the system-in-package module of the above embodiment.
In addition, the logic instructions in the memory 101 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products.
The memory 101, which is a computer-readable storage medium, may be used for storing software programs, computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 100 executes the functional application and data processing by executing the software program, instructions and modules stored in the memory 101, that is, implements the modeling method for the system-in-package module in the above method embodiment.
The memory 101 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the memory 101 may include a high-speed random access memory, and may also include a nonvolatile memory.
The disclosed embodiments provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described modeling method for a system-in-package module.
The disclosed embodiments provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the above-described modeling method for a system-in-package module.
The computer-readable storage medium described above may be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium.
The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes, and may also be a transient storage medium.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the disclosed embodiments includes the full ambit of the claims, as well as all available equivalents of the claims. As used in this application, although the terms "first," "second," etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, unless the meaning of the description changes, so long as all occurrences of the "first element" are renamed consistently and all occurrences of the "second element" are renamed consistently. The first and second elements are both elements, but may not be the same element. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other like elements in a process, method or apparatus that comprises the same element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit may be merely a division of a logical function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A modeling method for a system-in-package module, comprising:
establishing a PCB model according to PCB design of a printed circuit board;
establishing a pin, a bonding pad and a solder model according to a pin layout and a molding standard;
and the PCB model is connected with other devices through the pins and the solder to form a board-level model.
2. The method of claim 1, wherein modeling the pins, pads, and solder according to pin placement and molding criteria comprises:
and establishing pins according to parameters of bending radius, distance from a board and beam length in a pin forming standard, adding the pins, the solder and the bonding pads according to pin layout parameters, and establishing a pin model, a bonding pad model and a solder model.
3. The method of claim 1, wherein prior to modeling the PCB, further comprising: and establishing a solder ring model according to the design of the sealing cap.
4. The method of claim 1, 2 or 3, wherein before modeling the PCB, further comprising: and establishing a bonding model.
5. The method of claim 4, wherein said creating a bonding model comprises:
conducting modeling on the conductive adhesive and the chip;
modeling a chip PAD and a bonding finger;
modeling a bonding point and a bonding wire;
and carrying out copper coating and via hole modeling.
6. The method of claim 5, wherein said performing die PAD, bond site and bond finger modeling comprises:
and establishing a chip PAD, a bonding point and a bonding finger model according to the bare chip data and the bonding finger design.
7. The method of claim 6,
and in the modeling of the chip PAD and the bonding finger, a bonding mode that the first bonding point is spherical and the second bonding point is wedge-shaped is adopted.
8. The method of claim 5,
the modeling of the bonding point and the bonding wire is carried out in high-frequency structure simulation software HFSS by adopting a five-point control model of the solid state technology association, and other modeling is carried out in reliability analysis platform software Ansys workbench.
9. The method of claim 8,
and according to coordinate transformation, importing the results of modeling the bonding points and the bonding wires into reliability analysis platform software Ansys Workbench.
10. An electronic device for system-in-package module modeling, comprising a processor and a memory storing program instructions, characterized in that the processor is configured to perform the method of any of claims 1 to 9 when executing the program instructions.
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