CN110620146B - Field plate structure and semiconductor device - Google Patents
Field plate structure and semiconductor device Download PDFInfo
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- CN110620146B CN110620146B CN201910907838.1A CN201910907838A CN110620146B CN 110620146 B CN110620146 B CN 110620146B CN 201910907838 A CN201910907838 A CN 201910907838A CN 110620146 B CN110620146 B CN 110620146B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 239000004020 conductor Substances 0.000 claims abstract description 134
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 48
- 238000002161 passivation Methods 0.000 description 17
- 238000010168 coupling process Methods 0.000 description 14
- 238000005859 coupling reaction Methods 0.000 description 14
- 230000008878 coupling Effects 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 11
- 238000009825 accumulation Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a field plate structure and a semiconductor device, which relate to the technical field of semiconductor devices and comprise a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein a wall bottom field plate is arranged at the bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into the upper surface of the second insulating dielectric layer, the vertical wall conductor and the wall bottom field plate enclose a collecting cavity for collecting charges, and a guide field plate for introducing the charges into the collecting cavity is further arranged on the upper surface of the second insulating dielectric layer. The invention can effectively improve the stability of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a field plate structure and a semiconductor device.
Background
In the prior art, a field plate structure is generally used for stabilizing charges on the surface of a semiconductor device and blocking external mobile charges from entering a terminal structure at the edge of a semiconductor device chip. However, the inventors have found that the prior art field plate structure has gaps between the field plates, and that when there is a potential difference across the field plates, the movable charges will not be shielded and will move freely in the gaps in the direction from high to low potential, eventually entering the field plate structure, and accumulating over time will reduce the stability of the semiconductor device.
Disclosure of Invention
The invention aims to provide a field plate structure and a semiconductor device, which can effectively improve the stability of the semiconductor device.
In a first aspect, the invention provides a field plate structure, which comprises a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein a wall bottom field plate is arranged at the bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into the upper surface of the second insulating dielectric layer, the vertical wall conductor and the wall bottom field plate enclose a collecting cavity for collecting charges, and a guiding field plate for guiding charges into the collecting cavity is further arranged on the upper surface of the second insulating dielectric layer.
Further, the guide field plates and the vertical wall conductors are arranged on the upper surface of the second insulating dielectric layer at a first preset interval.
Further, an overlap length of the guide field plate and the wall bottom field plate in a vertical direction is less than or equal to twice a thickness of the second insulating dielectric layer.
Further, the guiding field plate comprises a first conductive plate and a second conductive plate, and a conductor post connecting the first conductive plate and the second conductive plate.
Further, the first conductive plate is arranged on the upper surface of the second insulating dielectric layer;
the first conductive plates and the vertical wall conductors are arranged on the upper surface of the second insulating dielectric layer at a second preset interval, wherein the second preset interval is larger than twice the thickness of the second insulating dielectric layer;
the second conductive plate is disposed at a bottom end of the second insulating dielectric layer.
Further, one end of the guide field plate is connected with the wall bottom field plate through a conductor post, and the distance between the other end of the guide field plate and the conductor post in the horizontal aspect is greater than or equal to the thickness of the second insulating dielectric layer.
Further, the guide field plate is arranged on one side or two sides of the vertical wall conductor.
Further, the vertical wall conductor comprises a T-shaped vertical wall conductor and/or an I-shaped vertical wall conductor;
the vertical wall conductor is made of polysilicon and/or metal.
Further, the first insulating dielectric layer and the second insulating dielectric layer each comprise an oxide dielectric layer;
the material of the oxidation dielectric layer in the first insulation dielectric layer comprises silicon dioxide material;
the material of the oxidation dielectric layer in the second insulation dielectric layer comprises boron phosphorus silicon material or polyimide material.
In a second aspect, the present invention provides a semiconductor device, including a lateral metamorphic doping termination device and a field limiting ring termination device;
the transverse variable doping terminal device and the field limiting ring terminal device both adopt the field plate structure described in the first aspect.
The embodiment of the invention has the following beneficial effects:
the invention provides a field plate structure and a semiconductor device, which comprise a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein a wall bottom field plate is arranged at the bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into the upper surface of the second insulating dielectric layer, the vertical wall conductor and the wall bottom field plate enclose a collecting cavity for collecting charges, and a guide field plate for introducing charges into the collecting cavity is further arranged on the upper surface of the second insulating dielectric layer. In the above manner provided in this embodiment, the vertical wall conductor and the wall bottom field enclose the collection cavity for collecting charges in the second insulating dielectric layer, and then the charges are introduced into the collection cavity by the guide field plate disposed on the upper surface of the second insulating dielectric layer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a field plate structure according to a first embodiment of the present invention;
fig. 2 is a schematic view of a first structure of a guiding field plate provided by the first embodiment of the present invention, which is disposed at one side of a vertical wall conductor;
FIG. 3 is a schematic view of a first structure of a guiding field plate according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of a second structure of a guiding field plate provided by the first embodiment of the invention, which is disposed at one side of a vertical wall conductor;
fig. 5 is a schematic diagram of a second structure of a guiding field plate according to a first embodiment of the present invention, wherein the guiding field plate is disposed at two sides of a vertical wall conductor;
fig. 6 is a schematic view of a third structure of a guiding field plate provided by the first embodiment of the present invention, which is disposed at one side of a vertical wall conductor;
fig. 7 is a schematic diagram of a fourth structure of a guide field plate according to the first embodiment of the present invention disposed on two sides of a vertical wall conductor;
fig. 8 is a schematic diagram of a semiconductor device according to a second embodiment of the present invention;
fig. 9 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 10 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 11 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 12 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 13 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 14 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 15 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 16 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 17 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 18 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 19 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 20 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 21 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 22 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 23 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 24 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 25 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 26 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 27 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 28 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 29 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 30 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 31 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 32 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 33 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 34 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 35 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 36 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 37 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 38 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 39 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 40 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 41 is a schematic structural diagram of a field plate structure applied to a lateral variable doping terminal device according to a second embodiment of the present invention;
fig. 42 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 43 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 44 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 45 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention;
fig. 46 is a schematic structural diagram of a field plate structure applied to a field limiting ring terminal device according to a second embodiment of the present invention.
Icon: 1-a semiconductor; 2-a first insulating dielectric layer; 3-a second insulating dielectric layer; 4-a wall bottom field plate; 5-vertical wall conductors; 6-guiding a field plate; 7-a collection chamber; 8-diffusion regions; a 9-P+ region; 10-a first conductive plate; 11-field limiting rings; 12-field plates; 13-an insulating dielectric layer; 14-coupling field plates; 15-a second conductive plate; a 100-semiconductor device; 200-a lateral variable doping termination device; 300-field limiting ring terminal device; 400-field plate structure.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to solve the problem that in the prior art, charges can freely move in gaps of a field plate when electric potentials exist at two ends of the field plate and then enter the field plate structure to reduce the stability of a semiconductor device, the invention provides the field plate structure and the semiconductor device, which comprise a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein the bottom end of the second insulating dielectric layer is provided with a wall bottom field plate, the upper surface of the second insulating dielectric layer is inserted with a vertical wall conductor, the vertical wall conductor and the wall bottom field plate are surrounded to form a collecting cavity for collecting the charges, the upper surface of the second insulating dielectric layer is also provided with a guide field plate for guiding the charges into the collecting cavity, the charges are guided into the collecting cavity through the vertical wall conductor and the wall bottom field plate on the second insulating dielectric layer, and then the charges are stably guided into the collecting cavity through the guide field plate arranged on the upper surface of the second insulating dielectric layer, so that the stability of the semiconductor device can be effectively improved.
For the sake of understanding the present embodiment, a field plate structure disclosed in the present embodiment is first described in detail.
Embodiment one:
referring to a schematic diagram of a field plate structure shown in fig. 1, the schematic diagram includes a first insulating dielectric layer 2 and a second insulating dielectric layer 3 which are connected, a wall bottom field plate 4 is disposed at the bottom end of the second insulating dielectric layer 3, a vertical wall conductor 5 is inserted into the upper surface of the second insulating dielectric layer 3, the vertical wall conductor 5 and the wall bottom field plate 4 enclose a collecting cavity 7 for collecting charges, and a guiding field plate 6 for guiding charges into the collecting cavity 7 is further disposed on the upper surface of the second insulating dielectric layer 3.
In a specific embodiment, the first insulating dielectric layer 2, the second insulating dielectric layer 3 and the guiding field plate 6 are manufactured by adopting photoetching and etching processes, and the manufacturing difficulty can be reduced by adopting a simple process. The guiding field plate 6 has the function of adsorbing charges, the guiding field plate 6 is adjacent to the collecting cavity 7, and meanwhile, the vertical wall conductor 5 and the charges are mutually induced, so that the charges can be introduced into the collecting cavity 7.
In addition, the bottom of the collecting cavity 7 is a conductive field plate, the movable charges in the collecting cavity 7 lose the influence on the silicon surface, and the field plate structure can also collect and bind the movable charges coming in from the outside. The terminal for field plate structure application is composed of a plurality of field plate structures, each field plate structure is separated by a vertical wall conductor 5, and therefore accumulation of high-density movable charges caused by long-distance movement of the movable charges is avoided.
In the above manner provided in this embodiment, the vertical wall conductor 5 and the wall bottom field enclose the collecting cavity 7 for collecting charges in the second insulating dielectric layer 3, and then the charges are introduced into the collecting cavity 7 by the guiding field plate 6 disposed on the upper surface of the second insulating dielectric layer 3, so that the charges can be collected in the collecting cavity 7, and compared with the manner that the charges in the prior art can freely move between the field plate gaps, the stability of the semiconductor device can be effectively improved by stabilizing the charges in the collecting cavity 7 through the collecting cavity 7.
In the specific implementation, the guiding field plate 6 is arranged at one side or two sides of the vertical wall conductor 5, and according to the different arrangement modes of the guiding field plate 6, the field plate structure comprises the following three structures:
(1) Referring to a first structural schematic diagram in which the guide field plates 6 shown in fig. 2 are disposed at one side of the vertical wall conductor 5 and the guide field plates 6 shown in fig. 3 are disposed at both sides of the vertical wall conductor 5, the guide field plates 6 and the vertical wall conductor 5 are arranged at a first predetermined interval on the upper surface of the second insulating dielectric layer 3.
Wherein the overlap length of the guide field plate 6 and the wall bottom field plate 4 in the vertical direction is less than or equal to twice the thickness of the second insulating dielectric layer 3.
(2) Referring to a second structural schematic of the guide field plate 6 shown in fig. 4 disposed at one side of the vertical wall conductor 5 and the guide field plate 6 shown in fig. 5 disposed at both sides of the vertical wall conductor 5, the guide field plate 6 includes a first conductive plate 10 and a second conductive plate 15, and a conductor post connecting the first conductive plate 10 and the second conductive plate 15. The first conductive plate 10 is disposed on the upper surface of the second insulating dielectric layer 3; the first conductive plates 10 and the vertical wall conductors 5 are arranged on the upper surface of the second insulating dielectric layer 3 at a second preset interval, wherein the second preset interval is more than twice the thickness of the second insulating dielectric layer 3; the second conductive plate 15 is disposed at the bottom end of the second insulating dielectric layer 3.
(3) Referring to a third structural schematic diagram in which the guide field plates 6 shown in fig. 6 are disposed on one side of the vertical wall conductor 5 and the guide field plates 6 shown in fig. 7 are disposed on both sides of the vertical wall conductor 5, one end of the guide field plates 6 is connected to the wall bottom field plates 4 through conductor posts, and the distance between the other end of the guide field plates 6 and the conductor posts in the horizontal direction is greater than or equal to the thickness of the second insulating dielectric layer 3.
In the above manner provided in this embodiment, charges may be collected according to field plate structures with different structures, so as to improve stability of the semiconductor device.
In particular implementations, the vertical wall conductors 5 include T-shaped vertical wall conductors 5 and/or I-shaped vertical wall conductors 5. The vertical wall conductor 5 is made of polysilicon and/or metal.
The first insulating dielectric layer 2 and the second insulating dielectric layer 3 each comprise an oxide dielectric layer.
The material of the oxide dielectric layer in the first insulating dielectric layer 2 comprises a silicon dioxide material.
The material of the oxide dielectric layer in the second insulating dielectric layer 3 includes a boron phosphorus silicon material or a polyimide material.
In the above manner provided in this embodiment, the process difficulty of the field plate structure may be reduced by using the oxide dielectric layer and the polysilicon material and/or the metal material.
Embodiment two:
referring to fig. 8, a schematic diagram of a semiconductor device 100 is shown, including a lateral varying doping termination means 200 and a field limiting ring termination means 300.
The field plate structure 400 of the first embodiment is used for both the lateral metamorphic doping termination device 200 and the field limiting ring termination device 300.
In the above manner provided in this embodiment, the vertical wall conductor 5 and the wall bottom field enclose the collecting cavity 7 for collecting charges in the second insulating dielectric layer 3, and then the charges are introduced into the collecting cavity 7 by the guiding field plate 6 disposed on the upper surface of the second insulating dielectric layer 3, so that the charges can be collected in the collecting cavity 7, and compared with the manner that the charges in the prior art can freely move between the field plate gaps, the stability of the semiconductor device can be effectively improved by stabilizing the charges in the collecting cavity 7 through the collecting cavity 7.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 2, which is arranged on one side of the vertical wall conductor 5, can be applied to a lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 9, in which a conventional floating field plate 12 is arranged at a distance above the first insulating dielectric layer 2 above the diffusion region 8. As shown in fig. 10, on the conventional floating field plate 12, a vertical wall conductor 5 is added by taking the floating field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small sections, so that long-distance movement of movable charges is avoided, and accumulation of high-density movable charges is avoided. In addition, a vertical wall conductor 5 may be added to the lateral variable doping terminal device 200 near the active region side and at the end of the lateral variable doping terminal device 200 to form a collection cavity 7 of movable charges for reducing the amount of movable charges of the lateral variable doping terminal device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 shown in fig. 2, in which the guiding field plate 6 is disposed at one side of the vertical wall conductor, may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 11, wherein the field plate structure 400 is repeatedly placed at a certain pitch, bridging the active region edge p+ region 9 and the diffusion region 8 and the surface of the semiconductor 1, and forming passivation structures of a plurality of movable charge collecting cavities 7 on the semiconductor surface. In addition, a vertical wall conductor 5 may be added to the lateral variable doping terminal device 200 near the active region and at the end of the lateral variable doping terminal device 200 to form a collection cavity 7 of movable charges, so as to reduce the amount of movable charges in the lateral variable doping terminal device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 3 disposed at both sides of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 12, wherein the field plate structure 400 is repeatedly placed at a certain pitch, straddling the active region edge p+ region 9 and the diffusion region 8 and the surface of the semiconductor 1, and forming passivation structures of a plurality of movable charge collecting cavities 7 on the semiconductor surface; a vertical wall conductor 5 may also be added to the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for the movable charges, for reducing the amount of movable charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, may be applied to the lateral variable doping terminal device 200, the application structure of which is shown with reference to fig. 12 and 13, wherein an insulating dielectric layer 13 is further added, and in the field plate structure 400 shown in fig. 3, the vertical wall conductor 5 is added to cut off the insulating dielectric layer 13 on top of the guiding field plates 6. A plurality of movable charge collection chambers 7 are also formed in the insulating dielectric layer 13 by electrical coupling between adjacent vertical wall conductors 5; a passivation structure of two layers of a plurality of movable charge collection cavities 7 is thus formed over the semiconductor surface for reducing the amount of movable charges in the lateral metamorphic termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 of the guiding field plate 6 shown in fig. 3 disposed at two sides of the vertical wall conductor 5 may be applied to the lateral variable doping terminal device 200, and its application structure is shown with reference to fig. 12 and 14, wherein an insulating dielectric layer 13 is further added, and in the second insulating dielectric layer 3 and the insulating dielectric layer 13, a longitudinal and lateral cascade structure is formed, and a passivation structure of two layers of a plurality of movable charge collecting cavities 7 is formed on the semiconductor surface for reducing the amount of movable charges of the lateral variable doping terminal device 200 and the chip active region. Further improving the collection capability of the movable charges. In this structure, the guiding field plate 6 of the field plate structure 400 may be divided into left and right 2 sections in the middle, and the same effect is achieved. In the same way, the field plate structure 400 may be multi-layered in the longitudinal direction.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 2 disposed at one side of the vertical wall conductor 5 may be applied to the field limiting ring termination 300, and the application structure thereof is shown with reference to fig. 15, wherein in the field limiting ring termination 300, the outermost field limiting ring and the end of the device are generally disposed to be the widest of the whole device for improving the voltage resistance and the stability of the voltage resistance, and the field plate structure 400 has a relatively strong capability of collecting the movable charges due to a relatively large width. Further, as shown in fig. 16, on the field plate 12 on the field limiting ring 11, a vertical wall conductor 5 is added by taking the field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small sections, so that long-distance movement of movable charges is avoided, and accumulation of high-density movable charges is avoided.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 2 disposed on one side of the vertical wall conductor 5 may be applied to the field limiting ring termination device 300, and the application structure thereof is shown with reference to fig. 17, wherein the field plate structure 400 is repeatedly placed by adjusting the lateral distance of the field plate structure 400 according to a certain interval in combination with the interval of the field limiting rings 11, and a passivation structure of a plurality of movable charge collecting cavities 7 is formed on the semiconductor surface and straddling the active region edge p+ region 9 and the field limiting ring 11 arrangement region and the surface of the semiconductor 1; vertical wall conductors 5 may be added to the field ring termination 300 on the side near the active region and at the end of the field ring termination 300 to form a collection cavity 7 for movable charges for reducing the number of movable charges in the field ring termination 300 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guide field plate 6 shown in fig. 3 disposed at both sides of the vertical wall conductor 5 may be applied to the field limiting ring termination device 300, the application structure of which is shown with reference to fig. 18, wherein the field plate structure 400 is repeatedly placed at a certain interval in combination with the interval of the field limiting rings 11, adjusting the lateral distance of the field plate structure 400, bridging the active region edge p+ region 9 and the field limiting ring 11 arrangement region and the surface of the semiconductor 1, and forming passivation structures of the plurality of movable charge collecting cavities 7 on the semiconductor surface; vertical wall conductors 5 may also be added to the field-limiting ring terminal device on the side near the active region and at the end of the field-limiting ring terminal device 300 to form a collection cavity 7 for the movable charges, for reducing the amount of movable charges in the field-limiting ring terminal device 300 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are arranged on both sides of the vertical wall conductor 5, can be applied to the field limiting ring termination 300, the application structure of which is shown with reference to fig. 18 and 19, wherein an insulating dielectric layer 13 is further added, and the vertical wall conductor 5 is added to cut off the insulating dielectric layer 13 above the guiding field plates 6 in the field plate structure 400. A plurality of movable charge collection chambers 7 are also formed in the insulating dielectric layer 13 by electrical coupling between adjacent vertical wall conductors 5; a passivation structure of two layers of a plurality of movable charge collection cavities 7 is thus formed over the semiconductor surface for reducing the amount of movable charges in the field limiting ring termination device 300 and the active area of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 of the guide field plate 6 shown in fig. 3 disposed on both sides of the vertical wall conductor 5 can be applied to the field limiting ring termination 300, the application structure of which is shown with reference to fig. 18 and 20, wherein an insulating dielectric layer 13 is added, and the field plate structure 400 forms a longitudinal and transverse cascade structure in the second insulating dielectric layer 3 and the insulating dielectric layer 13. A passivation structure of two layers of a plurality of movable charge collection cavities 7 is formed on the semiconductor surface for reducing the amount of movable charges of the lateral variable doping termination device 200 and the chip active region, further improving the collection capability of the movable charges.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 4, which is arranged on one side of the vertical wall conductor 5, can be applied to a lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 21, wherein the floating field plates 12 are arranged at a distance above the second insulating dielectric layer 3. Further, as shown in fig. 22, the floating field plate 12 is used as a wall bottom field plate to add the vertical wall conductor 5, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small sections, so that long-distance movement of the movable charges is prevented, and accumulation of high-density movable charges is avoided; a vertical wall conductor 5 may also be added to the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for the movable charges, for reducing the amount of movable charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 4 disposed on one side of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 23, wherein the field plate structure 400 is repeatedly placed at a certain pitch, and spans the active region edge p+ region 9 and the diffusion region 8 and the surface of the semiconductor 1, forming passivation structures of a plurality of movable charge collecting cavities 7 on the semiconductor surface; a vertical wall conductor 5 may also be added to the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for the movable charges, for reducing the amount of movable charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 4 disposed at one side of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 24, wherein the field plate structure 400 is repeatedly placed at a certain interval by the electric field coupling field plate 14, and spans the active region edge p+ region 9 and the diffusion region 8 and the surface of the semiconductor 1, forming passivation structures of a plurality of movable charge collecting cavities 7 on the semiconductor surface; a vertical wall conductor 5 may also be added to the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for the movable charges, for reducing the amount of movable charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 4, in which the guiding field plate is disposed at one side of the vertical wall conductor 5, may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 24 and 25, wherein an insulating dielectric layer 13 is further added, and the vertical wall conductor 5 is added above the electric field coupling field plate 14 to cut off the insulating dielectric layer 13. A plurality of movable charge collection chambers 7 are also formed in the insulating dielectric layer 13 by electrical coupling between adjacent vertical wall conductors 5; a passivation structure of two layers of a plurality of movable charge collection cavities 7 is thus formed over the semiconductor surface for reducing the amount of movable charges in the lateral metamorphic termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 4, in which the guiding field plate is disposed at one side of the vertical wall conductor 5, may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 24 and 26, wherein the guiding field plate 6 is added at one side of the vertical wall conductor 5 in the insulating dielectric layer 13, forming the field plate structure 400, enhancing the charge collecting capability of the movable charge collecting cavity 7. For reducing the amount of mobile charges in the lateral metamorphic termination device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 5 disposed on both sides of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 27, wherein the field plate structure 400 is repeatedly placed at a certain pitch, and spans the active region edge p+ region 9 and the diffusion region 8 and the surface of the semiconductor 1, forming passivation structures of a plurality of movable charge collecting cavities 7 on the semiconductor surface; further, as shown in fig. 28, the field plate structure 400 is repeatedly placed at a certain interval by the electric field coupling field plate 14, and is bridged over the active region edge p+ region 9 and the diffusion region 8 and the surface of the semiconductor 1, and a passivation structure of a plurality of movable charge collecting cavities 7 is formed on the semiconductor surface; a vertical wall conductor 5 may also be added to the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for the movable charges, for reducing the amount of movable charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 of the guiding field plate 6 shown in fig. 5 disposed on one side of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 28 and 29, wherein an insulating dielectric layer 13 is further added, and the vertical wall conductor 5 is added above the electric field coupling field plate 14 to cut off the insulating dielectric layer 13. A plurality of movable charge collection chambers 7 are also formed in the insulating dielectric layer 13 by electrical coupling between adjacent vertical wall conductors 5; further improvement, as shown in fig. 30, a guiding field plate 6 is added to one side or two sides of the vertical wall conductor 5 in the insulating dielectric layer 13 to form the field plate structure 400, so as to further enhance the charge collecting capability of the movable charge beam collecting cavity 7, and reduce the amount of the movable charges of the lateral variable doping terminal device 200 and the chip active region.
In a specific embodiment, the field plate structure 400 of the guide field plate shown in fig. 4 disposed at one side of the vertical wall conductor 5 may be applied to the field limiting ring termination 300, the application structure of which is shown with reference to fig. 31, wherein the field plate structure 400 is applied at the upper portion of the outermost field limiting ring 11. Further, as shown in fig. 32, on the field plate 12 on the conventional field limiting ring 11, a vertical wall conductor 5 is added by taking the field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small sections, so that long-distance movement of movable charges is prevented, and accumulation of high-density movable charges is avoided; vertical wall conductors 5 may be added to the field ring termination 300 on the side near the active region and at the end of the field ring termination 300 to form a collection cavity 7 for movable charges for reducing the number of movable charges in the field ring termination 300 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 4 disposed at one side of the vertical wall conductor 5 may be applied to the field limiting ring termination device 300, and the application structure thereof is shown with reference to fig. 33, wherein the field plate structure 400 is repeatedly placed at a certain interval in combination with the interval of the field limiting rings 11, by adjusting the lateral distance of the field plate structure 400, and a passivation structure of a plurality of movable charge collecting cavities 7 is formed on the semiconductor surface across the active region edge p+ region 9 and the field limiting ring 11 arrangement region and the surface of the semiconductor 1; vertical wall conductors 5 may be added to the field ring termination 300 on the side near the active region and at the end of the field ring termination 300 to form a collection cavity 7 for movable charges for reducing the number of movable charges in the field ring termination 300 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 4 disposed at one side of the vertical wall conductor 5 may be applied to the field limiting ring termination device 300, the application structure of which is shown with reference to fig. 34, wherein the field plate structure 400 is formed by coupling the field plates 14 at a certain interval, adjusting the lateral distance of the field plate structure 400 in combination with the interval of the field limiting rings 11, repeatedly placing the field plate structure 400 across the active region edge p+ region 9 and the field limiting ring 11 arrangement region and the surface of the semiconductor 1, and forming passivation structures of a plurality of movable charge collecting cavities 7 on the semiconductor surface; vertical wall conductors 5 may be added to the field ring termination 300 on the side near the active region and at the end of the field ring termination 300 to form a collection cavity 7 for movable charges for reducing the number of movable charges in the field ring termination 300 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 of the guiding field plate 6 shown in fig. 4 disposed on one side of the vertical wall conductor 5 may be applied to the field limiting ring termination 300, the application structure of which is shown with reference to fig. 34 and 35, wherein an insulating dielectric layer 13 is further added, and the vertical wall conductor 5 is added above the electric field coupling field plate 14 to cut off the insulating dielectric layer 13. A plurality of movable charge collection chambers 7 are also formed in the insulating dielectric layer 13 by electrical coupling between adjacent vertical wall conductors 5; further improvement, as shown in fig. 36, a guiding field plate 6 is added to one side or two sides of the vertical wall conductor 5 in the insulating dielectric layer 13 to form the field plate structure 400, so as to enhance the charge collecting capability of the movable charge beam collecting 7. For reducing the amount of field-limiting ring termination device 300 and the active area mobile charge of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 6 disposed at one side of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 37, wherein the field plate structure 400 is applied above the diffusion region PN junction and the floating field plate 12 is disposed at a certain interval above the second insulating dielectric layer 3 above the diffusion region 8. Further, as shown in fig. 38, on the floating field plate 12, a vertical wall conductor 5 is added by taking the floating field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small sections, thereby preventing the movable charges from moving for a long distance and causing the accumulation of high-density movable charges; a vertical wall conductor 5 may be added in the lateral metamorphic termination device 200 on the side near the active region and at the end of the lateral metamorphic termination device 200 to form a collection cavity 7 for the movable charges for reducing the amount of the movable charges in the lateral metamorphic termination device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 6 disposed on one side of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 39, wherein the field plate structure 400 is repeatedly placed at a certain pitch, and spans the active region edge p+ region 9 and the diffusion region 8 and the surface of the semiconductor 1, forming passivation structures of a plurality of movable charge collecting cavities 7 on the semiconductor surface; a vertical wall conductor 5 may be added in the lateral metamorphic termination device 200 on the side near the active region and at the end of the lateral metamorphic termination device 200 to form a collection cavity 7 for the movable charges for reducing the amount of the movable charges in the lateral metamorphic termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 of the guiding field plate 6 shown in fig. 6 disposed at one side of the vertical wall conductor 5 may be applied to the lateral variable doping termination device 200, the application structure of which is shown with reference to fig. 39 and 40, wherein an insulating dielectric layer 13 is further added, and the vertical wall conductor 5 is added to cut off the insulating dielectric layer 13 above the guiding field plate 6 of the field plate structure 400. A plurality of movable charge collection chambers 7 are also formed in the insulating dielectric layer 13 by electrical coupling between adjacent vertical wall conductors 5; further improved structure, as shown in fig. 41, a guiding field plate 6 is added on one side of the vertical wall conductor 5 in the insulating dielectric layer 13 to form the field plate structure 400, thereby enhancing the charge collecting capability of the movable charge collecting cavity 7, and reducing the amount of the movable charges of the lateral variable doping terminal device 200 and the chip active region.
In a specific embodiment, the field plate structure 400 of the guide field plate 6 shown in fig. 6 disposed at one side of the vertical wall conductor 5 may be applied to the field limiting ring termination 300, the application structure of which is shown with reference to fig. 42, wherein the field plate structure 400 is applied at the upper portion of the outermost field limiting ring 11. Further, as shown in fig. 43, on the field plate 12 on the field limiting ring 11, a vertical wall conductor 5 is added by taking the field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small sections, so that long-distance movement of the movable charges is prevented, and accumulation of high-density movable charges is avoided; the outermost field stop ring and the end of the field stop ring termination device 300 are typically arranged widest to increase the collection of movable charges by the field plate structure 400.
In a specific embodiment, the field plate structure 400 of the guiding field plate 6 shown in fig. 6 disposed at one side of the vertical wall conductor 5 may be applied to the field limiting ring termination device 300, the application structure of which is shown with reference to fig. 44, wherein the field plate structure 400 is repeatedly placed at a certain interval in combination with the interval of the field limiting rings 11 and the lateral distance of the field plate structure 400 is adjusted, and passivation structures of a plurality of movable charge collecting cavities 7 are formed on the semiconductor surface across the active region edge p+ region 9 and the field limiting ring 11 arrangement region and the surface of the semiconductor 1; vertical wall conductors 5 may be added to the field ring termination 300 on the side near the active region and at the end of the field ring termination 300 to form a collection cavity 7 for movable charges for reducing the number of movable charges in the field ring termination 300 and the active region of the chip.
In a specific embodiment, with further modifications, the field plate structure 400 shown in fig. 6, in which the guiding field plate 6 is arranged on one side of the vertical wall conductor 5, can be applied to the field ring termination device 300, the application structure of which is shown with reference to fig. 44 and 45, wherein an insulating dielectric layer 13 is added, and above the guiding field plate 6 of said field plate structure 400, the vertical wall conductor 5 is added to cut off the insulating dielectric layer 13. A plurality of movable charge collection chambers 7 are also formed in the insulating dielectric layer 13 by electrical coupling between adjacent vertical wall conductors 5; further improvement, as shown in fig. 46, a guiding field plate 6 is added to one side or two sides of the vertical wall conductor 5 in the insulating dielectric layer 13 to form a field plate structure 400, so as to enhance the charge collecting capability of the movable charge collecting cavity 7. At the same time, a vertical wall conductor 5 can be added at the tail end of the field limiting ring terminal device 300 to form a movable charge collecting cavity 7 for reducing the quantity of movable charges of the field limiting ring terminal device 300.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (9)
1. The field plate structure is characterized by comprising a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein a wall bottom field plate is arranged at the bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into the upper surface of the second insulating dielectric layer, the vertical wall conductor and the wall bottom field plate enclose a collecting cavity for collecting charges, and a guide field plate for introducing charges into the collecting cavity is further arranged on the upper surface of the second insulating dielectric layer; one end of the guide field plate is connected with the wall bottom field plate through a conductor column, and the distance between the other end of the guide field plate and the conductor column in the horizontal aspect is larger than or equal to the thickness of the second insulating dielectric layer.
2. The field plate structure of claim 1 wherein the guide field plate and the vertical wall conductors are arranged at a first predetermined spacing on the upper surface of the second insulating dielectric layer.
3. The field plate structure of claim 2, wherein an overlap length of the guide field plate and the wall bottom field plate in a vertical direction is less than or equal to twice a thickness of the second insulating dielectric layer.
4. The field plate structure of claim 1 wherein the guiding field plate comprises a first conductive plate and a second conductive plate, and a conductor post connecting the first conductive plate and the second conductive plate.
5. The field plate structure of claim 4 wherein said first conductive plate is disposed on an upper surface of said second insulating dielectric layer;
the first conductive plates and the vertical wall conductors are arranged on the upper surface of the second insulating dielectric layer at a second preset interval, wherein the second preset interval is larger than twice the thickness of the second insulating dielectric layer;
the second conductive plate is disposed at a bottom end of the second insulating dielectric layer.
6. A field plate structure according to any of claims 1-5, characterized in that the guiding field plate is arranged on one or both sides of the vertical wall conductor.
7. The field plate structure of claim 1 wherein the vertical wall conductors comprise T-type vertical wall conductors and/or I-type vertical wall conductors;
the vertical wall conductor is made of polysilicon and/or metal.
8. The field plate structure of claim 1 wherein said first insulating dielectric layer and said second insulating dielectric layer each comprise an oxidized dielectric layer;
the material of the oxidation dielectric layer in the first insulation dielectric layer comprises silicon dioxide material;
the material of the oxidation dielectric layer in the second insulation dielectric layer comprises boron phosphorus silicon material or polyimide material.
9. A semiconductor device comprising a lateral variable doping termination means and a field limiting ring termination means;
the lateral variable doping terminal device and the field limiting ring terminal device each employ the field plate structure of any one of claims 1 to 8.
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| CN101345254A (en) * | 2007-07-12 | 2009-01-14 | 富士电机电子技术株式会社 | Semiconductor device |
| CN106653830A (en) * | 2015-10-28 | 2017-05-10 | 无锡华润上华半导体有限公司 | Semiconductor device voltage-withstanding structure |
| CN107818964A (en) * | 2017-12-11 | 2018-03-20 | 四川九鼎智远知识产权运营有限公司 | A kind of voltage semiconductor device |
| CN109216430A (en) * | 2017-06-30 | 2019-01-15 | 无锡华润华晶微电子有限公司 | Semiconductor transverse varying doping terminal structure and preparation method thereof |
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| CN101345254A (en) * | 2007-07-12 | 2009-01-14 | 富士电机电子技术株式会社 | Semiconductor device |
| CN106653830A (en) * | 2015-10-28 | 2017-05-10 | 无锡华润上华半导体有限公司 | Semiconductor device voltage-withstanding structure |
| CN109216430A (en) * | 2017-06-30 | 2019-01-15 | 无锡华润华晶微电子有限公司 | Semiconductor transverse varying doping terminal structure and preparation method thereof |
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