CN110620146A - Field plate structure and semiconductor device - Google Patents
Field plate structure and semiconductor device Download PDFInfo
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- CN110620146A CN110620146A CN201910907838.1A CN201910907838A CN110620146A CN 110620146 A CN110620146 A CN 110620146A CN 201910907838 A CN201910907838 A CN 201910907838A CN 110620146 A CN110620146 A CN 110620146A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 239000004020 conductor Substances 0.000 claims description 134
- 239000000463 material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 49
- 238000002161 passivation Methods 0.000 description 17
- 230000008878 coupling Effects 0.000 description 13
- 238000010168 coupling process Methods 0.000 description 13
- 238000005859 coupling reaction Methods 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 11
- 238000009825 accumulation Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a field plate structure and a semiconductor device, and relates to the technical field of semiconductor devices. The invention can effectively improve the stability of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a field plate structure and a semiconductor device.
Background
In the prior art, a terminal structure at the edge of a semiconductor device chip generally adopts a field plate structure to stabilize charges on the surface of the semiconductor device and block the entering of external movable charges. However, the inventor has found that, in the field plate structure of the prior art, a gap exists between the field plates, when a potential difference exists between two ends of the field plates, the movable charges cannot be shielded, and freely move in the gap along the direction from high potential to low potential, and finally enter the field plate structure, and the stability of the semiconductor device is reduced along with the accumulation of time.
Disclosure of Invention
The invention aims to provide a field plate structure and a semiconductor device, which can effectively improve the stability of the semiconductor device.
In a first aspect, the present invention provides a field plate structure, including a first insulating dielectric layer and a second insulating dielectric layer connected to each other, where a wall bottom field plate is disposed at a bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into an upper surface of the second insulating dielectric layer, and the vertical wall conductor and the wall bottom field plate enclose a collection cavity for collecting charges, and a guide field plate for introducing charges into the collection cavity is further disposed on the upper surface of the second insulating dielectric layer.
Further, the guidance field plate and the vertical wall conductor are arranged on the upper surface of the second insulating dielectric layer at a first preset interval.
Further, the overlap length of the guiding field plate and the wall bottom field plate in the vertical direction is less than or equal to two times of the thickness of the second insulating dielectric layer.
Further, the guidance field plate includes a first conductive plate and a second conductive plate, and a conductor pillar connecting the first conductive plate and the second conductive plate.
Further, the first conductive plate is arranged on the upper surface of the second insulating dielectric layer;
the first conductive plates and the vertical wall conductors are arranged on the upper surface of the second insulating dielectric layer at a second preset interval, wherein the second preset interval is more than twice the thickness of the second insulating dielectric layer;
the second conductive plate is disposed at a bottom end of the second insulating dielectric layer.
Further, one end of the guiding field plate is connected with the wall bottom field plate through a conductor pillar, and the distance between the other end of the guiding field plate and the conductor pillar in the horizontal direction is larger than or equal to the thickness of the second insulating dielectric layer.
Further, the guide field plate is provided on one side or both sides of the vertical wall conductor.
Further, the vertical wall conductor comprises a T-shaped vertical wall conductor and/or an I-shaped vertical wall conductor;
the vertical wall conductor is made of polysilicon and/or metal.
Further, the first insulating dielectric layer and the second insulating dielectric layer each include an oxide dielectric layer;
the material of the oxide dielectric layer in the first insulating dielectric layer comprises a silicon dioxide material;
the material of the oxide dielectric layer in the second insulating dielectric layer comprises boron phosphorus silicon material or polyimide material.
In a second aspect, the present invention provides a semiconductor device comprising a lateral variable doping termination and a field limiting ring termination;
the lateral variable doping termination device and the field limiting ring termination device both adopt the field plate structure of the first aspect.
The embodiment of the invention has the following beneficial effects:
the invention provides a field plate structure and a semiconductor device, which comprise a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein a wall bottom field plate is arranged at the bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into the upper surface of the second insulating dielectric layer, a collection cavity for collecting charges is enclosed by the vertical wall conductor and the wall bottom field plate, and a guide field plate for introducing the charges into the collection cavity is also arranged on the upper surface of the second insulating dielectric layer. In the above manner provided by this embodiment, a collection cavity for collecting charges is defined by the vertical wall conductor and the wall bottom field in the second insulating dielectric layer, and then charges are introduced into the collection cavity by the guiding field plate disposed on the upper surface of the second insulating dielectric layer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a field plate structure according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of a first structure of a guiding field plate disposed on one side of a vertical wall conductor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a first structure of a guiding field plate disposed on two sides of a vertical wall conductor according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a second structure of a guiding field plate disposed on one side of a vertical wall conductor according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a second structure of a guiding field plate disposed on two sides of a vertical wall conductor according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a third structure of a guiding field plate disposed on one side of a vertical wall conductor according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a fourth structure of a guiding field plate disposed on two sides of a vertical wall conductor according to an embodiment of the present invention;
fig. 8 is a schematic view of a semiconductor device according to a second embodiment of the present invention;
fig. 9 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 10 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 11 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 12 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 13 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 14 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 15 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 16 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 17 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 18 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 19 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 20 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 21 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 22 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 23 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 24 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 25 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 26 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 27 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 28 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 29 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 30 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 31 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 32 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 33 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 34 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 35 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 36 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 37 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 38 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 39 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 40 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 41 is a schematic structural diagram of a field plate structure applied to a lateral variable doping termination device according to a second embodiment of the present invention;
fig. 42 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 43 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 44 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 45 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention;
fig. 46 is a schematic structural diagram of a field plate structure applied to a field limiting ring termination device according to a second embodiment of the present invention.
Icon: 1-a semiconductor; 2-a first insulating dielectric layer; 3-a second insulating dielectric layer; 4-wall bottom field plate; 5-vertical wall conductors; 6-a guided field plate; 7-a collection chamber; 8-a diffusion region; a 9-P + region; 10-a first conductive plate; 11-a field limiting ring; 12-a field plate; 13-an insulating dielectric layer; 14-a coupled field plate; 15-a second conductive plate; 100-a semiconductor device; 200-lateral variable doping termination; 300-field limiting ring termination; 400-field plate structure.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to solve the problem that in the prior art, when electric potential exists at two ends of a field plate, electric charge can freely move in a field plate gap and then enter the field plate structure, so that the stability of a semiconductor device is reduced, the invention provides the field plate structure and the semiconductor device, which comprise a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein a wall bottom field plate is arranged at the bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into the upper surface of the second insulating dielectric layer, a collecting cavity for collecting the electric charge is formed by the vertical wall conductor and the wall bottom field plate, a guide field plate for introducing the electric charge into the collecting cavity is further arranged on the upper surface of the second insulating dielectric layer, a collecting cavity for collecting the electric charge is formed by the vertical wall conductor and the wall bottom field plate in the second insulating dielectric layer in a surrounding manner, and the electric charge is introduced into the collecting cavity by the guide field plate arranged on the upper surface of, the electric charges are stabilized in the collecting cavity through the collecting cavity, so that the stability of the semiconductor device can be effectively improved.
For the understanding of the present embodiment, a field plate structure disclosed in the present embodiment will be described in detail first.
The first embodiment is as follows:
referring to fig. 1, a field plate structure diagram includes a first insulating dielectric layer 2 and a second insulating dielectric layer 3 which are connected, a wall bottom field plate 4 is disposed at a bottom end of the second insulating dielectric layer 3, a vertical wall conductor 5 is inserted into an upper surface of the second insulating dielectric layer 3, the vertical wall conductor 5 and the wall bottom field plate 4 enclose a collection cavity 7 for collecting charges, and a guidance field plate 6 for introducing charges into the collection cavity 7 is further disposed on the upper surface of the second insulating dielectric layer 3.
In a specific embodiment, the first insulating dielectric layer 2, the second insulating dielectric layer 3 and the guiding field plate 6 are all manufactured by using a photolithography and etching process, which is simple and can reduce the manufacturing difficulty. The guide field plate 6 has a function of adsorbing charges, the guide field plate 6 is adjacent to the collection chamber 7, and the vertical wall conductor 5 interacts with the charges to introduce the charges into the collection chamber 7.
In addition, the bottom of the collection cavity 7 is a conductor field plate, the movable charges in the collection cavity 7 lose the influence on the silicon surface, and the field plate structure can also collect and restrain the movable charges coming from the outside. The terminal applied by the field plate structure is composed of a plurality of field plate structures, and each field plate structure is separated by a vertical wall conductor 5, so that the accumulation of high-density movable charges caused by long-distance movement of the movable charges is avoided.
In the above manner provided by this embodiment, the vertical wall conductor 5 and the wall bottom field enclose the collection cavity 7 for collecting charges in the second insulating dielectric layer 3, and then the guiding field plate 6 disposed on the upper surface of the second insulating dielectric layer 3 guides charges into the collection cavity 7, so that charges can be collected in the collection cavity 7, and compared with the prior art in which charges can freely move between field plate gaps, the present embodiment stabilizes charges in the collection cavity 7 through the collection cavity 7, which can effectively improve the stability of the semiconductor device.
In specific implementation, the guiding field plate 6 is disposed on one side or both sides of the vertical wall conductor 5, and the field plate structure includes the following three structures according to the different arrangement modes of the guiding field plate 6:
(1) referring to a first structure diagram of fig. 2 in which the guide field plate 6 is disposed on one side of the vertical wall conductor 5 and fig. 3 in which the guide field plate 6 is disposed on both sides of the vertical wall conductor 5, the guide field plate 6 and the vertical wall conductor 5 are arranged at a first predetermined interval on the upper surface of the second insulating dielectric layer 3.
Wherein the overlap length of the guiding field plate 6 and the wall bottom field plate 4 in the vertical direction is less than or equal to twice the thickness of the second insulating dielectric layer 3.
(2) Referring to a second structural diagram in which the guide field plate 6 shown in fig. 4 is provided on one side of the vertical wall conductor 5 and the guide field plate 6 shown in fig. 5 is provided on both sides of the vertical wall conductor 5, the guide field plate 6 includes a first conductive plate 10 and a second conductive plate 15, and a conductor pillar connecting the first conductive plate 10 and the second conductive plate 15. The first conductive plate 10 is disposed on the upper surface of the second insulating dielectric layer 3; the first conductive plates 10 and the vertical wall conductors 5 are arranged on the upper surface of the second insulating dielectric layer 3 at second preset intervals, wherein the second preset intervals are more than twice the thickness of the second insulating dielectric layer 3; the second conductive plate 15 is disposed at the bottom end of the second insulating dielectric layer 3.
(3) Referring to a third structural diagram in which the guide field plate 6 is disposed on one side of the vertical wall conductor 5 as shown in fig. 6 and the guide field plate 6 is disposed on both sides of the vertical wall conductor 5 as shown in fig. 7, one end of the guide field plate 6 is connected to the wall bottom field plate 4 through a conductor pillar, and the distance between the other end of the guide field plate 6 and the conductor pillar in the horizontal direction is greater than or equal to the thickness of the second insulating dielectric layer 3.
In the above manner provided by this embodiment, charges can be collected according to field plate structures of different structures, thereby improving the stability of the semiconductor device.
In particular, the vertical wall conductors 5 include T-shaped vertical wall conductors 5 and/or I-shaped vertical wall conductors 5. The material of the vertical wall conductor 5 includes a polysilicon material and/or a metal material.
The first insulating dielectric layer 2 and the second insulating dielectric layer 3 each include an oxide dielectric layer.
The material of the oxide dielectric layer in the first insulating dielectric layer 2 includes a silicon dioxide material.
The material of the oxide dielectric layer in the second insulating dielectric layer 3 includes a boron-phosphorus-silicon material or a polyimide material.
In the above manner provided in this embodiment, the process difficulty of the field plate structure can be reduced by using the oxide dielectric layer and the polysilicon material and/or the metal material.
Example two:
referring to fig. 8, a semiconductor device 100 is schematically illustrated including a lateral variable doping termination device 200 and a field limiting ring termination device 300.
The lateral variable-doping termination device 200 and the field limiting ring termination device 300 both employ the field plate structure 400 of the first embodiment.
In the above manner provided by this embodiment, the vertical wall conductor 5 and the wall bottom field enclose the collection cavity 7 for collecting charges in the second insulating dielectric layer 3, and then the guiding field plate 6 disposed on the upper surface of the second insulating dielectric layer 3 guides charges into the collection cavity 7, so that charges can be collected in the collection cavity 7, and compared with the prior art in which charges can freely move between field plate gaps, the present embodiment stabilizes charges in the collection cavity 7 through the collection cavity 7, which can effectively improve the stability of the semiconductor device.
In a specific embodiment, the field plate structure 400 shown in fig. 2, in which the guide field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 9, in which a conventional floating field plate 12 is disposed on the first insulating dielectric layer 2 above the diffusion region 8 at a pitch. As shown in fig. 10, on the conventional floating field plate 12, the floating field plate 12 is used as a wall bottom field plate to add a vertical wall conductor 5, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small segments, so that the long-distance movement of the movable charges is avoided, and the accumulation of the high-density movable charges is avoided. In addition, a vertical wall conductor 5 can be added to the side of the lateral variable doping termination device 200 close to the active region and at the end of the lateral variable doping termination device 200 to form a movable charge collecting cavity 7 for reducing the amount of movable charges in the lateral variable doping termination device 200 and the chip active region.
In a specific embodiment, the field plate structure 400 shown in fig. 2, in which the guide field plate 6 is disposed on one side of the vertical wall conductor, can be applied to the lateral variable doping termination device 200, and the application structure thereof is shown in fig. 11, wherein the field plate structure 400 is repeatedly disposed at a certain pitch, and bridges the active region edge P + region 9 and the diffusion region 8 and the surface of the semiconductor 1, and a passivation structure of a plurality of movable charge collection cavities 7 is formed on the surface of the semiconductor. In addition, a vertical wall conductor 5 can be added to the side close to the active region in the lateral variable doping terminal device 200 and at the end of the lateral variable doping terminal device 200 to form a movable charge collecting cavity 7 for reducing the quantity of movable charges in the lateral variable doping terminal device 200 and the chip active region.
In a specific embodiment, the field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and the application structure thereof is shown in fig. 12, wherein the field plate structure 400 is repeatedly disposed at a certain pitch, and bridges over the active region edge P + region 9 and the diffusion region 8 and the surface of the semiconductor 1, and a passivation structure of a plurality of movable charge collection cavities 7 is formed above the semiconductor surface; it is also possible to add vertical wall conductors 5 in the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for mobile charges for reducing the number of mobile charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 12 and 13, wherein an additional insulating dielectric layer 13 is added, and in the field plate structure 400 shown in fig. 3, the vertical wall conductor 5 is added on the guiding field plate 6 to cut off the insulating dielectric layer 13. A plurality of movable charge collection cavities 7 are also formed in the insulating dielectric layer 13 by the electrical coupling between the adjacent vertical wall conductors 5; a passivation structure of two layers of a plurality of movable charge collection cavities 7 is thus formed over the semiconductor surface for reducing the amount of movable charges in the lateral metamoded termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 12 and fig. 14, wherein an additional insulating dielectric layer 13 is added, a longitudinal and lateral cascade structure is formed in the second insulating dielectric layer 3 and the insulating dielectric layer 13, and a passivation structure of two layers of a plurality of movable charge collecting cavities 7 is formed above the semiconductor surface, so as to reduce the number of movable charges in the lateral variable doping termination device 200 and the active region of the chip. The collection ability of the movable charges is further improved. In this structure, the guiding field plate 6 of the field plate structure 400 can also be divided into left and right 2 segments in the middle, with the same effect. In the same way, the field plate structure 400 can be stacked in multiple layers in the longitudinal direction.
In a specific embodiment, the field plate structure 400 shown in fig. 2, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and the application structure is shown in fig. 15, wherein in the field limiting ring termination device 300, the outermost field limiting ring and the end of the device are generally set to be the widest of the whole device, so as to improve the voltage resistance and the stability of the voltage resistance, because the width is relatively large, the field plate structure 400 also has relatively strong collection capability for the movable charges. Further, as shown in fig. 16, on the field plate 12 above the field limiting ring 11, the vertical wall conductor 5 is added by using the field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small segments, so that the accumulation of high-density movable charges due to long-distance movement of the movable charges is avoided.
In a specific embodiment, the field plate structure 400 shown in fig. 2, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 17, wherein the field plate structure 400 is repeatedly placed by adjusting the lateral distance of the field plate structure 400 according to a certain pitch and combining with the pitch of the field limiting rings 11, and bridges the active region edge P + region 9 and the arrangement region of the field limiting rings 11 and the surface of the semiconductor 1, so as to form a passivation structure of a plurality of movable charge collection cavities 7 on the surface of the semiconductor; it is also possible to add vertical wall conductors 5 in the field limiting ring termination device 300 on the side close to the active region and at the end of the field limiting ring termination device 300 to form a charge trapping cavity 7 for reducing the amount of charge trapped in the field limiting ring termination device 300 and the active region of the chip.
In a specific embodiment, the field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and the application structure is shown in fig. 18, wherein the field plate structures 400 are repeatedly disposed at a certain interval, in combination with the interval of the field limiting rings 11, to adjust the lateral distance of the field plate structures 400, and bridge over the active region edge P + region 9, the arrangement region of the field limiting rings 11, and the surface of the semiconductor 1, so as to form a passivation structure of a plurality of movable charge collection cavities 7 on the surface of the semiconductor; it is also possible to add vertical wall conductors 5 in the end-of-field-limiting-ring device near the active area side and at the end of the end-of-field-limiting-ring device 300 to form a collection chamber 7 for mobile charges, for reducing the number of mobile charges in the end-of-field-limiting-ring device 300 and in the active area of the chip.
In a specific embodiment, with further improvement, a field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 18 and fig. 19, wherein an insulating dielectric layer 13 is further added, and the vertical wall conductor 5 is added to cut off the insulating dielectric layer 13 above the guiding field plate 6 in the field plate structure 400. A plurality of movable charge collection cavities 7 are also formed in the insulating dielectric layer 13 by the electrical coupling between the adjacent vertical wall conductors 5; a passivation structure of two layers of a plurality of movable charge collecting cavities 7 is thus formed over the semiconductor surface for reducing the amount of movable charges in the field limiting ring termination device 300 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 3, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 18 and fig. 20, wherein an additional insulating dielectric layer 13 is added, and the field plate structure 400 forms a longitudinal and lateral cascade structure in the second insulating dielectric layer 3 and the insulating dielectric layer 13. A passivation structure of two layers and a plurality of movable charge collecting cavities 7 is formed on the surface of the semiconductor, and is used for reducing the quantity of movable charges in the transverse variable doping terminal device 200 and the active area of the chip, and further improving the collecting capability of the movable charges.
In a specific embodiment, the field plate structure 400 shown in fig. 4, in which the guiding field plates 6 are disposed on one side of the vertical wall conductors 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 21, in which floating field plates 12 are disposed on the second insulating dielectric layer 3 at a certain interval. Further, as shown in fig. 22, a floating field plate 12 is used as a wall bottom field plate to add a vertical wall conductor 5, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small sections, so that the accumulation of high-density movable charges due to long-distance movement of the movable charges is avoided; it is also possible to add vertical wall conductors 5 in the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for mobile charges for reducing the number of mobile charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 shown in fig. 4, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and the application structure thereof is shown in fig. 23, wherein the field plate structure 400 is repeatedly disposed at a certain pitch, and bridges over the active region edge P + region 9 and the diffusion region 8 and the surface of the semiconductor 1, and a passivation structure of a plurality of movable charge collection cavities 7 is formed on the surface of the semiconductor; it is also possible to add vertical wall conductors 5 in the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for mobile charges for reducing the number of mobile charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 shown in fig. 4, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and the application structure thereof is shown in fig. 24, wherein the field plate structure 400 is repeatedly disposed at a certain pitch by the electric field coupling field plate 14, and bridges over the active region edge P + region 9 and the diffusion region 8 and the surface of the semiconductor 1, and forms a passivation structure of a plurality of movable charge collection cavities 7 on the semiconductor surface; it is also possible to add vertical wall conductors 5 in the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for mobile charges for reducing the number of mobile charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, with further modification, the field plate structure 400 shown in fig. 4, in which the guiding field plate is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 24 and fig. 25, wherein an additional insulating dielectric layer 13 is added, and the vertical wall conductor 5 is added on the electric field coupling field plate 14 to cut off the insulating dielectric layer 13. A plurality of movable charge collection cavities 7 are also formed in the insulating dielectric layer 13 by the electrical coupling between the adjacent vertical wall conductors 5; a passivation structure of two layers of a plurality of movable charge collection cavities 7 is thus formed over the semiconductor surface for reducing the amount of movable charges in the lateral metamoded termination device 200 and the active region of the chip.
In a specific embodiment, with further modification, the field plate structure 400 shown in fig. 4, in which the guiding field plate is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 24 and fig. 26, wherein the guiding field plate 6 is added on one side of the vertical wall conductor 5 in the insulating dielectric layer 13 to form the field plate structure 400, so as to enhance the charge collection capability of the movable charge collection cavity 7. For reducing the amount of movable charge in the lateral variation doped termination device 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 shown in fig. 5, in which the guiding field plates 6 are disposed on both sides of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and the application structure thereof is shown in fig. 27, wherein the field plate structure 400 is repeatedly disposed at a certain pitch, and bridges over the active region edge P + region 9 and the diffusion region 8 and the surface of the semiconductor 1, and a passivation structure of a plurality of movable charge collection cavities 7 is formed on the surface of the semiconductor; further, as shown in fig. 28, the field plate structure 400 is repeatedly disposed at a certain pitch by the electric field coupling field plate 14, and bridges over the active region edge P + region 9 and the diffusion region 8 and the surface of the semiconductor 1, forming a passivation structure of a plurality of movable charge collection cavities 7 on the semiconductor surface; it is also possible to add vertical wall conductors 5 in the lateral variable doping termination device 200 near the active region side and at the end of the lateral variable doping termination device 200 to form a collection cavity 7 for mobile charges for reducing the number of mobile charges in the lateral variable doping termination device 200 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 5, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 28 and fig. 29, wherein an additional insulating dielectric layer 13 is added, and the vertical wall conductor 5 is added on the electric field coupling field plate 14 to cut off the insulating dielectric layer 13. A plurality of movable charge collection cavities 7 are also formed in the insulating dielectric layer 13 by the electrical coupling between the adjacent vertical wall conductors 5; in a further improved structure, as shown in fig. 30, a guiding field plate 6 is added on one side or two sides of the vertical wall conductor 5 in the insulating dielectric layer 13 to form the field plate structure 400, so as to enhance the charge collection capability of the movable charge beam collection cavity 7, thereby reducing the amount of movable charges in the lateral doping terminal device 200 and the chip active region.
In a specific embodiment, the field plate structure 400 shown in fig. 4, in which the guide field plate is disposed on one side of the vertical wall conductor 5, may be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 31, in which the field plate structure 400 is applied to the upper portion of the outermost field limiting ring 11. Further, as shown in fig. 32, on the field plate 12 above the conventional field limiting ring 11, the vertical wall conductor 5 is added by using the field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small segments, so that the accumulation of high-density movable charges due to long-distance movement of the movable charges is avoided; it is also possible to add vertical wall conductors 5 in the field limiting ring termination device 300 on the side close to the active region and at the end of the field limiting ring termination device 300 to form a charge trapping cavity 7 for reducing the amount of charge trapped in the field limiting ring termination device 300 and the active region of the chip.
In a specific embodiment, the field plate structure 400 shown in fig. 4, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and the application structure is shown in fig. 33, wherein the field plate structure 400 is repeatedly disposed at a certain interval, in combination with the interval of the field limiting rings 11, to adjust the lateral distance of the field plate structure 400, and bridges over the active region edge P + region 9, the arrangement region of the field limiting rings 11, and the surface of the semiconductor 1, so as to form a passivation structure of a plurality of movable charge collection cavities 7 on the surface of the semiconductor; it is also possible to add vertical wall conductors 5 in the field limiting ring termination device 300 on the side close to the active region and at the end of the field limiting ring termination device 300 to form a charge trapping cavity 7 for reducing the amount of charge trapped in the field limiting ring termination device 300 and the active region of the chip.
In a specific embodiment, a field plate structure 400 of fig. 4, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 34, wherein the field plate structure 400 is repeatedly disposed by coupling field plates 14 through an electric field according to a certain pitch, in combination with the pitch of the field limiting rings 11, and adjusting the lateral distance of the field plate structure 400, and bridges over the active region edge P + region 9 and the field limiting ring 11 arrangement region and the surface of the semiconductor 1, so as to form a passivation structure of a plurality of movable charge collection cavities 7 on the semiconductor surface; it is also possible to add vertical wall conductors 5 in the field limiting ring termination device 300 on the side close to the active region and at the end of the field limiting ring termination device 300 to form a charge trapping cavity 7 for reducing the amount of charge trapped in the field limiting ring termination device 300 and the active region of the chip.
In a specific embodiment, with further improvement, the field plate structure 400 shown in fig. 4, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 34 and fig. 35, wherein an additional insulating dielectric layer 13 is added, and the vertical wall conductor 5 is added on the electric field coupling field plate 14 to cut off the insulating dielectric layer 13. A plurality of movable charge collection cavities 7 are also formed in the insulating dielectric layer 13 by the electrical coupling between the adjacent vertical wall conductors 5; a further improved structure, as shown in fig. 36, is to add a guiding field plate 6 on one side or both sides of the vertical wall conductor 5 in the insulating dielectric layer 13 to form the field plate structure 400, thereby enhancing the charge collection capability of the movable charge beam collector 7. For reducing the amount of movable charges in the field limiting ring termination device 300 and the active region of the chip.
In a specific embodiment, a field plate structure 400 shown in fig. 6, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 37, in which the field plate structure 400 is applied on the PN junction of the diffusion region, and the floating field plates 12 are disposed on the second insulating dielectric layer 3 on the diffusion region 8 at a certain interval. Further, as shown in fig. 38, on the floating field plate 12, a vertical wall conductor 5 is added by using the floating field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small segments, so that the accumulation of high-density movable charges due to long-distance movement of the movable charges is avoided; vertical wall conductors 5 may be added to the lateral variable doping termination 200 near the active region side and at the ends of the lateral variable doping termination 200 to form a movable charge collection cavity 7 for reducing the amount of movable charge in the lateral variable doping termination 200 and the active region of the chip.
In a specific embodiment, the field plate structure 400 shown in fig. 6, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and the application structure thereof is shown in fig. 39, wherein the field plate structure 400 is repeatedly disposed at a certain pitch, and bridges over the active region edge P + region 9 and the diffusion region 8 and the surface of the semiconductor 1, and a passivation structure of a plurality of movable charge collection cavities 7 is formed on the surface of the semiconductor; vertical wall conductors 5 may be added to the lateral variable doping termination 200 near the active region side and at the ends of the lateral variable doping termination 200 to form a movable charge collection cavity 7 for reducing the amount of movable charge in the lateral variable doping termination 200 and the active region of the chip.
In a specific embodiment, with further modification, the field plate structure 400 shown in fig. 6, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the lateral variable doping termination device 200, and its application structure is shown in fig. 39 and fig. 40, wherein an additional insulating dielectric layer 13 is added, and the vertical wall conductor 5 is added on the guiding field plate 6 of the field plate structure 400 to cut off the insulating dielectric layer 13. A plurality of movable charge collection cavities 7 are also formed in the insulating dielectric layer 13 by the electrical coupling between the adjacent vertical wall conductors 5; in a further improved structure, as shown in fig. 41, a guiding field plate 6 is added on one side of the vertical wall conductor 5 in the insulating dielectric layer 13 to form the field plate structure 400, so as to enhance the charge collection capability of the movable charge collection cavity 7, thereby reducing the amount of movable charges in the lateral variable doping terminal device 200 and the chip active region.
In a specific embodiment, a field plate structure 400 in which the guide field plate 6 shown in fig. 6 is disposed on one side of the vertical wall conductor 5 can be applied to the field limiting ring termination device 300, and the application structure thereof is shown with reference to fig. 42, in which the field plate structure 400 is applied to the upper portion of the outermost field limiting ring 11. Further, as shown in fig. 43, on the field plate 12 above the field limiting ring 11, the vertical wall conductor 5 is added by using the field plate 12 as a wall bottom field plate, the vertical wall conductor 5 cuts off the second insulating dielectric layer 3, and the second insulating dielectric layer 3 is divided into a plurality of small segments, so that the accumulation of high-density movable charges due to long-distance movement of the movable charges is avoided; the outermost field limiting rings and the end of the field limiting ring termination 300 are typically arranged to be widest to increase the collection capability of the field plate structure 400 for mobile charges.
In a specific embodiment, a field plate structure 400 of fig. 6, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 44, wherein the field plate structure 400 is repeatedly disposed at a certain interval, in combination with the interval of the field limiting rings 11, and the lateral distance of the field plate structure 400 is adjusted, and bridges the active region edge P + region 9 and the arrangement region of the field limiting rings 11 and the surface of the semiconductor 1, so as to form a passivation structure of a plurality of movable charge collection cavities 7 on the semiconductor surface; it is also possible to add vertical wall conductors 5 in the field limiting ring termination device 300 on the side close to the active region and at the end of the field limiting ring termination device 300 to form a charge trapping cavity 7 for reducing the amount of charge trapped in the field limiting ring termination device 300 and the active region of the chip.
In a specific embodiment, with further improvement, a field plate structure 400 shown in fig. 6, in which the guiding field plate 6 is disposed on one side of the vertical wall conductor 5, can be applied to the field limiting ring termination device 300, and its application structure is shown in fig. 44 and 45, wherein an insulating dielectric layer 13 is further added, and the vertical wall conductor 5 is added to cut off the insulating dielectric layer 13 on the guiding field plate 6 of the field plate structure 400. A plurality of movable charge collection cavities 7 are also formed in the insulating dielectric layer 13 by the electrical coupling between the adjacent vertical wall conductors 5; in a further improved structure, as shown in fig. 46, a guiding field plate 6 is added on one side or two sides of the vertical wall conductor 5 in the insulating dielectric layer 13 to form a field plate structure 400, thereby enhancing the charge collection capability of the movable charge collection cavity 7. Meanwhile, at the end of the field limiting ring termination device 300, a vertical wall conductor 5 can be added to form a movable charge collecting cavity 7 for reducing the amount of movable charges of the field limiting ring termination device 300.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A field plate structure is characterized by comprising a first insulating dielectric layer and a second insulating dielectric layer which are connected, wherein a wall bottom field plate is arranged at the bottom end of the second insulating dielectric layer, a vertical wall conductor is inserted into the upper surface of the second insulating dielectric layer, a collection cavity for collecting charges is enclosed by the vertical wall conductor and the wall bottom field plate, and a guide field plate for introducing the charges into the collection cavity is further arranged on the upper surface of the second insulating dielectric layer.
2. The field plate structure of claim 1, wherein the guidance field plate and the vertical wall conductor are arranged at a first predetermined spacing on the upper surface of the second insulating dielectric layer.
3. The field plate structure of claim 2, wherein a vertical overlap length of the guided field plate and the bottom-of-wall field plate is less than or equal to twice a thickness of the second insulating dielectric layer.
4. The field plate structure of claim 1, wherein the guidance field plate comprises first and second conductive plates, and a conductor pillar connecting the first and second conductive plates.
5. The field plate structure of claim 4, wherein the first conductive plate is disposed on an upper surface of the second insulating dielectric layer;
the first conductive plates and the vertical wall conductors are arranged on the upper surface of the second insulating dielectric layer at a second preset interval, wherein the second preset interval is more than twice the thickness of the second insulating dielectric layer;
the second conductive plate is disposed at a bottom end of the second insulating dielectric layer.
6. The field plate structure of claim 1, wherein one end of the guided field plate is connected to the wall bottom field plate by a conductor pillar, and the other end of the guided field plate is horizontally spaced from the conductor pillar by a distance greater than or equal to the thickness of the second insulating dielectric layer.
7. The field plate structure of any of claims 1 to 6, wherein the guidance field plate is provided on one or both sides of the vertical wall conductor.
8. The field plate structure of claim 1, wherein the vertical wall conductor comprises a T-shaped vertical wall conductor and/or an I-shaped vertical wall conductor;
the vertical wall conductor is made of polysilicon and/or metal.
9. The field plate structure of claim 1, in which the first insulating dielectric layer and the second insulating dielectric layer each comprise a layer of oxide dielectric;
the material of the oxide dielectric layer in the first insulating dielectric layer comprises a silicon dioxide material;
the material of the oxide dielectric layer in the second insulating dielectric layer comprises boron phosphorus silicon material or polyimide material.
10. A semiconductor device comprising a lateral variable doping termination means and a field limiting ring termination means;
the lateral variable doping termination device and the field limiting ring termination device both adopt the field plate structure of any one of claims 1 to 8.
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