CN109801957B - Super junction device structure, device and preparation method - Google Patents
Super junction device structure, device and preparation method Download PDFInfo
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- CN109801957B CN109801957B CN201811477951.2A CN201811477951A CN109801957B CN 109801957 B CN109801957 B CN 109801957B CN 201811477951 A CN201811477951 A CN 201811477951A CN 109801957 B CN109801957 B CN 109801957B
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Abstract
The embodiment of the invention provides a super junction device structure, a super junction device and a preparation method, wherein the super junction device structure comprises: a first doping type column region, a second doping type column region, a first grid, a second grid and a first diversion region are arranged on the substrate; the first doping type column region and the second doping type column region are arranged above the substrate, the second doping type column region is located between the two first doping type column regions, the first grid electrode and the second grid electrode are isolated and respectively arranged above base regions of the two first doping type column regions, and a first drainage region used for guiding charge flow direction is arranged at the top end of the second doping type column region. The super-junction device solves the problem of charge imbalance of the first doping type column region and the second doping type column region caused by the fact that single-particle-resistant gate penetration is achieved in the prior art, and improves the dynamic characteristic and the single-particle-resistant characteristic of the super-junction device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a super junction device structure, a super junction device and a manufacturing method.
Background
The drift region of a super-junction device (super-junction) is composed of P columns and N columns which are alternately arranged, and when an external voltage is borne, PN junctions formed by the adjacent P columns and N columns are reversely biased and mutually depleted, so that the drift region is approximately an intrinsic semiconductor. The withstand voltage of the device is only related to the length of the drift region and is not related to the doping concentration of the drift region, so that the on-resistance can be reduced by increasing the doping concentration of the drift region. The super junction device simultaneously realizes high breakdown voltage and low on-resistance, solves the problem of silicon limit of the VDMOS, becomes a milestone breakthrough of a power device, and is widely applied to aspects of power electronic systems, automobile electronics and the like.
Super junction devices have been maturely applied in military and civil fields by virtue of excellent performance, and rapid development of modern technologies puts higher requirements on the performance of the devices. For example, in the application background of aerospace and the like, a space radiation environment is extremely complicated due to various particles and rays, and higher requirements are put forward on the reliability of a super junction device in the space radiation environment. The space irradiation environment of the spacecraft is very complex, including protons, electrons, high-energy heavy ions and the like from the Galaxy cosmic rays, the earth radiation zone and the sun, and the single-particle burnout effect (SEB) and the single-particle gate-through effect (SEGR) caused by the fact that the high-energy heavy ions are driven into the device are two main reasons for causing single-particle failure of the device.
At present, the resistance of the P region can be reduced by increasing the doping concentration of the P base region and the depth of the P + column, so that the voltage drop of the hole current flowing through the P base region is reduced, and thus the starting requirement of the parasitic transistor cannot be met, as shown in fig. 1, the P + column is thickened from 3um to 5um (wherein the a structure is before improvement, and the b structure is after improvement). However, the charge balance of the P column and the N column of the super junction device is affected by downward expansion of the P + column, so that the breakdown voltage of the super junction device is reduced, the dynamic characteristics of the super junction device are affected, and the single particle resistance is weak.
Disclosure of Invention
In view of this, embodiments of the present invention provide a super junction device structure, a super junction device, and a manufacturing method thereof, so as to solve the problem of unbalanced charges in the first doped column region and the second doped column region caused by the realization of single-particle-resistant gate punch-through in the prior art, and improve the dynamic characteristics and the single-particle-resistant characteristics of the super junction device.
In a first aspect, an embodiment of the present application provides the following technical solutions:
a superjunction device structure, comprising: a first doping type column region, a second doping type column region, a first grid, a second grid and a first diversion region are arranged on the substrate; the first doping type column region and the second doping type column region are arranged above the substrate, the second doping type column region is located between the two first doping type column regions, the first grid electrode and the second grid electrode are isolated and respectively arranged above base regions of the two first doping type column regions, and a first drainage region used for guiding charge flow direction is arranged at the top end of the second doping type column region.
Preferably, the first doping type column region is doped P-type, and the first drainage region is a P-type region.
Preferably, the first doping type column region is doped in an N type, and the first diversion region is an N type region.
Preferably, the first current guiding region is a trench schottky contact.
Preferably, the method further comprises the following steps: and the second diversion areas are arranged below the base areas of the two first doping type column areas.
Preferably, two of the second diversion areas extend in a direction approaching each other.
Preferably, a buffer layer is included between the substrate and the first and second doping type column regions.
In a second aspect, based on the same inventive concept, an embodiment of the present application provides the following technical solutions:
a superjunction device, comprising: the superjunction device structure of the first aspect, wherein the first doping type column region of each superjunction device structure is connected to the first doping type column region of its adjacent superjunction device structure.
In a third aspect, based on the same inventive concept, an embodiment of the present application provides the following technical solutions:
a method for manufacturing a super junction device structure is used for manufacturing the super junction device structure in the first aspect, etching the middle position of a complete grid electrode, and dividing the grid electrode into a first grid electrode and a second grid electrode.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
compared with the prior art, the super junction device structure, the device and the preparation method provided by the invention have the advantages that the super junction device structure can be used for guiding the flow direction of charges by arranging the first current guiding area at the top of the second doping type column area. And the first grid and the second grid are respectively isolated and positioned above the base regions of the two first doping type column regions, so that no grid is arranged above the first drainage region, a large amount of charges formed after high-energy heavy ions are driven into the second doping type column region can be drained by the first drainage region, and grid breakdown caused by charge accumulation below the grid is avoided. Therefore, the super-junction device and the manufacturing method thereof realize the anti-single-particle gate penetration, solve the problem of charge imbalance of the P column region (the first doped column region/the second doped column region) and the N column region (the first doped column region/the second doped column region) in the prior art, and improve the dynamic characteristic and the anti-single-particle characteristic of the super-junction device.
The foregoing objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a superjunction device structure in the prior art.
Fig. 2 is a schematic structural diagram of a super junction device structure according to a preferred embodiment of the present invention;
fig. 3 is a schematic structural diagram of a second superjunction device structure according to a preferred embodiment of the present invention;
fig. 4 is a schematic structural diagram of a third superjunction device structure according to a preferred embodiment of the present invention;
fig. 5 is a schematic diagram illustrating the flow of holes in a third superjunction device structure according to a preferred embodiment of the present invention;
fig. 6 is a schematic structural diagram of a fourth superjunction device structure provided in the preferred embodiment of the present invention;
fig. 7 is a schematic structural diagram of a superjunction device according to a preferred embodiment of the present invention.
Icon: 100-a superjunction device structure; 200-a super junction device structure; 300-a superjunction device structure; 400-a superjunction device structure; 500-a superjunction device; 11-a substrate; 12-a first doping type column region; 121-base region; 122-a source region; 14-a second doping type column region; 15-a first gate; 16-a second gate; 17-an insulating layer; 18-a first diversion zone; 21-a second diversion zone; 31-a buffer layer; 301-hole flow direction.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the present invention, and are used for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 2, fig. 2 shows a cross-sectional structure of a super junction device structure 100 according to an embodiment of the present invention. The super junction device structure 100 includes: a substrate 11, a first doping type column region 12, a second doping type column region 14, a first gate 15, a second gate 16, a metal layer, and a first current guiding region 18.
The first doping type column region 12 and the second doping type column region 14 are both arranged above the substrate 11, the second doping type column region 14 is located between the two first doping type column regions 12, the first gate 15 and the second gate 16 are respectively arranged above the two first doping type column regions 12 and the base region 121, a metal layer 122 covers the first doping type column region (a metal layer for external connection covers the source region 122 of the base region 121), an oxide layer is arranged between the metal layer and the first gate 15 and the second gate 16 for isolation, and a first current guiding region 18 for guiding the flow direction of charges is arranged at the top of the second doping type column region 14, namely a JFET region.
Specifically, the base region 121 is included at one end of each of the first doping type column region 12 and the second P column region 13 away from the substrate 11, the base region 121 extends toward the second doping type column region 14 and extends to the top of the second doping type column region 14, and a specific forming manner may be generally formed by using a P/N well process without limitation. The base region 121 includes source regions 122, and both the source regions 122 are located outside the base region 121 and are connected to the metal layer.
The first gate 15 and the second gate 16 are covered with a metal layer, and the trench formed between the first gate 15 and the second gate 16 is filled with the metal layer. The first gate 15 and the second gate 16 are formed by etching a complete gate at an intermediate position, i.e. etching away the middle part of the complete gate, and then filling the metal layer. An insulating layer 17, such as silicon dioxide, is wrapped around the first gate 15 and the second gate 16.
And the first diversion area 18 is used for guiding the flow direction of the charges so as to lead the charges out of the device and avoid the charges from accumulating below the insulating layers 17 of the first grid electrode 15 and the second grid electrode 16. The following two implementations are provided in this embodiment for the first diversion area 18:
1. the first current guiding region 18 may be a P-type region, i.e., a P-type region is formed by P-type implantation in the JFET region at the top of the second doped type column region 14, and a bow shape may be formed by controlling the implantation process, as shown in fig. 2. And may be regular or irregular in shape such as square or triangle. In addition, the first drainage region can also be an N-type region.
2. The first current guiding region 18 is a trenched schottky contact, such as the superjunction device structure 200 shown in fig. 3. Specifically, a trench may be formed at the top of the second doped column region 14, and a metal filling (the metal filling should be connected to the metal layer) is disposed in the trench to contact the second doped column region 14 to form a schottky contact, where charges can be conducted out through the schottky contact, and the specific shape of the schottky contact is not limited and can be determined according to the shape of the trench formed at the top of the second doped column region 14, such as the cross section of a bow-shaped trench or a square-shaped trench.
Referring to the super junction device structure 300 of fig. 4, in this embodiment, an implementation manner is further provided, in which a second current guiding region 21 is formed below the base region 121, and the second current guiding region 21 can also be used for guiding the direction of the charges, so as to prevent the charges from accumulating below the gate. The second current guiding region 21, when implemented in combination with the first current guiding region 18, greatly enhances the charge guiding in the second doping type column region 14, and allows for a timely extraction of charge out of the device. The number of the second drain regions 21 is not limited, and for example, a plurality of buried layers may be introduced as the second drain regions 21 on the first doping type column region 12.
In addition, in some embodiments, the second current guiding region 21 may also be implemented separately, and may also play a role in guiding the direction of charge flow, so as to improve the single particle resistance of the superjunction device.
In a preferred embodiment, the second current guiding region 21 is an introduced buried layer. The buried layer is arranged below the base region 121 of the first doping type column region 12, and the forming of the buried layer and the forming of the base region 121 can be compatible in process, so that the production and the manufacturing are convenient to implement.
In order to ensure the current guiding effect of the charges, the charges can be separated from the grid electrode to a greater extent through the type buried layer. In a specific implementation manner, the second current guiding region 21 of the first doping type column region 12 extends to the symmetry plane of the second doping type column region 14, and the total width is greater than or equal to the width of the first gate 15; the second guiding areas 21 of the first doping type column areas 12 extend towards the symmetry plane of the second doping type column areas 14, i.e. the second guiding areas 21 of two said second doping type column areas 12 extend towards each other. In a preferred embodiment, the width of each second diversion area 21 is greater than or equal to the width of the corresponding first gate 15 or second gate 16. As such, even after passing through the gap between the two first doping type column regions 12, there is a greater probability that the charges will be drawn by the first diversion region 18, as shown in fig. 5 by the charge flow direction 301 (which can be represented as an electron flow direction if the super junction device is an NPN type) in the PNP type super junction device structure 300. Specifically, when charges are accumulated to the gate, the charges are blocked and drained by the second drainage region 21, and when the charges pass through a position between two second drainage regions 21, the charges are drained by the first drainage region 18, so that the charges are prevented from accumulating below the first gate 15 or the second gate 16.
Further, the cross-sectional shape of the second diversion area 21 can be arcuate or square, depending on the process requirements, without limitation.
Referring to the super junction device structure 400 shown in fig. 6, in some embodiments, a buffer layer 31 may be disposed between the substrate 11 and the second doped column region 14/the first doped column region 12 to improve the single event resistance of the device, and the buffer layer 31 may play a role in assuming the electric field of the device when the single event effect occurs. Therefore, the buffer layer 31 is added, so that the electric field distribution of the drift region of the device can be reduced, the impact ionization rate of carriers is reduced, the generation of carriers is reduced, and the occurrence of single event effect is inhibited. And the first diversion area 18 and the second diversion area 21 are matched, so that the super junction device structure can be ensured to have higher single particle resistance. The type and doping concentration of the buffer layer 31 are not limited.
It should be noted that:
the super junction device in this embodiment may be a PNP type. Namely, the first doping type column region 12, the first current leading region 18 and the second current leading region 21 (buried layer) are all P-type regions; the second doping type column region 14 is doped N-type. The charge flow directed at this time is the flow of holes.
The super junction device in this embodiment may also be an NPN type. Namely, the first doping type column region 12, the first current leading region 18 and the second current leading region 21 (buried layer) are all N-type regions; the second doping type column region 14 is P-type doped. The flow of the electric charges guided at this time is the flow of electrons.
Therefore, compared with the prior art, the super junction device structure and the device provided by the invention can be used for guiding the flow direction of charges by arranging the first current guiding region at the top position of the second doping type column region. And the first grid and the second grid are respectively isolated and positioned above the base regions of the two first doping type column regions, so that no grid is arranged above the first drainage region, a large amount of charges formed after high-energy heavy ions are driven into the second doping type column region can be drained by the first drainage region, and grid breakdown caused by charge accumulation below the grid is avoided. Therefore, the super junction device provided by the invention has the advantages that the single-particle-resistant gate penetration is realized, the problem of charge imbalance of the P column region and the N column region in the prior art is solved, and the dynamic characteristic of the super junction device is improved.
Referring to fig. 7, based on the same inventive concept, in another embodiment of the present invention, a super junction device 500 is further provided, where the super junction device 500 is composed of a plurality of super junction device structures 300. The method specifically comprises the following steps: two or more superjunction device structures as described in the above embodiments, a plurality of the superjunction device structures being arranged in a row, the first doping type column region 12 of each superjunction device structure being contiguous with another first doping type column region 12 of its neighboring superjunction device structure.
The superjunction device in this embodiment has the improved effects and advantages of the superjunction device structure in the above embodiments, and reference may be made to the superjunction device structure described above.
The superjunction device in this embodiment may be formed by the superjunction device structure in any of the embodiments described in the above embodiments, and is not limited.
In an embodiment of the present invention, a method for manufacturing a superjunction device structure is also provided, where the method may be used to manufacture the superjunction device structure and the superjunction device in the above embodiments, and the method includes: and etching the middle position of a complete grid electrode, and dividing the grid electrode into a first grid electrode and a second grid electrode. Other preparation steps can be carried out by adopting the existing mode and are not described in detail.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A superjunction device structure, comprising: the transistor comprises a substrate, a first doping type column region, a second doping type column region, a first grid, a second grid, a first drainage region and a second drainage region; the first doping type column region and the second doping type column region are arranged above the substrate, the second doping type column region is located between the two first doping type column regions, the first grid electrode and the second grid electrode are isolated and respectively arranged above base regions of the two first doping type column regions, and a first drainage region for guiding charge flow direction is arranged at the top end of the second doping type column region; the second diversion areas are arranged below the base areas of the two first doping type column areas; the width of each second diversion area is larger than that of the corresponding first grid or second grid.
2. The superjunction device structure of claim 1, wherein the first doping type column region is P-type doped and the first current guiding region is a P-type region.
3. The superjunction device structure of claim 1, wherein the first doping type column region is N-type doped and the first current guiding region is an N-type region.
4. The superjunction device structure of claim 1, wherein the first current guiding region is a trenched schottky contact.
5. The superjunction device structure of claim 1, wherein two of the second current guiding regions extend in directions approaching each other.
6. The superjunction device structure of claim 1, comprising a buffer layer between the substrate and the first and second doping type column regions.
7. A super junction device, comprising: two or more superjunction device structures of any of claims 1-6, a plurality of said superjunction device structures arranged in rows, the first doping type column region of each superjunction device structure interfacing with the first doping type column region of its adjacent superjunction device structure.
8. A method for manufacturing a super junction device structure, wherein for manufacturing the super junction device structure according to any one of claims 1 to 6, the middle position of a complete gate is etched to divide the gate into a first gate and a second gate.
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| CN112713195B (en) * | 2021-02-18 | 2022-08-02 | 厦门芯一代集成电路有限公司 | High-voltage VDMOS device and preparation method thereof |
| CN115332317A (en) * | 2022-10-13 | 2022-11-11 | 深圳平创半导体有限公司 | SBD-integrated silicon carbide planar MOSFET and manufacturing method thereof |
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