CN110603651B - 移除衬底的方法 - Google Patents

移除衬底的方法 Download PDF

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Publication number
CN110603651B
CN110603651B CN201880029662.8A CN201880029662A CN110603651B CN 110603651 B CN110603651 B CN 110603651B CN 201880029662 A CN201880029662 A CN 201880029662A CN 110603651 B CN110603651 B CN 110603651B
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substrate
semiconductor layers
group iii
iii nitride
nitride based
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CN110603651A (zh
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神川刚
S·甘德瑞蒂拉
李鸿渐
D·A·科昂
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University of California
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University of California
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Abstract

一种移除衬底的方法，其包括：在基于GaN的衬底上直接或间接地形成具有多个条带状开口区域的生长限制掩模；以及使用所述生长限制掩模在所述基于GaN的衬底上生长多个半导体层，使得所述生长在平行于所述生长限制掩模的所述条带状开口区域的方向上延伸，且在所述半导体层聚结之前停止生长，由此得到岛状半导体层。针对所述岛状半导体层中的每一者处理装置。执行蚀刻，直到暴露所述生长限制掩模的至少一部分。接着将所述装置结合到支撑衬底。通过至少部分地溶解所述生长限制掩模的湿式蚀刻技术从所述装置移除所述基于GaN的衬底。接着可回收所移除的所述GaN衬底。

Description

移除衬底的方法
相关申请案的交叉参考
本申请案依据35U.S.C.第119(e)部分主张以下同在申请中且共同让渡的申请案的权益：
由Takeshi Kamikawa、Srinivas Gandrothula、Hongjian Li和Daniel A.Cohen在2017年5月5日提交的第62/502,205号美国临时专利申请案，标题为“移除衬底的方法(METHOD OF REMOVING A SUBSTRATE)”，代理人档案号码为30794.653-US-P1(UC2017-621-1)；
所述申请案以引用的方式并入本文中。
技术领域
本发明涉及用于移除衬底的方法，所述方法包含从基于GaN的半导体层移除基于GaN的衬底。
背景技术
在由不同材料制成的低价衬底上获得同等价值的高价值半导体的工业价值极高。因此，研究和开发已经试图实现此目标很长时间。
在硅(Si)衬底上生长基于砷化镓(GaAs)的半导体薄膜以及在蓝宝石(Al2O3)衬底上生长基于氮化镓(GaN)的半导体薄膜尤其如此。在两种情况下，都可使用外延横向过生长(ELO)技术获得质量相对良好的半导体薄膜。
然而，使用由不同材料制成的衬底涉及数个问题。举例来说，由于不同的热膨胀常数，在高温下外延生长期间衬底可能弓曲或弯曲。
此外，衬底可能经受不均一的温度，这可能致使掺杂浓度、层的厚度、铟(In)的含量不均一。这种情况可能致使良率减小。
关于基于GaN的半导体，许多研究人员已尝试使用GaN衬底避免这些问题。然而，通常使用HVPE(氢化物气相外延)生产的GaN衬底非常昂贵。
举例来说，2英寸c平面极性GaN衬底的成本为约1000美元/晶片，而2英寸半极性GaN衬底的成本为约10000美元/晶片。因此，需要回收GaN衬底。
从例如蓝宝石衬底等不同材料的衬底移除GaN装置很容易。举例来说，GaN/蓝宝石界面处存在许多缺陷，这意味着界面处的结合强度弱。参见例如第2012/0280363A1号美国专利公开案。
然而，例如超声波移除等机械移除方法可能会损坏半导体层。对于需要光滑小面的边缘发射激光二极管(EELD)来说，这尤其是一个问题。使用机械移除方法时，可能会出现裂纹。举例来说，劈开装置时，损坏可能会导致非预期方向上的裂纹。有必要减少任何这种损坏。
此外，由于界面处的许多缺陷，GaN/蓝宝石界面吸收激光。因此，可使用激光烧蚀方法从半导体层移除衬底。
另一方面，为了获得高质量的基于GaN的半导体层且避免在外延生长期间衬底弓曲或弯曲，使用GaN衬底使得难以移除衬底，因为不存在例如与GaN/蓝宝石一样的异质界面。
一种常规技术是使用光电化学(PEC)蚀刻牺牲层以从GaN衬底移除装置结构，但这需要很长时间，且涉及若干复杂过程。此外，这些过程的良率尚未达到工业期望。
因此，在本领域中需要改善的移除衬底的方法，特别是在GaN衬底上生长GaN薄膜的情况下。本发明满足了此需要。
发明内容
为了克服上述现有技术中的限制，且克服在阅读和理解本说明书后将变得显而易见的其它限制，本发明公开一种用于移除衬底的方法，且具体地说，公开一种以容易的方式从基于GaN的半导体层移除基于GaN的衬底，以使得可回收基于GaN的衬底的方法。
附图说明
现参看图式，其中相同参考标号贯穿各图表示对应部件：
图1和2是根据本发明制造的装置结构的示意图。
图3(a)和3(b)说明生长限制掩模和生长限制掩模的开口区域。
图4(a)和4(b)说明生长限制掩模、生长限制掩模的开口区域、平坦表面区和层弯曲区。
图5(a)和5(b)说明在层弯曲区处的蚀刻。
图6(a)、6(b)和6(c)说明在层弯曲区以及外包覆区处的蚀刻。
图7是包含弯曲的有源区的装置结构的示意图。
图8是由岛状半导体层形成的装置结构的示意图。
图9是在基于GaN的衬底的表面下方已经进行干式蚀刻的装置结构的示意图。
图10是结合支撑衬底的示意图。
图11是通过湿式蚀刻溶解生长限制掩模的示意图。
图12是n电极沉积的示意图。
图13(a)和13(b)说明制造用于激光二极管装置的小面的方法以及芯片划线技术。
图14(a)和14(b)也说明制造用于激光二极管装置的小面的方法以及芯片划线技术。
图15是说明根据一个实施例的本发明的步骤和功能的流程图。
具体实施方式
在优选实施例的以下描述中，参考了可实践本发明的特定实施例。应理解，在不脱离本发明的范围的情况下，可利用其它实施例且可进行结构改变。
概述
大体来说，本发明描述一种用于制造基于GaN的半导体装置的方法，以使得可从基于GaN的半导体装置移除基于GaN的衬底，且回收基于GaN的衬底。这至少使用以下步骤实现：
1.外延横向过生长(ELO)、装置层的生长、p电极沉积和隆脊条带处理。
此步骤在图1中描述，其说明基于GaN的衬底101与其上形成的SiO2基生长限制掩模102。或者，如图2所示，可首先在基于GaN的衬底101上沉积基于GaN的中间层103，其中SiO2基生长限制掩模102形成于基于GaN的中间层103上。
生长限制掩模102被图案化成条带104，且在条带104之间包含用于基于GaN的层106的外延横向过生长的开口区域105。生长限制掩模102的条带104中的每一者具有约50μm的宽度，其中开口区域105中的每一者具有约5μm的宽度，其分隔开条带104中的邻近者。
ELO基于GaN的层106的生长首先发生在开口区域105中，在如图1所示的基于GaN的衬底101上或在如图2所示的基于GaN的中间层103上，且接着从生长限制掩模102的条带104上方的开口区域105横向地生长。在邻近开口区域105处的ELO基于GaN的层106可聚结在生长限制掩模102的顶部上之前，ELO基于GaN的层106的生长停止或中断。优选地，ELO基于GaN的层106在生长限制掩模102的条带104的侧翼区中具有约20μm的横向宽度。这种中断的生长导致在邻近ELO基于GaN的层106之间的无生长区107。
此后，在ELO基于GaN的层106上或上方生长半导体装置层108。在一个实施例中，半导体装置层108可包含AlGaN包层109、n-GaN引导层110、InGaN/GaN多量子阱((MQW)有源区111和p-GaN引导层112。在p-GaN引导层112上沉积透明导电氧化物(TCO)包层113，随后沉积电流限制层114。最终，p衬垫115沉积在TCO包层113上。
ELO基于GaN的层106与半导体装置层108的组合厚度可例如在1到20μm的范围内，但不限于这些值。从生长限制掩模102的表面到半导体装置层108的上部表面测量ELO基于GaN的层106与半导体装置层108的组合厚度。
半导体装置层108包含由蚀刻区117分隔开的一或多个平坦表面区116，所述蚀刻区在两侧上由在邻近于无生长区107的其边缘处的层弯曲区118限定。平坦表面区116的宽度优选为至少5μm，且更优选为10μm或更大。平坦表面区116中的半导体装置层108中的每一者的厚度具有高均一性。
由蚀刻区117和/或无生长区107分隔开的半导体装置层108称为岛状半导体层119。岛状半导体层119中的每一者可处理成单独装置。举例来说，可在岛状半导体层119中的每一者上进行隆脊条带处理，以形成单独的激光装置。
结合下文图3(a)-3(b)、4(a)-4(b)、5(a)-5(b)、6(a)-6(c)、7和8进一步展示且更详细地描述这些元件。
2.在基于GaN的衬底的表面下方的干式蚀刻。
此步骤在图9中描述。通过装置层108和ELO基于GaN的层106在蚀刻区117上执行干蚀刻，以暴露生长限制掩模102。此蚀刻导致形成岛状半导体层119，包含平坦表面区116和层弯曲区118，且起始将岛状半导体层119与基于GaN的衬底101分离的步骤。
只要暴露生长限制掩模102，就并不始终有必要蚀刻基于GaN的衬底101的表面。更优选地，执行蚀刻直到基于GaN的衬底101的表面，以使得可容易地移除基于GaN的衬底101。
3.结合支撑衬底。
此步骤在图10中展示。使用金属-金属结合或焊接技术，将岛状半导体层119倒装芯片结合到上面沉积有金属或焊料结合衬垫1002的支撑衬底1001。
4.通过湿式蚀刻溶解生长限制掩模。
此步骤在图11中展示。使用例如氢氟酸(HF)或缓冲氢氟酸(BHF)等化学溶液移除生长限制掩模102(图10中所示)的SiO2，此举从岛状半导体层119抬离基于GaN的衬底101。
5.N电极沉积。
此步骤在图12中展示。在抬离基于GaN的衬底101之后，在岛状半导体层119的背侧上沉积N电极1201。
6.芯片划线。
此步骤在图13(a)-13(b)和14(a)-14(b)展示。使用实线或虚线执行芯片划线。
下文更详细地描述本发明的这些和其它方面。
术语的定义
基于GaN的衬底
可使用从块状GaN晶体在{0001}、{1-100}、{11-20}、{20-21}、{20-2-1}、{11-22}平面或其它平面上切片的任何基于GaN的衬底101。基于GaN的衬底101可包含Al、In、B等。
基于GaN的半导体层
基于GaN的半导体层包含ELO基于GaN的层106、装置层108(例如AlGaN包层109、n-GaN引导层110、InGaN/GaN多量子阱(MQW)有源区111和p-GaN引导层112)以及中间层103。
这些基于GaN的半导体层可包含In、Al和/或B，以及其它掺杂剂和杂质，例如Mg、Si、Zn、O、C、H等。具体地说，基于GaN的半导体层可包括GaN层、AlGaN层、AlGaInN层、InGaN层等。
如上文所指出，装置层108(例如AlGaN包层109、n-GaN引导层110、InGaN/GaN多量子阱(MQW)有源区111和p-GaN引导层112)通常包含在n型层、未掺杂层与p型层之间的至少一层。
使用基于GaN的半导体层，所得装置可包括例如发光二极管(LED)、激光二极管(LD)、肖特基势垒二极管(SBD)、光电二极管、金属-氧化物-半导体场效应晶体管(MOSFET)等，但不限于这些装置。本发明特别适用于微型LED和激光二极管，例如边缘发射激光器和垂直腔表面发射激光器(VCSEL)。
生长限制掩模
生长限制掩模102包括介电层，例如SiO2、SiN、SiON、Al2O3、AlN、AlON或耐火金属，例如W、Mo、Ta、Nb等。生长限制掩模102可为层压体或选自上述材料的堆叠层结构。
在一个实施例中，生长限制掩模102的厚度为约0.05-3μm。生长限制掩模102的条带104中的每一者的宽度优选大于20μm，更优选大于40μm，且最优选为约50μm。
如上文所指出，生长限制掩模102被图案化成条带104，且在条带104之间包含开口区域105。在如图3(a)所示的一个实施例中，开口区域105的条带具有长度a和宽度b。开口区域105中的每一者的长度a在平行于(0001)c平面定向的基于GaN的衬底101的1-100方向的第一方向上，且开口区域105中的每一者的宽度b在平行于(0001)c平面定向的基于GaN的衬底101的11-20方向的第二方向上，周期性地以第一间隔p1在第二方向上延伸。开口区域105中的每一者的宽度b通常是恒定的，但可根据需要改变。生长限制掩模102的条带104中的每一者的宽度L是L＝p1-b。
在图3(b)所示的另一实施例中，开口区域105中的每一者的长度和宽度在与图3(a)类似的方向上布置，但长度a可不同，且邻近的开口区域105在第一方向上偏移第二间隔p2，且在第二方向上移位第一间隔p1的一半，其方式使得邻近开口区域105的末端部分在第一方向上纵向重叠预定距离q。此布置防止了开口区域105的两个末端部分在基于GaN的衬底101的1-100方向上凸起。
在这两个实施例中，间隔p1可为约5到120μm；间隔p2可为约500到1050μm；长度a可为约200到2000μm；宽度b可为约2到20μm；且距离q可为约35到40μm。在图3(a)中，举例来说，间隔p1可为55μm；间隔p2可为约810μm；长度a可为约1200μm；宽度b可为约5μm；且宽度L为50μm。
ELO基于GaN的层
图4(a)和4(b)说明分别使用图3(a)和3(b)的生长限制掩模102生长的ELO基于GaN的层106。
使用生长限制掩模102，通过气相沉积方法，例如金属有机化学气相沉积(MOCVD)方法，以(0001)平面定向的岛状形状生长ELO基于GaN的层106。
基于GaN的衬底101或基于GaN的中间层103的表面在生长限制掩模102的开口区域105中暴露，且ELO基于GaN的层106选择性地在其上在相对于生长限制掩模102的垂直和横向方向两者上连续生长。在ELO基于GaN的层106与生长限制掩模102上的邻近ELO基于GaN的层106聚结之前，停止生长。
对于基于GaN的半导体的(0001)平面生长，平行于所述平面的横向生长速率在11-20方向上最大，而在1-100方向上最小。在图3(a)和3(b)中所示的生长限制掩模102中，由于开口区域105的纵向方向是1-100方向，因此基于GaN的半导体的生长速率在开口区域105的两个末端处较小，在1-100方向上彼此相对的ELO基于GaN的层106不会聚结且保持彼此分离。ELO基于GaN的层106在1-100方向上的长度几乎等于开口区域105的长度a。
ELO基于GaN的层106的厚度很重要，因为其决定了平坦表面区116的宽度。优选地，平坦表面区116的宽度为20μm或更大。ELO基于GaN的层106的厚度优选地尽可能地薄，以减少处理时间且便于蚀刻开口区域105。
ELO基于GaN的层106的生长率是平行于基于GaN的衬底101的11-20轴的横向方向的生长速率与平行于基于GaN的衬底101的0001轴的垂直方向的生长速率的比率。优选地，ELO基于GaN的层106的生长率高，其中通过优化生长条件，可将ELO基于GaN的层106的生长率控制在1到4。
在ELO基于GaN的层106的比率为4的情况下，ELO基于GaN的层106的厚度仅为约5μm，但获得的平坦表面区116的宽度为20μm。在此情况下，蚀刻开口区域105非常容易。
为了获得ELO基于GaN的层106的高比率，ELO基于GaN的层106的生长温度优选地高于约950℃，且MOCVD腔室中的压力优选地低于约100托。而且，为了促进Ga原子的迁移，V/III比优选为高的。
当具有最低生长速率的相对平面上的ELO基于GaN的层106之间的距离大时，出现以下缺点。在生长限制掩模102的在ELO基于GaN的层106之间的区处的掩膜部分(其在1-100方向上生长速率最低)中，未消耗原始气体，且因此气体浓度增大，且产生在1-100方向上的浓度梯度，且通过根据所述浓度梯度进行扩散，在ELO基于GaN的层106的1-100方向上的边缘部分处供应大量气体。结果，与其它部分相比，ELO基于GaN的层106的在1-100方向上的边缘部分的厚度增大，且导致凸起的形状。凸起的形状不仅在装置中造成结构上的不便，而且在随后的光刻等制造过程中产生问题。
为了防止凸起的形状，ELO基于GaN的层106尽可能靠近，且因此有必要从生长开始就不产生原料气体的平面内均一性。在图3(b)中所示的生长限制掩模102中，形成有在11-20方向上彼此邻近的开口区域105，其形成方式为使得开口区域105在相对末端部分处重叠达长度q。
结果，通过由于生长ELO基于GaN的层106而引起的原始气体的消耗来获得气体浓度的平面内均一性。最终，这导致岛状半导体层119的厚度均一性。
开口区域的蚀刻
图5(a)至6(c)说明开口区域105的蚀刻过程的细节。
图5(a)展示基于图3(a)的生长限制掩模102的无生长区107、ELO基于GaN的层106、平坦表面区116、层弯曲区118和蚀刻区117，且图5(b)展示ELO基于GaN的层106和蚀刻区117，其中已执行蚀刻501以移除层弯曲区118(未展示)。
图6(a)展示基于图3(b)的生长限制掩模102的开口区域105、无生长区107、ELO基于GaN的层106、平坦表面区116和层弯曲区118，且图6(b)展示开口区域105和ELO基于GaN的层106，其中已执行蚀刻501以移除层弯曲区118(未展示)。
如图6(a)中的601和602所示，蚀刻501可大于开口区域105。在此实例中，岛状半导体层119不具有与基于GaN的衬底101和其它岛状半导体层119的界面。在蚀刻区域较宽的情况下，可快速且容易地从基于GaN的衬底101移除岛状半导体层119。
如果岛状半导体层119与基于GaN的衬底101之间的界面至少部分地保留，则确实提供一些益处。举例来说，图6(c)展示岛状半导体层119与基于GaN的衬底101之间的界面保留在开口区域105的两个边缘处的情况。在此情况下，容易在干式刻蚀之后固持岛状半导体层119。然而，最好使剩余区域尽可能小。在干式蚀刻之后，在生长限制掩模102上的岛状半导体层119可滑动且易于移除。
蚀刻区
图5(a)至6(c)还说明蚀刻区117的细节。
蚀刻区117是通过干式蚀刻和/或湿式蚀刻加以蚀刻以暴露生长限制掩模102的位置。如图5(a)和5(b)中所示，蚀刻区117主要在开口区域105上。然而，在图6(a)和6(c)中，存在外包覆生长限制掩模102(未展示)的第一方向的蚀刻区601和/或外包覆生长区域掩模的第二方向的蚀刻区602。这是为了暴露生长限制掩模102。
在第一方向上，外包覆宽度通常在约0与10μm之间的范围内，且更优选在约1与6μm之间的范围内，因为保持了高的处理良率。第二方向几乎是相同的值。然而，外包覆宽度可不同而不会引起任何问题。
蚀刻区117可比开口区域105宽，以使得在岛状半导体层119与基于GaN的衬底101之间的界面处不存在其它任何东西。这使得基于GaN的衬底101易于从岛状半导体层119移除。
层弯曲区
图7结合生长限制掩模102、开口区域105、平坦表面区116和蚀刻区117说明层弯曲区118的细节。
在一个实施例中，可通过蚀刻移除或不移除层弯曲层118。举例来说，可同时执行蚀刻区117和层弯曲区118两者的蚀刻，以便减少处理时间和成本。
如图7中所示，层弯曲区118可包含弯曲的有源区701。如果不通过蚀刻移除层弯曲层118，且弯曲的有源区701保留在装置中，则从有源区111发射的光的一部分被重新吸收。结果，可能优选的是移除层弯曲区118。
此外，如果装置是激光二极管，且未通过蚀刻移除层弯曲层118，以使得弯曲的有源区701保留在装置中，则激光模式可能会由于弯曲的有源区701中的低折射率(例如，InGaN层)而受到层弯曲区118和弯曲的有源区701的影响。结果，可能优选的是移除层弯曲区118和弯曲的有源区701。
岛状半导体层
图8是岛状半导体层119的截面图，所述岛状半导体层在此实例中包括激光二极管。
具体地说，III族氮化物半导体激光二极管由以下层组成(这些层以所提及的次序一层一层地层叠在上面)：1.3μm的n-Al0.06GaN包层109、0.4μm的n-GaN引导层110、InGaN/GaN MQW有源区111、p-GaN引导层112、TCO包层113、电流限制层114和p电极115。请注意，在此实例中，存在位于InGaN/GaN MQW有源区111与p-GaN引导层112之间的任选AlGaN电子阻挡层(EBL)801。
图8的截面图展示沿着垂直于光学谐振器的方向的激光棒，其包括隆脊条带结构。所述隆脊条带结构包括TCO包层113、电流限制层114和p电极115，且在水平方向上提供光学限制。所述隆脊条带结构的宽度为约1.0到20μm，且通常为5μm。
在一个实施例中，p电极115可包括以下材料中的一或多者：Pd、Ni、Ti、Pt、Mo、W、Ag、Au等。举例来说，p电极可包括Pd-Ag-Ni-Au(厚度为3-50-30-300nm)。这些材料可通过电子束蒸镀、溅镀、热蒸镀等进行沉积。此外，p电极通常沉积在TCO包层113上。
蚀刻区
图9展示蚀刻区117的深度，其至少在生长限制掩模102的表面下方且在此实例中延伸到基于GaN的衬底101中。在此情况下，容易使用湿式蚀刻方法移除生长限制掩模102。
支撑衬底
图10说明支撑衬底1001，其使用经图案化的结合衬垫1002个别地结合到岛状半导体层119。可使用常规的结合技术。
支撑衬底1001可包括元素半导体、化合物半导体、金属、合金、基于氮化物的陶瓷、基于氧化物的陶瓷、金刚石、碳、塑料等，且可包括单层结构或由这些材料制成的多层结构。例如焊料等的金属或有机粘结剂可用于经图案化的结合衬垫1002，且根据需要选择。
一般来说，最常见类型的倒装芯片结合是热压结合和晶片熔融/结合。晶片熔融已广泛用于基于InP的装置中。然而，热压结合通常比晶片熔融简单得多，因为其使用金属到金属结合，且具有还极大地提高导热率的益处。
迄今为止，Au-Au压缩结合是最简单的结合，且会导致相当牢固的结合。Au-Sn共晶结合提供大得多的结合强度。
在一个实施例中，Cu衬底1001用作支撑衬底。通过电子束蒸镀或溅镀在Cu衬底1001上制造经图案化的Ti/Au结合衬垫1002。在一个实例中，结合衬垫1002包括Ti(10nm)和Au(500nm)。
岛状半导体层119的暴露表面的活化可在压缩结合之前执行。使用Ar和/或O2的等离子体过程实现活化。
此后，在约150-300℃下在压力下，将岛状半导体层119结合到支撑衬底1001的结合衬垫1002。
移除衬底
存在两种技术可用于从岛状半导体层119移除基于GaN的衬底101。
一种技术是仅使用支撑衬底1001。生长限制掩模102与ELO基于GaN的层106之间的界面具有弱的结合强度。因此，易于使用支撑衬底1001从基于GaN的衬底101剥离岛状半导体层119。
另一技术是在移除基于GaN的衬底101之前，使用氢氟酸(HF)、缓冲HF(BHF)或其它蚀刻剂来蚀刻生长限制掩模102，以至少部分地溶解生长限制掩模102。此技术要求蚀刻开口区域105和/或蚀刻区117，直到暴露出生长限制掩模102为止。一旦暴露出生长限制掩模102，湿式蚀刻可部分或完全溶解生长限制掩模102，且接着可从岛状半导体层119移除基于GaN的衬底101。此在图11中加以说明。
具体地说，在已将支撑衬底1001结合到岛状半导体层119之后，将整个结构浸入用于湿式蚀刻的溶剂中以溶解生长限制掩模102。在一个实施例中，如图10中所示，生长限制掩模102是SiO2，其被HF或BHF溶剂溶解。此技术的优点在于非常容易且快速地用HF溶解大面积的SiO2，且当从岛状半导体层119(非常温和地)移除基于GaN的衬底101时，不存在机械损伤。
接着可回收图11中所示的所移除的基于GaN的衬底101。举例来说，可通过抛光机重新抛光基于GaN的衬底101的表面。回收过程可重复进行，从而降低制造基于GaN的半导体装置的成本。
第一支撑衬底和第二支撑衬底
在另一实例中，第一支撑衬底和第二支撑衬底可用于从岛状半导体层119移除基于GaN的衬底101。此方法包括以下步骤：在从岛状半导体层119移除基于GaN的衬底101之前或之后，将第一支撑衬底1001结合到岛状半导体层119的暴露表面，且将第二支撑衬底(未展示)结合到基于GaN的衬底101的暴露表面。通常，稍后可通过使用适当的蚀刻剂将低温熔融金属和/或焊料结合层溶解在所结合的第二支撑衬底与基于GaN的衬底101之间来移除结合到基于GaN的衬底101的第二支撑衬底。
N电极
图12说明n电极1201在岛状半导体层119的背侧上的沉积，其在移除基于GaN的衬底101之后暴露。
通常，n电极1201可包括以下材料：Ti、Hf、Cr、Al、Mo、W、Au等。举例来说，n电极1201可包括Ti-Al-Pt-Au(厚度为30-100-30-500nm)，但不限于那些材料。这些材料的沉积可通过电子束蒸镀、溅镀、热蒸镀等执行。
小面
图13(a)-13(b)和14(a)-14(b)说明用于激光二极管装置的小面的制造方法。
图13(a)展示基于图3(a)的生长限制掩模102的无生长区107、ELO基于GaN的层106和蚀刻区117。图13(b)是图13(a)的带圆圈部分的放大图，且展示在图13(a)中的ELO基于GaN的层106上的隆脊条带结构1301、经蚀刻镜区1302和芯片划线1303。经蚀刻镜区1302基于光学谐振长度而定位，芯片划线1303也是如此。
图14(a)展示结合到支撑衬底1001的岛状半导体层119。图14(b)是图14(a)的带圆圈部分的放大图，且展示在图14(a)中的岛状半导体层119上的隆脊条带结构1301、经蚀刻镜区1302和芯片划线1303。经蚀刻镜区1302基于光学谐振长度而定位，芯片划线1303也是如此。
用于GaN蚀刻的蚀刻过程使用Ar离子束和Cl2周围气体。蚀刻深度为约1μm到约4μm。蚀刻的镜小面可由选自以下的群组的介电膜涂布：SiO2、Al2O3、AlN、AlON、SiN、SiON、TiO2、Ta2O5、Nb2O5、Zr2O等。
芯片划分
图13(a)-13(b)和14(a)-14(b)还说明芯片划分方法。
芯片划分方法具有两个步骤。第一步骤是对岛状半导体层119划线。第二步骤是使用激光划刻等划分支撑衬底1001。
如图13(b)和14(b)两者中所示，芯片划线1303通过金刚石划线机或激光划线机制造。芯片划线1303被制造在岛状半导体层119的背侧上。芯片划线1303可为实线或虚线。
接下来，也通过激光划线来划分支撑衬底1001以获得激光二极管装置。在制造芯片划线1303时最好避开隆脊条带结构1301。
处理步骤
图15是说明根据本发明的一个实施例的在从基于GaN的半导体层形成装置之后从基于GaN的半导体层移除基于GaN的衬底以使得可回收基于GaN的衬底的方法的流程图。
框1501表示提供基底衬底101的步骤。在一个实施例中，基底衬底101是基于III族氮化物的衬底101，例如基于GaN的衬底101。
框1502表示在衬底101上沉积中间层103的任选步骤。在一个实施例中，中间层103是基于III族氮化物的层103，例如基于GaN的层103。
框1503表示在衬底101上或上方，即在衬底101本身上或在中间层103上，形成生长限制掩模102的步骤。生长限制掩模102经图案化以包含多个条带104和开口区域105。
框1504表示使用外延横向过生长(ELO)在生长限制掩模102上或上方生长一或多个半导体层106的步骤，其中半导体层106的外延横向生长在平行于生长限制掩模102的开口区域105的方向上延伸，且在半导体层106在条带104上聚结之前停止外延横向过生长。在一个实施例中，ELO层106是ELO基于III族氮化物的层106，例如ELO基于GaN的层106。
框1505表示在ELO层106上生长一或多个半导体装置层108的步骤。这些装置层108与ELO层106一起形成岛状半导体层119中的一或多者。
框1506表示以下步骤：在蚀刻区117中蚀刻半导体装置层108的至少一部分，以移除半导体装置层108的蚀刻部分且暴露生长限制掩模102的至少一部分。蚀刻可包含蚀刻装置层108的在生长限制掩模102的开口区域105上方的至少一部分，且可在衬底101的表面下方继续。蚀刻还可包含从半导体装置层108移除层弯曲区118。
框1507表示将岛状半导体层119结合到支撑衬底1001的步骤。通过使用金属-金属结合或焊接技术将岛状半导体层119倒装芯片结合到上面沈积有金属或焊料1002的支撑衬底1001。
框1508表示通过蚀刻至少部分地溶解生长限制掩模102以从岛状半导体层119移除衬底101的步骤。通过蚀刻至少部分地移除生长限制掩模102，其将衬底101从岛状半导体层119抬离。另外，可从衬底101剥离岛状半导体层119。
框1509表示在岛状半导体层119的背侧上沉积n电极的步骤，所述岛状半导体层的背侧通过衬底101的抬离而暴露。
框1510表示芯片划线以分离装置的步骤。此步骤还可包含蚀刻用于激光二极管装置的小面。
框1511表示所述方法的所得产品，即根据此方法制造的一或多个基于III族氮化物的半导体装置，以及已从装置移除且可用于回收和重新使用的衬底101。
优点和益处
本发明提供数个优点和益处：
·从装置层108移除衬底101之后，可重新使用昂贵的基于III族氮化物的衬底101。
·可使用具有非常低缺陷密度的相同或类似材料的衬底101获得高质量的装置层108。
·对于衬底101和装置层108两者使用相同或类似材料可减少装置层108中的应变。
·对于衬底101和装置层108两者使用具有相同或类似热膨胀的材料可减少衬底101在外延生长期间的弯曲。
·从具有错误切割定向的块状晶体切出衬底101维持装置层108之间的厚度均一性且产生较高良率。
·通过ELO生长的层106具有高质量。
·ELO层106彼此不聚结，且释放了内部应变，这有助于避免裂纹的任何出现。对于为AlGaN层的装置层108，这是非常有用的，特别是在高Al含量层的情况下。
·岛状半导体层119是隔离形成的，因此拉伸应力或压缩应力不会落在其它岛状半导体层119上。
·而且，生长限制掩模102与ELO层106不会化学结合，因此可通过在生长限制掩模102与ELO层106之间的界面处引起的滑动来舒缓ELO层106和装置层108中的应力。
·岛状半导体层119中的每一者之间的无生长区107的存在提供了灵活性，且当施加外力时衬底101容易变形且可弯曲。因此，即使在衬底101中发生轻微的翘曲、弯曲或变形，也可通过小的外力容易地对其进行校正，以避免出现裂纹。结果，可通过真空吸持来处置衬底101，这使得半导体装置的制造过程更容易进行。
·无生长区107使得易于溶解大面积的生长限制掩模102。
·可通过抑制衬底101的弯曲来生长高质量半导体晶体的装置层108，且另外，即使当装置层108非常厚时，也可抑制裂纹等的发生，且由此可容易地实现大面积半导体装置。
·由于在支撑衬底上的倒装芯片结合，装置的热管理得到显著改善。
·与市售装置相比时，芯片大小减小了约10倍。
·制造方法也可容易地用于大大小晶片(>2英寸)。
修改和替代
可在不脱离本发明的范围的情况下进行数个修改和替代。
具体地说，基于III族氮化物的衬底可为基底c平面{0001}、非极性a平面{11-20}和m平面{10-10}系列以及具有至少两个非零的h、i或k米勒指数和非零的l米勒指数的半半极性平面系列，例如{20-2-1}平面。(20-2-1)的半极性衬底特别有用，因为平坦的ELO生长区域大，而用蓝宝石衬底很难获得。
结论
至此，结束了对本发明的优选实施例的描述。出于说明和描述的目的，已呈现本发明的一或多个实施例的前述描述。其并不意欲为穷尽性的或将本发明限于所公开的精确形式。鉴于上述教导，许多修改和变化是可能的。希望本发明的范围不受此详细描述限制，而是由所附权利要求限制。

Claims (16)

1.一种移除衬底的方法，其包括：
在衬底上或上方形成生长限制掩模，其中所述生长限制掩模由开口区域组成；
首先在所述衬底上或上方的所述开口区域中生长一或多个基于III族氮化物的半导体层，随后从所述生长限制掩模中的所述开口区域横向地生长，其中在所述开口区域的邻近一者处的所述一或多个基于III族氮化物的半导体层聚结在所述生长限制掩模的顶部上之前，停止或中断所述一或多个基于III族氮化物的半导体层的生长；
移除在所述生长限制掩模中的所述开口区域的一或多个上或上方的所述一或多个基于III族氮化物的半导体层的一部分，借此从所述衬底上或上方的所述一或多个基于III族氮化物的半导体层形成一个或多个岛状半导体层；以及
从所述一或多个基于III族氮化物的半导体层移除所述衬底。
2.根据权利要求1所述的方法，其中所述一或多个基于III族氮化物的半导体层中的每一者经过处理以形成装置。
3.根据权利要求1所述的方法，其中生长限制掩模包括条带，且每一所述开口区域布置在每两条所述条带之间。
4.根据权利要求1所述的方法，其中通过外延横向过生长(ELO)来生长所述一或多个基于III族氮化物的半导体层。
5.根据权利要求4所述的方法，其中在所述一或多个基于III族氮化物的半导体层中的聚结之前，停止所述外延横向过生长。
6.根据权利要求1所述的方法，其中所述移除所述衬底包括将所述一或多个基于III族氮化物的半导体层与所述衬底完全分离。
7.根据权利要求1所述的方法，其中所述衬底是基于III族氮化物的衬底。
8.根据权利要求1所述的方法，其还包括从所述一或多个基于III族氮化物的半导体层移除层弯曲区。
9.根据权利要求2所述的方法，其中移除所述衬底包括使用支撑衬底来移除所述衬底。
10.根据权利要求9所述的方法，其中所述支撑衬底被划分以分隔开所述装置。
11.根据权利要求1所述的方法，其中在所述移除所述衬底之后，可回收所述衬底。
12.根据权利要求1所述的方法，其中所述移除所述一或多个基于III族氮化物的半导体层的所述一部分包括蚀刻接触所述一或多个基于III族氮化物的半导体层的所述一部分的所述生长限制掩模的部分。
13.根据权利要求1所述的方法，其中所述一个或多个岛状半导体层具有均匀的厚度。
14.根据权利要求1所述的方法，其中所述一或多个基于III族氮化物的半导体层包含一或多个外延横向过生长(ELO)基于III族氮化物层和装置层；以及
层弯曲区，其包括所述一或多个基于III族氮化物的半导体层的经弯曲有源区，且所述经弯曲有源区从所述一或多个基于III族氮化物的半导体层移除。
15.根据权利要求1所述的方法，其进一步包括将所述一或多个岛状半导体层结合到支撑衬底，且移除所述衬底进一步包括使用所述支撑衬底从所述一或多个基于III族氮化物的半导体层移除所述衬底。
16.一种移除衬底的方法，其包括：
提供一或多个基于III族氮化物的半导体层包括：
衬底；以及
生长限制掩模，其在所述衬底上或上方，其中所述生长限制掩模由开口区域组成；以及
一或多个基于III族氮化物的半导体层，其在所述开口区域中以及在所述衬底上或上方，其中所述一或多个基于III族氮化物的半导体层与邻近一者分隔开；
移除在所述生长限制掩模中的开口区域的一或多个上或上方的所述一或多个基于III族氮化物的半导体层的一部分，借此从所述衬底上或上方的所述一或多个基于III族氮化物的半导体层形成一个或多个岛状半导体层；以及
从所述一或多个基于III族氮化物的半导体层移除所述衬底。
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