CN110534145B - 感测电路和包括其的半导体器件 - Google Patents
感测电路和包括其的半导体器件 Download PDFInfo
- Publication number
- CN110534145B CN110534145B CN201811495676.7A CN201811495676A CN110534145B CN 110534145 B CN110534145 B CN 110534145B CN 201811495676 A CN201811495676 A CN 201811495676A CN 110534145 B CN110534145 B CN 110534145B
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- CN
- China
- Prior art keywords
- line
- sense
- signal
- circuit
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020180058434A KR102471418B1 (ko) | 2018-05-23 | 2018-05-23 | 센싱 회로 및 이를 포함하는 반도체 장치 |
KR10-2018-0058434 | 2018-05-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110534145A CN110534145A (zh) | 2019-12-03 |
CN110534145B true CN110534145B (zh) | 2023-06-30 |
Family
ID=68613488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811495676.7A Active CN110534145B (zh) | 2018-05-23 | 2018-12-07 | 感测电路和包括其的半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10643687B2 (ko) |
KR (1) | KR102471418B1 (ko) |
CN (1) | CN110534145B (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200068942A (ko) * | 2018-12-06 | 2020-06-16 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 동작 방법 |
KR102634614B1 (ko) * | 2019-07-12 | 2024-02-08 | 에스케이하이닉스 주식회사 | 수직형 메모리 장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5608668A (en) * | 1995-12-22 | 1997-03-04 | Micron Technology, Inc. | Dram wtih open digit lines and array edge reference sensing |
CA2217359A1 (en) * | 1997-09-30 | 1999-03-30 | Mosaid Technologies Incorporated | Method for multilevel dram sensing |
US6301175B1 (en) * | 2000-07-26 | 2001-10-09 | Micron Technology, Inc. | Memory device with single-ended sensing and low voltage pre-charge |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100261217B1 (ko) * | 1997-11-21 | 2000-07-01 | 윤종용 | 반도체 메모리장치의 셀 어레이 제어장치 |
KR100393224B1 (ko) * | 2001-06-30 | 2003-07-31 | 삼성전자주식회사 | 비트라인 쌍들의 부하를 차단하는 회로를 구비하는 반도체메모리장치 |
KR100410988B1 (ko) * | 2001-11-15 | 2003-12-18 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 비트 라인 센싱 방법 |
US6590819B1 (en) * | 2002-03-14 | 2003-07-08 | Micron Technology, Inc. | Digit line equilibration using time-multiplexed isolation |
KR20100036596A (ko) | 2008-09-30 | 2010-04-08 | 삼성전자주식회사 | 에지 더미 셀들을 제거한 오픈 비트라인 구조의 반도체 메모리 장치 |
KR102070977B1 (ko) | 2013-08-01 | 2020-01-29 | 삼성전자주식회사 | 감지 증폭기 및 그것을 포함하는 메모리 장치 |
KR102562312B1 (ko) * | 2016-08-24 | 2023-08-01 | 삼성전자주식회사 | 비트라인 센스 앰프 |
-
2018
- 2018-05-23 KR KR1020180058434A patent/KR102471418B1/ko active IP Right Grant
- 2018-11-30 US US16/206,601 patent/US10643687B2/en active Active
- 2018-12-07 CN CN201811495676.7A patent/CN110534145B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5608668A (en) * | 1995-12-22 | 1997-03-04 | Micron Technology, Inc. | Dram wtih open digit lines and array edge reference sensing |
CA2217359A1 (en) * | 1997-09-30 | 1999-03-30 | Mosaid Technologies Incorporated | Method for multilevel dram sensing |
US6301175B1 (en) * | 2000-07-26 | 2001-10-09 | Micron Technology, Inc. | Memory device with single-ended sensing and low voltage pre-charge |
Also Published As
Publication number | Publication date |
---|---|
KR20190133461A (ko) | 2019-12-03 |
US10643687B2 (en) | 2020-05-05 |
CN110534145A (zh) | 2019-12-03 |
KR102471418B1 (ko) | 2022-11-29 |
US20190362767A1 (en) | 2019-11-28 |
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