CN110504300B - Insulated gate transistor and preparation method and application thereof - Google Patents
Insulated gate transistor and preparation method and application thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title description 5
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims description 37
- 150000002500 ions Chemical class 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 11
- 238000001465 metallisation Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 23
- 238000002347 injection Methods 0.000 abstract description 16
- 239000007924 injection Substances 0.000 abstract description 16
- 230000002441 reversible effect Effects 0.000 abstract description 10
- 230000003068 static effect Effects 0.000 abstract description 8
- 230000002829 reductive effect Effects 0.000 abstract description 7
- 238000009827 uniform distribution Methods 0.000 abstract description 7
- 239000002131 composite material Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 90
- 230000008569 process Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 230000007774 longterm Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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Abstract
The invention provides an insulated gate transistor and a manufacturing method and application thereof. The insulated gate transistor includes: a drift region; the P well region is arranged on one side of the drift region; the active region is arranged on one side, far away from the drift region, of the P well region; the grid is arranged on one side, far away from the drift region, of the P well region; the emitter is arranged on one side, far away from the drift region, of the active region and the P well region; the buffer layer is arranged on one side of the drift region far away from the grid electrode; the collector region is arranged on one side of the buffer layer, which is far away from the drift region; the collector is arranged on one side, far away from the drift region, of the collector region; wherein the collector region is composed of a plurality of P + Ion-doped first layer and plurality of P ‑ The ion-doped second layers are alternately stacked. The invention provides an insulated gate transistor, the collector region of which is P + /P ‑ The composite structure layer is formed, so that the injection efficiency of minority carriers is optimized, the risk of damage to a device caused by turn-off loss and reverse current is reduced, the uniform distribution of carrier concentration in a drift region is facilitated, and the dynamic loss and the static loss are optimized.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an insulated gate transistor and a manufacturing method and application thereof. More particularly, the present invention relates to an insulated gate transistor, a method of manufacturing the same, an intelligent power module, and an air conditioner.
Background
The Insulated Gate Bipolar Transistor (IGBT) has the current capability of a Bipolar Junction Transistor (BJT) and the voltage control characteristic of an insulated gate field effect transistor (MOSFET), and is a high-current and high-power switching device. Structurally comprising a gate (G), an emitter (E), a collector (C) and a drift region (N) - ) And a back side collector region (P) + ) The operating principle is that after the grid reaches the threshold voltage, the channel is conducted, the collector region injects minority carriers to the drift region to play a role in conductivity modulation, and the conduction loss is smaller when the minority carriers are injected more. But correspond toThe larger the tail current effect, the larger the turn-off losses, and thus the injection of minority carriers is related to the turn-on and turn-off losses of the device. Meanwhile, the two also have a contradiction relationship, and at present, a compromise relationship of conduction loss and turn-off loss is optimized by adopting a method for controlling the lifetime of minority carriers in a local region of a collector region or reducing the injection efficiency of the minority carriers.
Disclosure of Invention
The present invention has been completed based on the following findings of the inventors:
during research, the inventor of the present invention found that, in order to shorten the lifetime of minority carriers or reduce the injection efficiency of minority carriers, a local defect region is usually introduced in the collector region, or isolated N of different conductivity types is introduced in the collector region + The method is characterized in that a collector region short circuit structure is arranged in a region, and the region with different local conduction types or inconsistent material properties is introduced into the collector region below a drift region, so that large concentration nonuniformity exists in the transverse horizontal concentration distribution of a cellular drift region after minority carriers are injected into the drift region. However, in an actual application process, the non-uniform carrier concentration distribution in the IGBT drift region also increases the conduction loss of the device, and on the contrary, the non-uniform carrier concentration distribution has a great influence on the performance of the device.
Therefore, the inventor designs a new P + /P - The collector region formed by the composite structure layer can optimize injection efficiency of minority carriers, so that extraction speed of the minority carriers is increased during turn-off, turn-off speed is increased, current tailing effect is reduced, turn-off loss and risk of damage of reverse current to devices are reduced, and in addition, uniform distribution of carrier concentration in a drift region is facilitated, so that the insulated gate transistor has more optimized dynamic and static loss.
In a first aspect of the invention, an insulated gate transistor is presented.
According to an embodiment of the invention, the insulated gate transistor comprises: a drift region; the P well region is arranged on one side of the drift region; the active region is arranged on one side, far away from the drift region, of the P well region; a gate disposed in the P well region and away from the P well regionOne side of the drift region; the emitter is arranged on one side, far away from the drift region, of the active region and the P well region; the buffer layer is arranged on one side, far away from the grid electrode, of the drift region; the collector region is arranged on one side, far away from the drift region, of the buffer layer; the collector electrode is arranged on one side, far away from the drift region, of the collector region; the collector region is formed by alternately stacking a plurality of first layers and a plurality of second layers, and the first layers are P + Ion doping, the second layer is P - And (5) ion doping.
The inventor discovers through research that the collector region of the insulated gate transistor of the embodiment of the invention is P + /P - The composite structure layer is formed, so that the injection efficiency of minority carriers can be optimized, the risk of the turn-off loss and the damage of reverse current to a device is reduced, the uniform distribution of the carrier concentration in a drift region is facilitated, and the dynamic loss and the static loss are optimized.
In addition, the insulated gate transistor according to the above embodiment of the present invention may further have the following additional technical features:
according to an embodiment of the invention, the thickness of the first layer is 120-150 nm.
According to an embodiment of the invention, the thickness of the second layer is 80-100 nm.
According to an embodiment of the present invention, the number of the first layer and the second layer is 2 to 4 each.
According to an embodiment of the present invention, P of the first layer + Ion doping concentration of 5 × 10 18 ～1×10 19 cm -3 (ii) a And/or P of said second layer - The ion doping concentration is 1 x 10 17 ～5×10 17 cm -3 。
In a second aspect of the invention, a method of making an insulated gate transistor is presented.
According to an embodiment of the invention, the method comprises: performing P ion implantation on one surface of the N-ion doped substrate to form a P well region and a drift region; to instituteThe P well region is far away from the surface of the drift region for carrying out N + Ion implantation is carried out to form an active region; performing metal deposition on the surfaces of the active region, the P well region and the drift region to form a grid electrode and an emitter electrode; conducting N on the surface of the drift region far away from the grid electrode + Ion implantation to form a buffer layer; p ion implantation is carried out on the surface of the buffer layer far away from the drift region to form a collector region, the collector region is formed by sequentially and alternately stacking a plurality of first layers and a plurality of second layers, and the first layers are P + Ion doping, the second layer is P - Ion doping; and performing metal deposition on the surface of the collector region far away from the drift region to form a collector electrode.
The inventors have found through research that by using the preparation method of the embodiment of the present invention, P can be formed by adjusting the dose or implantation energy of P ion implantation + /P - And the collector region of the alternating laminated structure is compounded, so that the insulated gate transistor with lower turn-off loss, lower risk of damage of reverse current to a device and more optimized dynamic loss and static loss can be prepared.
In addition, the preparation method according to the above embodiment of the present invention may further have the following additional technical features:
according to an embodiment of the present invention, the step of forming the collector region includes: performing P on the surface of the buffer layer far away from the drift region - Ion implantation to form a second layer; p is carried out on the surface of the second layer far away from the drift region + Ion implantation to form a first layer; repeating P for multiple times alternately - Ion implantation and multiple times of said P + And ion implantation is carried out to form a collector region.
According to an embodiment of the present invention, said P - The doping concentration of the ion implantation is 5 x 10 18 ～1×10 19 cm -3 (ii) a And/or, said P -+ The doping concentration of the ion implantation is 1 × 10 17 ～5×10 17 cm -3 。
In a third aspect of the invention, a smart power module is presented.
According to an embodiment of the invention, the smart power module comprises: a circuit substrate on which a circuit wiring is provided, the circuit wiring including a soldered device region; at least one insulated gate transistor as described above, a bottom side of said insulated gate transistor being soldered to said soldered device region, a top side of said insulated gate transistor being bridged to said circuit trace by a metallic connection.
The inventor finds that the intelligent power module provided by the embodiment of the invention has the advantages that the turn-off loss of the insulated gate transistor is lower, the risk of damage of reverse current to a device is lower, and the dynamic loss and the static loss are more optimized, so that the intelligent power module has lower loss and longer service life. It will be appreciated by those skilled in the art that the features and advantages described above for insulated gate transistors are applicable to the smart power module and will not be described in detail herein.
In a fourth aspect of the present invention, an air conditioner is provided.
According to an embodiment of the invention, the air conditioner comprises the intelligent power module.
The inventor finds that the air conditioner provided by the embodiment of the invention has lower loss and longer service life of the intelligent power module, so that the air conditioner has higher stability and longer service life in long-term use. Those skilled in the art will appreciate that the features and advantages described above with respect to the smart power module are applicable to the air conditioner and will not be described in detail herein.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing aspects of the invention are explained in the detailed description of the embodiments with reference to the drawings, in which:
FIG. 1 is a schematic cross-sectional view of an insulated gate transistor according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating a method of fabricating an insulated gate transistor according to one embodiment of the present invention;
fig. 3 is a schematic top view of a mask for forming an active region in the manufacturing method according to an embodiment of the invention.
Reference numerals
100. Drift region
200 P well region
210. Mask area
220. Blank area
300. Active region
400. Grid electrode
500. Emitter electrode
600. Buffer layer
700. Collector region
710. First layer
720. Second layer
800. Collector electrode
Detailed Description
The following examples of the present invention are described in detail, and it will be understood by those skilled in the art that the following examples are intended to illustrate the present invention, but should not be construed as limiting the present invention. Unless otherwise indicated, specific techniques or conditions are not explicitly described in the following examples, and those skilled in the art may follow those techniques or conditions commonly employed in the art or in the product specification.
In one aspect of the invention, an insulated gate transistor is presented.
According to an embodiment of the present invention, referring to fig. 1, the insulated gate transistor includes a drift region 100, a P-well region 200, an active region 300, a gate 400, an emitter 500, a buffer layer 600, a collector region 700, and a collector 800; wherein, the P-well region 200 is disposed at one side of the drift region 100; the active region 300 is disposed on a side of the P-well region 200 away from the drift region 100; the gate 400 is disposed on a side of the P-well region 200 away from the drift region 100; the emitter 500 is disposed on the active region 300 and the P-well region 200 on a side away from the drift region 100; the buffer layer 600 is disposed on a side of the drift region 100 away from the gate 400; the collector region 700 is arranged on one side of the buffer layer 600 far away from the drift region 100; and collector 800 is disposed on a side of collector 700 away from drift region 100; wherein the collector region 700 is formed by alternately stacking a plurality of first layers 710 and a plurality of second layers 720, and the first layerLayer 710 is P + Ion doping, the second layer 720 is P - And (5) ion doping. In the present specification, the term "stacked arrangement" specifically means that the layers are stacked in sequence in the direction from the collector 800 to the drift region 100, that is, the layers are repeatedly arranged according to the repetition period of the first layer 710, the second layer 720, the layer structure of 8230\8230, and the layer structure of the first layer 710 and the layer structure of the second layer 720.
The inventor finds that in the research process, compared with the conventional single-layer transparent collector region, the P +/P - The collector region formed by alternate composition is P when the device is in forward conduction + Layer to P - The minority carriers injected into the drift region 100 are relatively large, so P + The layer ensures the injection efficiency of minority holes, and P - The layer reduces the storage of minority carriers in the drift layer 100; in addition, P + /P - The alternately formed structure can also make the process of injecting holes into the drift layer 100 more uniform, which is beneficial to the uniform distribution of current carriers in the drift region 100, and further effectively improves the dynamic loss and shock resistance of the device.
According to an embodiment of the present invention, P + The specific thickness of the ion-doped first layer 710 can be designed accordingly by those skilled in the art according to the implantation efficiency after the actual minority carrier optimization. In some embodiments of the present invention, the thickness of the first layer 710 may be 120-150 nm, such that a thinner P + The first layer 710 is doped with ions, so that the injection process of holes from the collector region 700 to the drift layer 100 is more uniform, and the device performance is better.
According to an embodiment of the present invention, P - The specific thickness of the ion-doped second layer 720 can be designed accordingly by those skilled in the art according to the actual minority carrier-optimized implantation efficiency. In some embodiments of the present invention, the thickness of the second layer 720 may be 80-100 nm, such that a thinner P - The second layer 720 is doped with ions, so that the injection process of holes from the collector region 700 to the drift layer 100 is more uniform, and the device performance is better.
According to an embodiment of the present invention, P + Ion doped first layer 710 and P - Specific number of ion-doped second layers 720, as is known in the artThe skilled person can select accordingly according to the actual optimization effect of collector region 700 on the minority carrier injection rate of drift region 100. In some embodiments of the present invention, the number of the first layer 710 and the second layer 720 may be 2 to 4, specifically, for example, 2, so that the injection rate of minority carriers is further optimized, thereby further increasing the extraction rate of minority carriers during turn-off, further increasing the turn-off speed, and further reducing the current tailing effect, thereby further reducing the risk of turn-off loss and damage of reverse current to the device.
According to an embodiment of the present invention, P of the first layer 710 + Ions and P of the second layer 720 - The specific doping concentration of the ions is not particularly limited as long as the P ion concentration of the first layer 710 is different from that of the second layer 720, and those skilled in the art can select the doping concentration accordingly according to the actual optimization effect of the actual collector region 700 on the injection rate of minority carriers. In some embodiments of the invention, P of the first layer 710 + The ion doping concentration may be 5 × 10 18 ～1×10 19 cm -3 And P of the second layer 720 - The ion doping concentration may be 1 × 10 17 ～5×10 17 cm -3 Thus, the collector region formed by alternately stacking the first layers 710 with high doping concentration and the second layers 720 with low doping concentration can better optimize the injection rate of minority carriers and is more beneficial to the uniform distribution of carrier concentration in the drift region.
In summary, according to the embodiments of the present invention, the present invention provides an insulated gate transistor having a collector region P + /P - The composite structure layer is formed, so that the injection efficiency of minority carriers can be optimized, the risk of the turn-off loss and the damage of reverse current to a device is reduced, the uniform distribution of the carrier concentration in a drift region is facilitated, and the dynamic loss and the static loss are optimized.
In another aspect of the invention, a method of making an insulated gate transistor is provided. According to an embodiment of the present invention, referring to fig. 2, the preparation method includes:
s100: p ions are implanted into one surface of the N-ion doped substrate to form a P well region and a drift region.
In this step, P ion implantation is performed on one surface of the N-ion doped substrate to form the P well region 200 and the drift region 100. According to an embodiment of the present invention, the specific shape of the P-well region 200 can be correspondingly designed by a person skilled in the art according to the structural design of the insulated gate transistor, and will not be described herein again.
S200: performing N on the surface of the P well region far away from the drift region + And implanting ions to form an active region.
In this step, the surface of P-well region 200 away from drift region 100 is subjected to N + Ion implantation is performed to form the active region 300. According to the embodiment of the present invention, the specific shape of the active region 300 can be correspondingly planned according to the structural design of the insulated gate transistor by those skilled in the art, and will not be described herein.
In some embodiments of the present invention, insulated gate transistors for silicon carbide (SiC) substrates may be designed as lateral devices, so long as isolated insulating regions are formed between the cells (i.e., individual insulated gate transistors). Specifically, referring to FIG. 3, a 1.5-3 micron (e.g., 2 micron) thick layer of silicon oxide (SiO) may be first epitaxially (e.g., sputtered or chemical vapor deposited) on the front side of the substrate 2 ) A protective layer, and etching the mask region 210 and the window region 220 in fig. 3 by a photolithography process, wherein the mask region 210 corresponds to a process region (e.g., the active region 200) of a plurality of unit cells, and the window region 220 corresponds to a gap between the plurality of process regions; then, ions (such as B, P, or N, etc.) are implanted at a temperature of 500 to 700 degrees celsius (such as about 600 degrees celsius) by a high temperature ion implantation technique, so that the mask region 210 is protected by the protection layer and is not affected by the ion implantation, the surface material of the window region 220 is bombarded and damaged by the ion implantation to generate deep level defects, and thus the material of the window region 220 is in a high resistance state, and an isolated insulation region is formed. Finally, the protective layer on the surface of the mask region 210 can be removed by wet etching, so that the subsequent device process can be continued.
Compared with the trench mesa spacing mode commonly adopted by silicon carbide transverse devices, the high-resistance isolation region formed by local ion implantation does not need to etch deep trenches between devices and does not need to fill isolation dielectric layers in the trenches. Moreover, the silicon carbide transverse device obtains the isolation of electrical properties on the basis of a planar process, the technical problems of poor mask coverage, poor metal connecting wire fracture and difficult and complex process caused by steps of the device are solved, the device is effectively isolated on the plane, and the integration level of the device is favorably improved.
S300: and performing metal deposition on the surfaces of the active region, the P well region and the drift region to form a grid electrode and an emitter electrode.
In this step, metal deposition is performed on the surfaces of the active region 300, the P-well region 200, and the drift region 100, and the gate electrode 400 and the emitter electrode 500 may be formed. Specifically, the gate 400 covers a portion of the P-well region 200 and the drift region 100, and the emitter 500 covers a portion of the active region 300 and the P-well region 200.
According to the embodiment of the present invention, a specific manner of metal deposition may be selected by a person skilled in the art according to actual materials of the gate 400 and the emitter 500, for example, physical Vapor Deposition (PVD) and the like, which are not described herein again.
S400: conducting N on the surface of the drift region far away from the grid electrode + And ion implantation is carried out to form the buffer layer.
In this step, N is performed on the back surface of the substrate + Ion implantation, i.e. N into the surface of the drift region remote from the gate + The buffer layer 600 may be formed by ion implantation.
S500: and performing P ion implantation on the surface of the buffer layer far away from the drift region to form a collector region.
In this step, P ion implantation is performed on the surface of the buffer layer 600 away from the drift region 200 to form the collector region 700, and the collector region 700 is formed by alternately stacking a plurality of first layers 710 and a plurality of second layers 720 in sequence, and the first layers 710 are P + Ion doping, the second layer 720 is P - And (5) ion doping.
In some embodiments of the present invention, step S500 may comprise: s510 performs P on the surface of the buffer layer 600 away from the drift region 100 - Ion implantation to form a second layer 720; s520 performs P on the surface of the second layer 720 far away from the drift region 100 + Ion implantation to form a first layer 710; s530 is repeated for P times alternately - Ion implantation and multiple P + Ion implantation is performed to form collector region 700. Thus, the collector region 700 is formed by combining different P ion implantation layers.
According to the embodiment of the invention, the repetition period can be 2-4 times, so that a collector region consisting of 4-8 layers of P +/P-composite structure layers is formed, the injection rate of minority carriers can be better optimized, the extraction speed of the minority carriers during turn-off is further increased, the turn-off speed is further increased, the current trailing effect is further reduced, and the turn-off loss and the risk of damage of reverse current to a device are further reduced.
In some embodiments of the invention, P of the first layer 710 + The ion doping concentration may be 5 × 10 18 ～1×10 19 cm -3 And P of the second layer 720 - The ion doping concentration may be 1 × 10 17 ～5×10 17 cm -3 Thus, the collector region formed by alternately stacking the first layers 710 with high doping concentration and the second layers 720 with low doping concentration can better optimize the injection rate of minority carriers and is more beneficial to the uniform distribution of carrier concentration in the drift region.
S600: and performing metal deposition on the surface of the collector region far away from the drift region to form a collector.
In this step, metal deposition is performed on the surface of collector region 700 remote from drift region 100 to form collector 800. Therefore, the insulated gate transistor with a complete structure and function can be prepared.
In summary, according to the embodiments of the present invention, the present invention provides a manufacturing method, which can form P by adjusting the dose or implantation energy of P ion implantation + /P - And the collector region of the alternating laminated structure is compounded, so that the insulated gate transistor with lower turn-off loss, lower risk of damage of reverse current to a device and more optimized dynamic loss and static loss can be prepared.
In another aspect of the invention, a smart power module is provided.
According to an embodiment of the present invention, a smart power module includes a circuit substrate and at least one of the above-described insulated gate transistors; the circuit substrate is provided with circuit wiring, and the circuit wiring comprises a welding device area; and the bottom side of the insulated gate transistor is soldered to the soldered device region, and the top side of the insulated gate transistor is bridged to the circuit wiring by a metal connection.
In summary, according to the embodiments of the present invention, the present invention provides an intelligent power module, in which turn-off loss of an insulated gate transistor is lower, a risk of damage to a device by a reverse current is lower, and dynamic loss and static loss are optimized, so that the intelligent power module has lower loss and longer service life. It will be appreciated by those skilled in the art that the features and advantages described above for the insulated gate transistor are still applicable to the smart power module and will not be described in detail here.
In another aspect of the present invention, an air conditioner is provided.
According to an embodiment of the invention, the air conditioner comprises the intelligent power module.
It should be noted that, besides the above-mentioned intelligent power module, the air conditioner also includes necessary components and structures, specifically, for example, a fan, a compressor, a heat exchanger, a throttling component, an air guiding component, a chassis, a panel, etc., and those skilled in the art can design and supplement the air conditioner accordingly according to the functions of the air conditioner, and details are not described herein again.
In summary, according to the embodiments of the present invention, the present invention provides an air conditioner, in which the loss of the intelligent power module is lower and the service life is longer, so that the air conditioner has higher stability and longer service life in long-term use. Those skilled in the art will appreciate that the features and advantages described above with respect to the smart power module are applicable to the air conditioner and will not be described in detail herein.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. An insulated gate transistor, comprising:
a drift region;
the P well region is arranged on one side of the drift region;
the active region is arranged on one side, far away from the drift region, of the P well region;
the grid electrode is arranged on one side, far away from the drift region, of the P well region;
the emitter is arranged on one side, far away from the drift region, of the active region and the P well region;
the buffer layer is arranged on one side, far away from the grid electrode, of the drift region;
the collector region is arranged on one side, far away from the drift region, of the buffer layer;
the collector electrode is arranged on one side, far away from the drift region, of the collector region;
wherein the collector region is formed by alternately stacking a plurality of first layers and a plurality of second layers in a direction from the collector to the drift region, and the first layers are P + Ion doping, the second layer is P - Ion doping; the first second layer is formed on the surface of the buffer layer far away from the drift region, and the first layer is formed on the surface of the first second layer far away from the drift region.
2. The insulated gate transistor of claim 1, wherein the thickness of the first layer is 120 to 150nm.
3. The insulated gate transistor of claim 1, wherein the thickness of the second layer is 80 to 100nm.
4. The insulated gate transistor according to claim 1, wherein the number of the first layer and the second layer is 2 to 4, respectively.
5. The insulated gate transistor of claim 1, wherein P of the first layer + The ion doping concentration is 5 × 10 18 ~1×10 19 cm -3 (ii) a And/or the presence of a gas in the atmosphere,
p of the second layer - The ion doping concentration is 1 x 10 17 ~5×10 17 cm -3 。
6. A method of fabricating an insulated gate transistor according to claim 1, wherein the method comprises:
performing P ion implantation on one surface of the N-ion doped substrate to form a P well region and a drift region;
n is conducted on the surface, far away from the drift region, of the P well region + Ion implantation is carried out to form an active region;
performing metal deposition on the surfaces of the active region, the P well region and the drift region to form a grid electrode and an emitter electrode;
n is carried out on the surface of the drift region far away from the grid electrode + Ion implantation to form a buffer layer;
p ion implantation is carried out on the surface of the buffer layer far away from the drift region to form a collector region, the collector region is formed by sequentially and alternately stacking a plurality of first layers and a plurality of second layers, and the first layers are P + Ion doping, the second layer is P - Ion doping;
and performing metal deposition on the surface of the collector region far away from the drift region to form a collector.
7. The method of claim 6, wherein the step of forming a collector region comprises:
performing P on the surface of the buffer layer far away from the drift region - Ion implantation to form a second layer;
p is carried out on the surface of the second layer far away from the drift region + Ion implantation to form a first layer；
Repeating P for multiple times alternately - Ion implantation and multiple times of said P + And implanting ions to form a collector region.
8. The method of claim 7, wherein P is + The doping concentration of the ion implantation is 5 x 10 18 ~1×10 19 cm -3 (ii) a And/or, said P - The doping concentration of the ion implantation is 1 × 10 17 ~5×10 17 cm -3 。
9. A smart power module, comprising:
a circuit substrate on which a circuit wiring is provided, the circuit wiring including a soldered device region;
the insulated gate transistor of any one of claims 1 to 5, wherein a bottom side surface of the insulated gate transistor is welded in the welding device area, and a top side surface of the insulated gate transistor is bridged to the circuit wiring through metal connection.
10. An air conditioner comprising the smart power module of claim 9.
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| JP2014022708A (en) * | 2012-07-17 | 2014-02-03 | Yoshitaka Sugawara | Semiconductor device and operation method of the same |
| CN103915489A (en) * | 2014-04-01 | 2014-07-09 | 绍兴文理学院 | Insulated gate bipolar transistor |
| CN107910367A (en) * | 2017-11-13 | 2018-04-13 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
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| CN100459151C (en) * | 2007-01-26 | 2009-02-04 | 北京工业大学 | Insulation bar dual-pole transistor with the internal transparent collector |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014022708A (en) * | 2012-07-17 | 2014-02-03 | Yoshitaka Sugawara | Semiconductor device and operation method of the same |
| CN103915489A (en) * | 2014-04-01 | 2014-07-09 | 绍兴文理学院 | Insulated gate bipolar transistor |
| CN107910367A (en) * | 2017-11-13 | 2018-04-13 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
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