JP2014022708A - Semiconductor device and operation method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable and high-voltage semiconductor device and an operation method of the same which inhibit a snapback phenomenon at the time of turn-off of a reverse conducting IGBT and inhibit damages on a semiconductor body due to the snapback phenomenon.SOLUTION: A reverse conducting IGBT is formed by a wide-gap semiconductor, and a distance Wp between collector short circuits 103 is set within a range from an upper limit determined by a distance between short circuits of a reverse conducting IGBT which is formed by a Si semiconductor and has the same breakdown voltage and the same configuration, to a lower limit determined by AxWp(Si). Here, a coefficient A represents a value obtained by dividing a product of built-in voltage Vbi(WB) of pn junction of a wide-gap semiconductor with characteristic on-resistance RonS(WB) of the wide-gap semiconductor device by a product of the built-in voltage Vbi(Si) after pn junction of a Si semiconductor device with characteristic on-resistance RonS(Si) of the Si semiconductor device.

Description

  The present invention relates to a semiconductor device, and more particularly to a high-performance reverse conducting IGBT and an operation method thereof.

  At present, Si-IGBTs mainly made of silicon (Si) are widely used in various application fields as high-voltage high-power and medium-power applications, and products up to 6 kV class are supplied. In recent years, various ideas have been devised in order to shorten the turn-off speed of these Si-IGBTs and reduce the loss. As a typical example, Si reverse conducting IGBTs of Conventional Example 1 shown in FIG. 5 and Conventional Example 2 shown in FIG. 6 have been developed and disclosed in Non-Patent Documents 1 and 2, respectively.

In the short-circuit collector Si-IGBT of the conventional example 1, the n ⁻ drift layer is short-circuited to the collector electrode by the n ⁺ short circuit portion provided in the p collector layer, and the carriers remaining in the n ⁻ drift layer at the time of turn-off are this n ⁺ short circuit. By eliminating it through the section, the turn-off time is shortened and the loss is reduced.
The Si reverse conducting IGBT of Conventional Example 2 is composed of a reverse conducting Si-IGBT region and a pilot IGBT region. In the Si reverse conducting IGBT region, the n drift layer is short-circuited to the collector electrode by the n ⁺ short-circuit portion provided in the p collector layer as in the conventional example 1, and carriers remaining in the n drift layer at the turn-off time are transferred to the n ⁺ layer. By eliminating via the short-circuit portion, the turn-off time is shortened to reduce the loss. Further, the collector width of the pilot IGBT region is significantly larger than the collector width of the reverse conducting IGBT region so that the pilot IGBT region is turned on prior to the reverse conducting IGBT region.
Note that these disclosed IGBTs are generally called reverse conducting IGBTs in recent years because the n drift layer is short-circuited to the collector electrode by the n ⁺ short-circuit portion, and thus has no ability to prevent reverse voltage. Therefore, all are hereinafter referred to as reverse conducting IGBTs.

  Hajime AKIYAMA, 5 others, Ict of Shorted Collector on Characters of IGBTS of The 2nd International Symposium on Power Semiconductor Devices & ICs), April 1990, p. 131-136   Liutauras Strasta, 2 others, A Comparison of Charge Dynamics in the Leverth Conducting RCIGBT and Bimode Insulated Gate Transistor (BIG) Insulated Gate Transistor BiGT), Proceedings of the Twenty Second International Symposium on Power Semiconductor Devices and ICs (Proceedings of The 22nd International Symposium) ium on Power Semiconductor Devices & ICs), 6 May 2010, p. 391-394

  By the way, the output characteristics of the disclosed Si reverse conducting IGBTs of Conventional Examples 1 and 2, that is, Ice-Vce between the collector-emitter voltage (hereinafter referred to as Vce) and the collector-emitter current (hereinafter referred to as Ice). As a characteristic, a snapback phenomenon occurs in which the collector-emitter voltage immediately before turning on is larger than the collector-emitter voltage immediately after turning on (hereinafter referred to as Von0). The collector-emitter voltage immediately before being turned on is referred to as “knee point voltage” in the conventional example 1 and is called the peak voltage before snapback in the conventional example 2, but is hereinafter referred to as “snapback voltage” and described as Vsb. The collector-emitter current at Vsb is called snapback current and is written as Isb.

  By the way, these reverse conducting IGBTs have a short time from immediately before turning on to immediately after turning on, that is, a turn-on time. (Hereinafter referred to as dI / dt). As a result, a steep jump voltage (C · dv / dt) is generated due to the parasitic capacitance existing in the circuit, and a steep jump current (L · dI / dt) is generated due to the parasitic reactor, resulting in a large transient phenomenon. Is triggered. For this reason, a large disturbance is caused in the circuit using the reverse conducting IGBT, causing malfunction, and in some cases, the element or circuit is destroyed. This is a very serious first problem.

  In the Si reverse conducting IGBT of Conventional Example 2, the pilot IGBT region is provided adjacent to the reverse conducting IGBT region composed of a large number of reverse conducting IGBT cells. The lateral resistance of the buffer layer on the p collector is increased by making the p collector width of the pilot IGBT region significantly larger than the p collector width of the IGBT cell in the reverse conducting IGBT region. The area is turned on. Thereby, the snapback phenomenon of the pilot IGBT region is suppressed. As a result, first, the pilot IGBT region in which the snapback phenomenon is suppressed is turned on with a small ice, and a larger on-current flows. This on-current spreads and flows into the nearest reverse conducting IGBT cell. Since the p collector of the adjacent reverse conducting IGBT cell is small in width, the lateral resistance of the buffer layer on the p collector is small. However, since a part of the on-current of the pilot IGBT flows as a large spreading current, The p-collector junction of the reverse conducting IGBT cell easily reaches the built-in voltage and turns on. As a result, the on-current further increases, and the reverse conducting IGBT cell adjacent to the nearest reverse conducting IGBT cell is similarly turned on. By repeating such an operation, the reverse conducting IGBT cells that are close to the pilot IGBT region are sequentially turned on, and the entire reverse conducting Si-IGBT is turned on.

  However, in the case of Reference 2, the area of the pilot IGBT region occupying the entire IGBT chip area is considerably increased. For example, in the case of Reference 2, when reading from the data, the p collector width of the reverse conducting IGBT cell is 180 μm, whereas the p collector width of the pilot IGBT is increased to about 720 μm or more, which is about four times or more. The voltage is 0.7V or less. As a result, the snapback phenomenon is eliminated, but the area of the reverse conducting IGBT region is reduced, so that the function of the original reverse conducting IGBT for eliminating carriers remaining at the time of turn-off is greatly impaired. This is a big problem in the present situation where the chip size of the element is normally set to about 12 mm × 12 mm or less from the viewpoint of economy such as yield, and is a second problem to be solved.

  In the case of a high breakdown voltage reverse conducting IGBT, the higher the breakdown voltage, the smaller the active area because a larger occupied area is required to relax the electric field on the chip surface, so the second problem becomes more serious.

  Moreover, the indirect reliability problem of the semiconductor device in which the reverse conducting IGBT causes malfunction or partial destruction through the disturbance of the circuit operation based on the snapback phenomenon has been clarified as described above. However, the reliability problem related to the damage directly applied to the semiconductor body by the snapback phenomenon has not been clarified and is not mentioned in the reference. This is an important third issue.

  An object of the present invention is to provide a high-performance reverse conducting IGBT that solves the above-described problems of the prior art and that can reduce Vsb and Isb and suppress a snapback phenomenon. In addition, the present invention provides a high-performance reverse conducting IGBT that can reduce the area occupied by the pilot IGBT region in the reverse conducting IGBT provided with the pilot IGBT region and that does not significantly suppress the function of removing the remaining carriers at turn-off. Make it the purpose. Furthermore, the present invention suppresses the loss of reliability due to the deterioration of the semiconductor body caused directly by the snapback phenomenon, and achieves high reliability and high performance reverse conducting IGBT and reverse conducting IGBT. The purpose is to provide an operation method.

  In the following, in order to facilitate understanding, the layer to which each semiconductor layer or semiconductor region corresponds functionally will be described in parentheses.

In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention includes a first semiconductor layer (drift layer) of a first conductivity type,
A second conductive type first semiconductor layer (collector layer) provided on the back surface of the semiconductor layer (drift layer), and a plurality of first conductive types penetrating the second conductive type first semiconductor layer (collector layer). A first semiconductor region (short-circuit portion) of the mold,
A plurality of second conductive type first semiconductor regions (p body layers) selectively provided on the front surface of the first conductive type first semiconductor layer (drift layer);
A first conductivity type second semiconductor region (emitter layer) selectively provided on the front surface of each of the second conductivity type first semiconductor regions (p body layer);
A first main electrode (emitter electrode) in contact with each second conductivity type first semiconductor region (p body layer) and the first conductivity type second semiconductor region (emitter layer);
The first conductive type second semiconductor region (emitter layer) and the first conductive type first semiconductor layer (drift layer) of each second conductive type first semiconductor region (p body layer). A control electrode provided via an insulating film on the surface of the portion sandwiched between
A semiconductor comprising a second main electrode (collector electrode) in contact with a back surface of the first conductivity type first semiconductor layer (collector layer) and the plurality of first conductivity type first semiconductor regions (short-circuit portions). In the device
Each semiconductor layer and each semiconductor region is formed of a wide gap semiconductor, and a distance Wp (WB) between the plurality of first semiconductor regions (short-circuited portions) of the first conductivity type,
The upper limit is the distance Wp (Si) of the semiconductor device having the same breakdown voltage and substantially the same configuration made of Si semiconductor,
The product of the built-in voltage Vbi (WB) of the pn junction of the wide gap semiconductor and the characteristic on-resistance RonS (WB) of the wide gap semiconductor device is calculated as the product of the built-in voltage Vbi (Si) of the pn junction of the Si semiconductor device and the Si semiconductor device. The value obtained by multiplying the value divided by the product of the characteristic on-resistance RonS (Si) by the distance Wp (Si) between the short-circuit portions is selected from a range having a lower limit.

The semiconductor device according to the present invention is the above-described invention,
Between the first semiconductor layer (drift layer) of the first conductivity type, the first semiconductor layer (collector layer) of the second conductivity type, and the plurality of first semiconductor regions (short-circuit portions) of the first conductivity type. The second conductive layer is provided with a second semiconductor layer (buffer layer) of the first conductivity type.

The semiconductor device according to the present invention is the above-described invention,
Of the distances Wp (WB) between the first semiconductor regions (short-circuit portions) of the plurality of first conductivity types, at least one distance Wp (WB) is set to a value that is less than or equal to the upper limit of the range and sufficiently larger than the lower limit. Wp (WB) other than is set to a value close to the lower limit of the range.

The semiconductor device according to the present invention is the above-described invention,
A cell has one or more first-conductivity-type first semiconductor regions (short-circuit portions), and a distance Wp between a width Wn (WB) and the first-conductivity-type first semiconductor regions (short-circuit portions). The ratio Wn (WB) / Wp (WB) to (WB) is 0.3 to 5.0.

According to another aspect of the present invention, there is provided a method of operating a semiconductor device in which a forward voltage is applied between the first main electrode (emitter electrode) and the second main electrode (collector electrode) in the above-described invention, and the control electrode Also, a low voltage is applied to make a forward bias state, and a forward current due to majority carriers flows through the plurality of first semiconductor regions (short-circuit portions) of the first conductivity type. After the temperature is raised to the above, the first carriers are injected so that minority carriers are injected from the second conductive type first semiconductor layer (collector layer) into the first conductive type first semiconductor layer (drift layer). The voltage between the main electrode (emitter electrode) and the second main electrode (collector electrode) and / or the voltage of the control electrode is controlled to a higher voltage.

According to the present invention, each semiconductor layer and each semiconductor region is formed of a wide gap semiconductor, and the upper limit of the distance Wp (WB) between the short-circuit portions is formed of a Si semiconductor as shown in the equation (1). The distance Wp (Si) between the short-circuit portions of the semiconductor device having the same configuration with the withstand voltage is set so that the lower limit is a newly discovered lower limit, that is, AxWp (Si), and the value is between these upper and lower limits. To do.

The newly discovered coefficient A is shown in the equation (2), and the product of the built-in voltage Vbi (WB) of the pn junction of the wide gap semiconductor and the characteristic on-resistance RonS (WB) of the wide gap semiconductor device is expressed by the Si This is divided by the product of the built-in voltage of the pn junction of the semiconductor device and the characteristic on-resistance of the Si semiconductor device.
This coefficient A is a value significantly smaller than 1.

Here, “the semiconductor device having the same breakdown voltage and the same configuration made of Si semiconductor” means “the cross-sectional shape is the same as that of the wide gap semiconductor reverse conducting IGBT and the impurity concentration and the width of the n ⁺ short-circuit portion are also the same. However, considering the physical properties peculiar to the Si material in order to realize the same breakdown voltage, the semiconductor device having the Si reverse conducting IGBT structure adopting the necessary impurity concentration, thickness and width of each semiconductor layer and each semiconductor region " Means.

  Although the distance Wp (WB) between the short-circuit portions of the reverse conducting wide gap semiconductor IGBT is set in this way, the Wp is reduced compared to the Si reverse conducting IGBT having the same breakdown voltage and the same configuration as the reference. The snapback phenomenon can be suppressed, and high performance can be achieved by speeding up and drastically reducing switching loss, and the first problem can be solved.

Hereinafter, the reason will be described with reference to FIG. 1 together with the derivation of the newly discovered coefficient A.
FIG. 1 shows a part of a cross-sectional view of an n-type Si reverse conducting IGBT. It is configured as follows. On the back surface in contact with the collector electrode 1 of the reverse conducting IGBT, p collector regions 2 and n + short-circuit portions 3 are alternately provided, and n (second conductivity type) is provided on the front surface of these regions 2 and 3. A buffer layer 4 is provided. An n ⁻ drift layer (first semiconductor layer) 5 is provided on the surface of the n buffer layer 4, and an n-type semiconductor layer (current density increasing layer: CEL, second semiconductor layer) 6 is provided on the surface thereof. . A plurality of p body regions (first semiconductor regions) 7 are selectively provided on the surface layer of the nCEL 6, and n ⁺ emitter regions (second semiconductor regions) 8 and p ⁻ low-concentration channel regions 9 are formed on the surface layer. And a p + contact region 10 are selectively provided. A gate electrode (control electrode) 12 is provided on the surface of the p ⁻ low-concentration channel region 9 via a gate insulating film 11. The emitter electrode (input electrode) 13 is in contact with the n ⁺ emitter region 8 and is also in contact with the p body region 7 through the p ⁺ contact layer 10. The emitter electrode 13 is insulated from the gate electrode 12.

First, the generation mechanism of the snapback phenomenon will be described using this reverse conducting IGBT. When a gate voltage higher than the threshold is applied to the MOS gate electrode 12 of the reverse conducting Si-IGBT and the forward voltage Vce between the collector electrode 1 and the emitter electrode 13 is applied and increased, the MOSFET portion first operates, An electron current flows from the emitter electrode 13 to the collector electrode through the n ⁺ emitter region 8, the p ⁻ low-concentration channel region 9, the nCEL layer 6, the n ⁻ drift layer 5, the n buffer layer 4, and the n ⁺ short-circuit portion 3. In the figure, the flow path of the electron current is schematically shown by dotted lines a, b, and c. A part c of this current flows laterally through the buffer layer 4 on the collector junction and flows to the collector electrode 1 via the n ⁺ short-circuit portion 3, and this lateral electron current causes the p collector junction central portion 14 and the collector electrode 1. When a potential difference is generated between 1 and 1 and this potential difference exceeds the built-in voltage Vbi of the collector junction (approximately 0.7 V in the case of Si), holes are injected from the p collector 2 into the n buffer layer 4 and then into the n drift layer 5. The hole current d indicated by the solid arrow flows, and the IGBT part is turned on. At this time, since the lateral resistance is small when the width of the p collector layer 2 is small, a large current is required to make the potential difference due to the lateral current more than the built-in voltage Vbi. As a result, the voltage in the n ⁻ drift layer The voltage drop and the voltage drop in the MOSFET part become large, and Vsb becomes large. However, once the IGBT portion is turned on, conductivity modulation occurs in the n ⁻ drift layer 5 due to the holes injected from the p collector 2, and the internal resistance of the n ⁻ drift layer is drastically reduced. . For this reason, a snapback phenomenon occurs.

Next, how the newly discovered coefficient A is derived will be described.
First, from the consideration of the mechanism of occurrence of the snapback phenomenon, Vbi (Si) when hole injection occurs from the collector of the Si reverse conducting IGBT is expressed as the following two items and converted as the four items: it can.
Here, Rb (Si) and ρb (Si) represent the resistance and resistivity of the buffer layer of the Si reverse conducting IGBT, and Jsb (Si) represents the snapback current density.
Thus, Wp (Si) can be approximately expressed by equation (2).
Similarly, the conditions under which hole injection from the collector occurs in a wide-gap semiconductor reverse conducting IGBT with the same configuration are as follows:
Here, ρb (WB) represents the resistivity of the buffer layer of the wide gap semiconductor reverse conducting IGBT, and Jsb (WB) represents the snapback current density.

By the way, in order to reduce and optimize the constant on-loss and turn-off loss in a high voltage IGBT, it is necessary to inject holes from the collector properly. Since ρb of the n buffer layer 4 for performing proper hole injection can be determined almost unambiguously without depending on the semiconductor material, it is approximately ρb (Si) = ρb (WB). Therefore, equation (5) can be derived from equations (3) and (4).

By the way, in the case of a high breakdown voltage IGBT, since the conductivity of the drain layer is not modulated before turning on, the voltage drop Vdrift of the drain layer is much higher than the voltage drop Vch at the channel resistance of the MOSFET part and the built-in voltage Vbi of the collector. Big. Therefore,
Since Vce just before turning on the reverse conducting IGBT is Vsb and Ice is Isb,
Substituting Jsb obtained from equation (6) into equation (5),
Therefore, the relationship between the distances Wp (WB) and Wp (Si) between the short-circuit portions for making Vsb the same in the wide-gap semiconductor reverse conducting IGBT and the Si reverse conducting IGBT having the same breakdown voltage is Vsb (WB) = By setting Vsb (Si), the equation (7) is obtained.
In this way, the coefficient A in the equation (2) can be derived.

Next, the reason why the first problem can be solved by setting Wp (WB) as shown in equation (1) will be described.
From the equation (7), it can be seen that the wide gap semiconductor reverse conducting IGBT can greatly reduce the distance Wp (WB) between the short-circuited portions as compared with the Si reverse conducting IGBT. For example, in the case of a SiC reverse conducting IGBT composed of a silicon carbide (hereinafter referred to as SiC) semiconductor, which is a kind of wide gap semiconductor, RonS (SiC) is approximately 1/1000 of RonS (Si), and Vbi (SiC) is Since Vbi (Si) is about 4 times, Wp (SiC) is about 1/250 of Wp (Si) from equation (7). Therefore, even if Wp (SiC) is significantly reduced to about 1/250 of Wp (Si), it is possible to achieve substantially the same Vsb. When a trial calculation is made with respect to a typical high breakdown voltage Si reverse conducting IGBT, Wp (Si) can be calculated as 175 μm from the equation (3). Therefore, Vsb of the SiC reverse conducting IGBT is higher than that of the Si reverse conducting IGBT having the same breakdown voltage. The range that can be suppressed is as follows from equation (1).
175 μm> Wp (SiC)> 0.7 μm
As a result, when the Vsb of the SiC reverse conducting IGBT is made the same as the Vsb of the Si reverse conducting IGBT in the case of the same breakdown voltage and the same chip size, there is a room for greatly increasing Wp (SiC) to 175 μm. Therefore, Vsb can be significantly reduced by significantly increasing Wp (SiC) within a range not exceeding Wp (Si) and reducing Isb. This means that the snapback phenomenon can be greatly suppressed.

Further, in the case of the same chip size with the same breakdown voltage, the snapback phenomenon is suppressed as described above by setting Wp (WB) to be smaller than Wp (Si) within the above range, while the smaller portion is obtained. In this case, the area of only the short-circuit region can be increased or the number of cells can be increased. In any case, the total area of the n ⁺ short-circuit portion can be greatly increased. As a result, the function of eliminating the remaining carriers at the turn-off time of the reverse conducting IGBT can be greatly increased, so that the turn-off time can be reduced, the reverse conducting IGBT can be speeded up, the switching loss can be reduced, and the wide gap semiconductor reverse conducting IGBT. Can improve performance.

As described above, the snapback phenomenon can be greatly suppressed and the reverse conducting IGBT can be improved in performance, so that the first problem can be solved.
Of course, it is possible to enjoy a known effect that the loss can be reduced while maintaining the same breakdown voltage due to the wide gap semiconductor.

  According to the invention, according to the above configuration, of the distances Wp between the plurality of first conductivity type first semiconductor regions (short-circuit portions), at least one distance Wp is close to the upper limit, that is, the upper limit of the range. In the following, it is set to a considerably large value that is several times the lower limit, and other Wp values are close to the lower limit of the range. A portion where the distance between the short-circuit portions is close to the upper limit can sufficiently function as a pilot IGBT portion. Therefore, the wide-gap semiconductor reverse conducting IGBT can keep the area occupied by the pilot IGBT portion much smaller than the Si reverse conducting IGBT. Therefore, in the case of the same chip size with the same breakdown voltage, the area of the reverse conducting IGBT region other than the pilot IGBT portion can be increased. As a result, the pilot IGBT portion is introduced and the snapback phenomenon is suppressed, but the turn-off is suppressed. It is possible to prevent a decrease in the original function of the reverse conducting IGBT, which sometimes eliminates the remaining carriers, and on the contrary, it can be increased and the second problem can be solved. This is because the chip size of the wide gap semiconductor element is restricted to 10 mm × 10 mm or less, and generally 5 mm × 5 mm or less from the economic point of view such as yield, and the original function of the reverse conducting IGBT is exhibited. This is extremely effective.

  Naturally, when the Wp of the pilot IGBT portion of the reverse conducting IGBT according to the present invention is increased within a range not exceeding the Wp of the pilot IGBT portion of the Si reverse conducting IGBT having the same structure, the snapback phenomenon can be further suppressed.

  According to the invention, the ratio of the width Wn of the first conductive type first semiconductor region (short-circuited portion) to the distance Wp between the first conductive type first semiconductor region (short-circuited portion) is within a specific range. Thus, the deterioration of the semiconductor main body caused directly by the snapback phenomenon can be suppressed, the high reliability of the high-performance reverse conducting IGBT can be realized, and the third problem can be achieved.

In general, a wide variety of defects are generated in a wide gap semiconductor material in a larger amount than Si. Of these defects, stacking faults have a property unique to wide-gap semiconductors, where when the injected minority carriers collide with the lattice points of the crystal, the atoms at the lattice points are moved by the collision energy, and the stacking faults expand. . Since the stacking fault traps minority carriers and recombines and disappears without contributing much to energization, the increase in stacking fault causes an increase in the internal resistance of the IGBT semiconductor device. Therefore, in the case of a bipolar type wide gap semiconductor device such as an IGBT, the stacking faults are expanded due to minority carriers injected while the device is in operation and energized, increasing the internal resistance. That is, the on-voltage deterioration is caused and the reliability is greatly impaired. However, the phenomenon that the stacking fault of the wide gap semiconductor traps minority carriers and recombines and disappears is gradually suppressed when the temperature is raised to about 40 ° C. or higher, and disappears almost completely at 200 ° C. or higher. The inventors have found that the papers of the Silicon Carbide and Related Materials 2007 (K. Nakayama et al., 7 of Behavior of Stacking Falts in TEDREC Phenomena for 4.5kV SiC. October, p. 1175-1178).
Hereinafter, this type of on-voltage increase is described as on-voltage degradation in order to distinguish it from an increase in on-voltage accompanying an increase in on-current.

  When a snap-back phenomenon exists in a wide gap semiconductor reverse conducting IGBT, a relatively large Isb needs to flow in order to realize a voltage drop, ie, Vbi, necessary for injecting minority carriers from the collector in Vsb immediately before turning on. . Until Vsb immediately before turning on, Isb due to majority carriers flows and the stacking fault does not expand, but once turned on, a large number of minority carrier currents corresponding to this Isb flow from the collector all at once into the buffer layer and the drift layer. As a result, stacking faults existing in the wide gap semiconductor reverse conducting IGBT are expanded at once, leading to rapid progress of on-voltage degradation, deteriorating the semiconductor body, and finally leading to damage and destruction. The rapid deterioration of the on-voltage when the wide-gap semiconductor reverse conducting IGBT in which the snapback phenomenon exists is hereinafter referred to as rapid on-voltage deterioration.

However, according to the present invention, by increasing the total area of increased width Wn of the n ⁺ short circuit portion n ⁺ short circuit portion, the semiconductor body is deteriorated resulting snapback phenomenon described above becomes a direct cause It is possible to suppress the rapid on-voltage degradation and achieve high reliability.
That is, Isb flows through the n ⁺ short circuit before the reverse conducting IGBT in which the snapback phenomenon exists, but this current is a large carry current and does not cause an increase in stacking faults. Therefore, n ⁺ aims to increase the Isb composed aggressive majority carrier by increasing the width Wn of the short-circuit portion for increasing the area of the n ⁺ short circuit portion, thereby the element temperature of the reverse conducting IGBT, stacking faults Can be raised before the reverse conducting IGBT is turned on to a temperature at which the phenomenon of trapping minority carriers and recombining and annihilating them is suppressed, so that rapid on-voltage degradation at the time of turning on can be suppressed.

In the case of the same breakdown voltage and the same chip size, the total area of the n ⁺ short-circuit portion is increased by increasing the width Wn of the first semiconductor region (n ⁺ short-circuit portion) of the first conductivity type of the cell. This decreases the distance Wp between the first semiconductor regions (n ⁺ short-circuited portion), and thereby reduces the collector area. In the former case, this causes an increase in snapback phenomenon, and in the latter case, an increase in on-voltage after turning on, that is, an increase in power loss. That is, when the cell width is fixed, if the Wn / Wp ratio is small, the temperature rise to a level that can suppress the on-voltage degradation is not easy, and if it is too large, the power due to the increase of the snapback phenomenon and the increase of the on-voltage Increases loss. Therefore, it is necessary to set the ratio of Wn / Wp within an appropriate range. On the other hand, the higher the breakdown voltage, the lower the impurity concentration in the drift region and the thicker the thickness, so that the internal resistance of the drift region is large and the device temperature can be increased with a smaller Isb. Therefore, the appropriate range of Wn / Wp varies depending on the breakdown voltage. As a result of various studies, the inventors have determined that the appropriate range of Wn / Wp in a high breakdown voltage reverse conducting IGBT of 3 kV or higher is preferably 0.2 to 5.0, more preferably in the case of a SiC semiconductor. It has been found that the range of 0.3 to 3.0 is good.
Thereby, the third problem can be solved and high reliability of the high-performance reverse conducting IGBT can be realized.

  Further, according to the operation method of the present invention, in addition to the rapid on-voltage degradation of the wide gap semiconductor reverse conducting IGBT, the on-voltage degradation at the initial operation can be suppressed, and high reliability can be realized.

In the wide-gap semiconductor reverse conducting IGBT, normal on-voltage degradation occurs due to stacking faults as described above, and rapid on-voltage degradation occurs due to a snapback phenomenon.
Therefore, according to the operation method of the present invention, at least before turning on the wide gap semiconductor reverse conducting IGBT, the MOSFET part is turned on at a predetermined low gate voltage, and a forward current due to majority carriers flows through the short-circuit part. The semiconductor device is heated to a predetermined temperature by a majority carrier current that does not cause an increase in defects, and then the gate voltage is increased to inject minority carriers from the collector layer, thereby turning on the reverse conducting IGBT.
As a result, not only the stacking faults that already exist, but also the rapid expansion of stacking faults caused by a large amount of minority carriers being rapidly injected from the collector layer into the buffer layer or drift layer due to the snapback phenomenon, Since the minority carrier trap phenomenon of stacking faults can be suppressed by the increase, not only normal on-voltage deterioration but also rapid on-voltage deterioration can be suppressed.
Once the wide gap semiconductor reverse conducting IGBT is turned on, the temperature rises due to self-heating, so that the effects of normal on-voltage degradation and rapid on-voltage degradation are suppressed. However, at the initial operation, the temperature of the wide gap semiconductor reverse conducting IGBT is as low as the ambient temperature. If the switch is turned on in this state, the stacking faults that have already existed are further enlarged, the deterioration of the ON voltage is promoted, and the reliability is impaired.
Therefore, at least during the initial operation of the wide gap semiconductor reverse conducting IGBT, the operation method of the present invention is used to raise the temperature to a predetermined temperature at which the minority carrier trap phenomenon of stacking faults can be suppressed before the reverse conducting IGBT is turned on. As a result, the influence of deterioration of the on-voltage can be greatly suppressed even at the initial operation, and the reliability can be improved.
Since the phenomenon is greatly suppressed, deterioration such as an increase in on-voltage can be significantly suppressed, and reliability can be improved.

Although an appropriate temperature increase temperature varies depending on the amount and size of stacking faults in the reverse conducting IGBT, it is preferable to increase the temperature to 40 ° C. or more, more preferably 50 ° C. or more at least at the initial operation. Even when 40 ° C. or higher cannot be maintained after the operation is started, if the operation method of the present invention is applied at each turn-on after the operation is started, an adverse effect of a large on-voltage degradation can be suppressed as in the case of the initial operation.
Thus, the third problem can be solved more effectively by this operation method, and high reliability of the high-performance reverse conducting IGBT can be realized.

  As described above, according to the present invention, the snapback phenomenon can be suppressed without significantly reducing the area of the short-circuit portion of the reverse conducting IGBT, and the remaining carriers can be effectively eliminated at the time of turn-off. As a result, the disturbance and destruction of the circuit operation due to the snapback phenomenon can be reduced, and the switching loss can be further reduced by shortening the turn-off time. Further, even if the chip area is smaller, the snapback phenomenon can be suppressed, so that the cost can be reduced. In addition, it is possible to improve the reliability by suppressing the influence of the on-voltage deterioration.

Explanatory diagram of the derivation method of the found coefficient Schematic sectional view of the semiconductor device according to the first embodiment. Schematic sectional view of the semiconductor device according to the second embodiment. Schematic sectional view of the semiconductor device according to the third embodiment. Schematic sectional view of the semiconductor device according to the fourth embodiment. Schematic sectional view of the semiconductor device according to the fifth embodiment. Sectional drawing of the high voltage | pressure-resistant Si reverse conduction IGBT apparatus of the prior art example 1. FIG. Sectional drawing of the high voltage | pressure-resistant Si reverse conduction IGBT apparatus of the prior art example 2. FIG.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n or p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. In the drawings, numbers and arrows indicating layers and regions are represented by only one representative in the case of the same layer or region, and others are omitted.

(Embodiment 1)
FIG. 2 is a cross-sectional view schematically showing the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment shown in FIG. 2 is a reverse conducting IGBT 100 having a planar gate structure of, for example, a design withstand voltage of 15 kV manufactured using a silicon carbide (SiC) semiconductor. FIG. 2 shows only a part of the active region of the reverse conducting IGBT 100. The SiC reverse conducting IGBT 100 includes a breakdown voltage structure (not shown) so as to surround the active region, for example. The active region is a region through which a current flows when the semiconductor device is turned on, and the breakdown voltage structure portion is a structure portion that relaxes the electric field strength on the pn junction surface constituting the semiconductor device and realizes a desired breakdown voltage.
The chip size of the SiC reverse conducting IGBT 100 is 8 mm × 8 mm, the active region is 6 mm × 6 mm, and the width of the pressure-resistant structure part surrounding the active region is 1 mm. The reverse conducting IGBT cell in the active region is striped and the cell width is 16 microns.

As shown in FIG. 2, in SiC reverse conducting IGBT 100, a p collector layer and a plurality of n ⁺ short-circuit portions penetrating this layer are provided on the back surface in contact with collector electrode 101, and p collector region 102 and n ⁺ short-circuit portion region are provided. 103 are alternately formed. An n (second conductivity type) buffer layer 104 is provided on the front surfaces of these regions 102 and 103. The n buffer layer 104 is a SiC epitaxial layer. The impurity concentration and thickness of the p collector region 102 may be, for example, 3.5 × 10 ¹⁷ cm ⁻³ and 1.5 μm, respectively. The impurity concentration and thickness of the n + short-circuit portion 103 may be, for example, 1 × 10 ¹⁹ cm ⁻³ and 1.5 μm, respectively. Further, the impurity concentration and thickness of the n buffer layer 104 may be, for example, 1.5 × 10 ¹⁶ cm ⁻³ and 10 μm, respectively. The n + short circuit part 103 in the cell may be provided near the center of the cell, and the width thereof may be 4 μm. The distance between the n + short-circuited portions, which corresponds to the width of the p collector region, may be 12 μm.

An n ⁻ drift layer (first semiconductor layer) 105 is provided on the surface of the n buffer layer 104. The n ⁻ drift layer 105 is a SiC epitaxial layer. The impurity concentration of the n ⁻ drift layer 105 is lower than the impurity concentration of the n buffer layer 102. Specifically, the impurity concentration and thickness of the n ⁻ drift layer 105 may be, for example, 2 × 10 ¹⁴ cm ⁻³ and 150 μm, respectively. When the impurity concentration is roughly this level, for example, a breakdown voltage of 1 kV per 10 μm thickness of the n ⁻ drift layer 105 can be easily realized. Therefore, a breakdown voltage of 15 kV can be expected by setting the thickness of the n ⁻ drift layer 105 to 150 μm.

An n-type semiconductor layer 106 is provided on the surface of the n ⁻ drift layer 105. This layer 106 is a layer having an effect of reducing the on-voltage of the IGBT by accumulating holes injected from the p collector region 102 in the vicinity of the surface of the n ⁻ drift layer 105, and is hereinafter referred to as an n charge accumulation layer. The n charge storage layer is, for example, a SiC epitaxial layer epitaxially grown using nitrogen (N) as an impurity, but may be a semiconductor layer formed by ion implantation of nitrogen ions. The n charge storage layer 106 may be provided only in the active region, and may be a semiconductor layer formed by ion implantation in the n ⁻ drift layer 105 of the active region, for example.

The impurity concentration of the n charge storage layer is higher than the impurity concentration of the n ⁻ drift layer 105 and lower than the impurity concentration of a p body region (p base region) 107 described later. However, it is important that n charge storage layer 106 has an impurity concentration and a thickness that are depleted with an applied voltage smaller than the withstand voltage of reverse conducting IGBT 100. Specifically, the impurity concentration of the n charge storage layer 106 may be 3 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less. The thickness between the n ⁻ drift layer 105 and the p body region (p base region) of the n charge storage layer 106 may be, for example, 0.3 μm or more and 1.6 μm or less.

A plurality of p body regions (first semiconductor regions) 107 are selectively provided on the surface layer of the n charge storage layer 106. The impurity concentration of p body region 107 is higher than the impurity concentration of n ⁻ drift layer 105 and n charge storage layer 106. Specifically, the impurity concentration and thickness of p body region 107 may be, for example, 1 × 10 ¹⁸ cm ⁻³ and 0.3 μm, respectively. The width of the n charge storage layer 106 sandwiched between adjacent p body regions 107 in the direction in which the p body regions 107 are arranged in parallel (hereinafter referred to as the horizontal direction) may be, for example, 6 μm.

The p body region 107 is a diffusion layer formed by ion implantation of aluminum, for example. In this embodiment, the n charge storage layer 106 has an impurity concentration of 5 × 10 ¹⁶ cm ⁻³ and a thickness of 0.7 μm.

  Since the SiC semiconductor has less impurity diffusion in the direction perpendicular to the depth direction than the silicon semiconductor, the semiconductor layer is shown in a rectangular shape in FIG. 2 (hereinafter, the same applies to the reverse conducting IGBT shown in FIGS. 3 to 5). The semiconductor layer is illustrated in a rectangular shape).

On the surface layer of the p body region 107, an n ⁺ emitter region (second semiconductor region) 108, a p ⁻ low-concentration channel region 109, and a p + contact region 110 are selectively provided. The n ⁺ emitter region 108, the p ⁻ low-concentration channel region 109, and the p + contact region 110 are semiconductor layers formed by ion implantation, for example. The p ⁻ low concentration channel region 109 is provided at one end of the p body region 108 and is in contact with the n charge storage layer 106. The n ⁺ emitter region 8 is in contact with the end of the p ⁻ low-concentration channel region 109 opposite to the end in contact with the n charge storage layer 106.

The end of the n ⁺ emitter region 108 on the side not in contact with the p ⁻ low concentration channel region 109 is in contact with the p + contact region 110. P provided in each p body region 107 ^- low-concentration channel region 109 and ^{n +} emitter region 108, p other p body regions 107 adjacent ^- placed in a low concentration channel region 109 and ^{n +} emitter region 108 and the symmetrical Has been.

The impurity concentration of the p ⁻ low concentration channel region 109 is lower than the impurity concentration of the p body region 107. Specifically, the impurity concentration and thickness of the p ⁻ low-concentration channel region 109 may be 3 × 10 ¹⁶ cm ⁻³ and 0.3 μm, respectively, for example. The channel length may be 0.75 μm.
The impurity concentration of the n ⁺ emitter region 108 is higher than the impurity concentration of the n ⁻ drift layer 105 and the n charge storage layer 106. Specifically, the impurity concentration and thickness of the n ⁺ emitter region 8 may be, for example, 5 × 10 ¹⁹ cm ⁻³ and 0.3 μm, respectively. The impurity concentration and thickness of the p + contact region 10 may be 1 × 10 ¹⁹ cm ⁻³ and 0.3 μm, for example.

The p ⁻ low concentration channel region 109 and the n ⁺ emitter region 110 are formed in the surface layer of the p body region 108 by ion implantation, respectively. Since the p ⁻ low concentration channel region 109 and the n ⁺ emitter region 108 are provided in the surface layer of the p body region 107 at a depth of, for example, 0.3 μm, the n charge accumulation layer 106 and the p ⁻ low concentration of the p body region 107 are provided. The thickness between the channel region 109 and the n ⁺ emitter region 108 is, for example, 0.3 μm.

The horizontal width of the p ⁻ low concentration channel region 109 may be, for example, 0.75 μm. The horizontal width of the n ⁺ emitter region 108 may be 3 μm, for example.

A gate electrode (control electrode) 112 is provided on the surface of the p ⁻ low-concentration channel region 109 via a gate insulating film 111. The thickness of the gate insulating film 111 may be about 500 angstroms. Emitter electrode (input electrode) 113 is in contact with n ⁺ emitter region 108 and is also in contact with p body region 107 through p ⁺ contact layer 110. The emitter electrode 113 is insulated from the gate electrode 112.

Next, a method for manufacturing SiC reverse conducting IGBT 100 shown in FIG. 2 will be described.
First, an n drift layer 105 having a thickness of 170 μm and an n buffer layer 104 having a thickness of 11.5 μm are sequentially formed on an off-angle n ⁺ SiC substrate having a thickness of 300 μm by epitaxial growth. Further, a 1.5 μm thick p collector layer is formed by aluminum ion implantation, and then a 1.5 μm thick n short-circuit region 103 and p collector region 102 are selectively formed by nitrogen ion implantation. Hereinafter, throughout this specification, the n short-circuit region and the p collector region are simply referred to as an n short-circuit region and a p collector.
Thereafter, a protective coating film is formed on the p collector 102 and the short circuit portion 103 to protect the p collector 102 and the short circuit portion 103 when the n ⁺ SiC substrate is polished. Next, the n ⁺ SiC substrate is completely removed by polishing, and the n drift layer 105 is also polished by about 20 μm to a thickness of 150 μm.

Next, for example, nitrogen is doped as an impurity and epitaxial growth is performed to grow the nCEL 106 on the surface of the n ⁻ drift layer 105. Since the nCEL 106 only needs to be provided at least in the active region, the nCEL may be formed only in the surface layer of the n ⁻ drift layer 105 in the active region, for example, by ion implantation.

In the case of forming the nCEL 106 by ion implantation, first, a resist mask having an opening exposing the formation region of the nCEL 106 is formed on the surface of the n ⁻ drift layer 105. Then, using this resist mask as a mask, for example, nitrogen ions are implanted into the n ⁻ drift layer 105 exposed at the opening of the resist mask. Furthermore, a thermal annealing process is performed. As a result, the n charge storage layer 106 is formed on the surface layer of the n ⁻ drift layer 105 over the entire active region. Thereafter, the resist mask used to form the n charge storage layer 106 is removed.
When the n charge storage layer 106 is formed by epitaxial growth, for example, nitrogen is doped as an impurity and epitaxial growth is performed.

Next, a resist mask having an opening exposing the formation region of the p body region 107 is formed on the surface of the n charge storage layer 106. Then, using this resist mask as a mask, p-type impurity ions are implanted into the n charge storage layer 106 exposed in the opening of the resist mask. At this time, in order to form the p ^- low concentration channel region 109 having an impurity concentration lower than that of the p body region 107 in the surface layer of the p body region 107 in a later process, the impurity concentration of the shallow portion of the p body region 107 is reduced. It is preferable to perform ion implantation so as to be lower than the impurity concentration in the deep portion.

Next, a thermal annealing process is performed. Thereby, p body region 107 is selectively formed on the surface layer of n charge storage layer 106. Next, the resist mask used to form p body region 107 is removed. Next, a resist mask having an opening exposing the p ⁺ contact layer formation region 110 is formed on the surface of the p body region 107. Then, using this resist mask as a mask, p-type impurity ions are implanted into p body region 107 exposed at the opening of the resist mask.
Further, a resist mask having an opening exposing the formation region of the p ⁻ low concentration channel region 109 is formed. Then, using this resist mask as a mask, impurity ions are implanted into p body region 107 exposed at the opening of the resist mask.

In the ion implantation for forming the p ⁻ low concentration channel region 109, when the impurity concentration of the surface layer of the p body region 107 is lower than the desired impurity concentration of the p ⁻ low concentration channel region 109, the p ⁻ low concentration A p-type impurity concentration is ion-implanted so that the channel region 109 has a desired impurity concentration. On the other hand, the impurity concentration of the surface layer of the p-body region 107 is p ^- low concentration is higher than desired impurity concentration of the channel region 109, p ^- n-type so that the low concentration channel region 109 has a desired impurity concentration Impurity concentration is ion-implanted.

Next, a thermal annealing process is performed. A p ⁻ low concentration channel region 109 is selectively formed in the surface layer of the p body region 107. Next, the resist mask used to form the p ⁻ low concentration channel region 109 is removed. Next, a resist mask having an opening exposing the formation region of the n ⁺ emitter region 8 is formed on the surface of the p ⁻ low concentration channel region 109. Then, using this resist mask as a mask, n-type impurity ions are implanted into p body region 107 exposed in the opening of the resist mask.

Next, a thermal annealing process is performed. As a result, n ⁺ emitter region 108 is selectively formed in the surface layer of p body region 107. Next, the resist mask used to form the n ⁺ emitter region 108 is removed. Next, a polycrystalline silicon gate electrode 112 is formed on the surface of the p ⁻ low-concentration channel region 109 with a gate insulating film 111 interposed therebetween. Next, an interlayer insulating film 113 is formed on the front surface, and the gate electrode 112 is covered with the interlayer insulating film 113.

Next, the interlayer insulating film 113 and the gate insulating film 111 are selectively removed by photolithography to form a contact hole for connecting the n ⁺ emitter region 108 and the p ⁺ contact layer forming region 110 and the emitter electrode 114. . Next, the emitter electrode 114 is formed in the front surface and the contact hole, and the emitter electrode 114 is connected to the n ⁺ emitter region 108 and the p ⁺ contact region 110. Next, a protective film (not shown) or the like is formed on the front surface of the semiconductor substrate. Thereafter, the collector electrode 111 in contact with the p collector 102 and the n short-circuit portion 103 is formed on the back surface of the semiconductor substrate, and the reverse conducting IGBT 100 shown in FIG. 1 is completed.

Next, characteristics of the IGBT 100 manufactured by the above manufacturing method will be described.
The IGBT 100 is die-bonded to a lead frame of a TO-type high-breakdown-voltage package, and a plurality of Al wires for connection are bonded to the emitter electrode 114, and then the chip is bonded with a high-temperature protective resin (nanotech resin) for protection. The Al wire is completely covered to make a semiconductor device, and then subjected to an operation test.
When a forward voltage is applied between the emitter electrode 114 and the collector electrode 101 without applying a gate voltage, a leakage current flows, but a good forward blocking characteristic is exhibited, and a voltage at room temperature, ie, an avalanche breakdown, is about 16. 4k. Moreover, the leakage current before avalanche breakdown is as good as 3.5 × 10 ⁻³ A / cm ² or less at room temperature and 5 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

When a gate voltage higher than the threshold voltage is applied to the gate electrode 112 and then a forward voltage is applied between the collector electrode and the emitter electrode and then increased, an on-current starts to flow in the vicinity of the built-in voltage of about 2.7 V, and snapback occurs. The phenomenon is not observed. This is an effect of the present invention. When the collector-emitter voltage (hereinafter Vce) is 5 V, Jce is as good as 105 A / cm ² .

The lower limit value of Wp (SiC) of the SiC reverse conducting IGBT derived from the equation (7) is about 1/250 of Wp (Si). The n ⁺ short-circuit portion distance Wp is the width of the p collector itself, and may be, for example, 12 μm as described above in this embodiment. Therefore, in the case of the Si reverse conducting IGBT that can eliminate the snapback phenomenon with the same breakdown voltage and the same configuration, the n ⁺ short-circuit distance Wp (Si) is 3000 μm. Here, the structure is the same as that shown in FIG. 2 as described above, but the impurity concentration and thickness of each semiconductor layer and each semiconductor region necessary for realizing the same breakdown voltage in consideration of the physical properties of the Si material. And a reverse conducting IGBT structure employing a width and the like. When Wn of both is 4 μm and the area of the active region is about 6 mm × 6 mm, in the case of Si reverse conducting IGBT, only two p collectors and three n ⁺ short-circuit portions can be provided. For this reason, even if the snapback phenomenon can be eliminated, it is speculated that the improvement in turn-off speed aimed at by the reverse conducting IGBT will be insignificant because the area occupied by Wn is too small. Actually, the 15 kV class SiC reverse conducting IGBT which has solved the above snapback phenomenon and the reverse conducting Si-IGBT having the same breakdown voltage and the same structure design have not achieved the IGBT operation in the simulation study. Therefore, when a Si reverse conducting IGBT having the same configuration with a breakdown voltage reduced to 6 kV was examined, when Wn (Si) was set to 4 μm and Wp (Si) was set to 12 μm as in the above-described reverse conducting SiC-IGBT, Vsb was set to 0.1. It is 7 kV or more, and there is a high possibility of destruction in the process of repeating the on operation.

In the case of the semiconductor device according to the present embodiment, the turn-off time when the DC power supply voltage is 6 kV and the current density is 50 A / cm can be shortened to 1.1 μs. In the case of the above-described 6 kVSi reverse conducting IGBT having the same breakdown voltage and the same configuration, the turn-off time is 6.5 μs. In general, when the withstand voltage is increased, the turn-off time tends to be longer, so the effect of this embodiment is clear. That is, in the SiC reverse conducting IGBT of the present embodiment, the width of the n ⁺ short-circuit portion is the same, but the n ⁺ short-circuit portion distance Wp is much smaller, so the number of cells can be increased correspondingly, and the total n ⁺ Since the occupation area of the short-circuit portion 103 can be increased, the carrier removal function at the time of turn-off of the reverse conducting IGBT can be increased.

Further, the n ⁺ short-circuit width Wn is 4 μm and the n + short-circuit distance Wp is 3000 μm, which is the same as that of the Si reverse-conducting IGBT, and the turn-off time of the SiC reverse-conducting IGBT is otherwise 4.2 μs. is there. Further, the SiC reverse conducting IGBT in which Wp is 1 μm and the carrier elimination function at the turn-off is greatly increased can reduce the turn-off time to about 0.35 μs, but a remarkable snapback phenomenon occurs.

In the SiC reverse conducting IGBT according to the present embodiment, the increase in the on-voltage after conducting the energization test for 500 hours at Jce 100 A / cm ² is conspicuous because most elements remain at 0.1 V or less, which is equivalent to the Si reverse conducting IGBT. No adverse effects on reliability are found.

On the other hand, in the case of an SiC reverse conducting IGBT in which the snapback phenomenon is intentionally generated by extremely reducing the distance between the n + short-circuited portions Wp, an IGBT showing on-voltage degradation of 2 V or more is generated in the same energization test. In addition, an SiC reverse conducting IGBT with this structure is an IGBT that shows a rapid on-voltage deterioration of the on-voltage after repeated 20-hour on / off test with Jce 60 A / cm ² and a pulse width of 500 μs, and shows an on-voltage deterioration of 7 V or more. Occur.

By applying the operation method according to the present invention described above, these SiC reverse conducting IGBTs can suppress an increase in on-voltage during IGBT operation to 0.2 V or less and eliminate adverse effects on reliability. Repeated tests can eliminate rapid on-voltage degradation. That is, first, a predetermined Vce voltage is applied between the collector electrode and the emitter electrode, and a gate voltage that does not start the IGBT operation, for example, about 5 V, is applied to the gate electrode. As a result, a MOSFET current is passed through the n ⁺ short-circuit portion 103, and the temperature of the element is increased by this current. When the temperature of the element reaches 50 ° C. or higher, the gate voltage is raised to about 20 V to perform the IGBT operation. This is because, by applying the operation method according to the present invention, the phenomenon of trapping and annihilating minority carriers due to stacking faults that cause an increase in on-voltage is greatly suppressed.

  In addition, when the operation method according to the present invention is not applied, that is, an operation of applying a predetermined Vce voltage and a gate voltage of 20 V to turn on is performed several times at a time interval in which the SiC reverse conducting IGBT cools to the ambient temperature. When these are repeated, the increase of the ON voltage further progresses each time, and the possibility that an element that breaks down at the time of ON increases is increased.

As described above, according to the semiconductor device according to the first embodiment, the snapback phenomenon can be significantly suppressed and the performance can be improved by further increasing the speed and loss, and the on-voltage deterioration can be suppressed and the reliability can be improved. High reverse conducting IGBT 100 can be realized. Further, by applying the operation method according to the present invention to the SiC reverse conducting IGBT in which the snapback phenomenon is intentionally generated by extremely reducing the distance between the n ⁺ short-circuited portions Wp, the on-voltage deterioration can be suppressed and the reliability is improved. It is possible to realize a high reverse conducting IGBT operation method.

(Embodiment 2)
FIG. 3 is a cross-sectional view schematically showing the semiconductor device according to the second embodiment. Compared to the semiconductor device of the first embodiment described above, the rest of the structure is the same except that the n drift layer is 175 μm thick and the n buffer layer is not provided and the n charge storage layer is not provided. The manufacturing process is substantially the same except that the n drift layer is epitaxially grown as thick as 195 μm and the formation process of the n buffer layer and the n charge storage layer is eliminated.

Next, the characteristics of the SiC reverse conducting IGBT according to the second embodiment will be described.
When a forward voltage is applied between the emitter electrode 214 and the collector electrode 201 without applying a gate voltage, a leakage current flows, but a good forward blocking characteristic is exhibited, and a voltage indicating a withstand voltage at room temperature, that is, an avalanche breakdown is 17.8 kV. It is near. Moreover, the leakage current before avalanche breakdown is 1.5 × 10 ⁻³ A / cm ² or less at room temperature and 3 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.
When a gate voltage higher than the threshold voltage is applied to the gate electrode 212 and then a forward voltage is applied between the collector and the emitter, an on-current flows at a built-in voltage of about 2.7 V and a snapback phenomenon is not observed. When the collector-emitter voltage (hereinafter referred to as Vce) is 5 V, Jce is as good as about 80 A / cm ² .

In the case of the semiconductor device according to the present embodiment, the width of the n ⁺ short-circuit portion is 4 μm as compared with the Si reverse conducting IGBT having the short-circuit portion distance Wp of 3000 μm that can eliminate the snapback phenomenon with the same breakdown voltage and the same configuration. Although the same, the distance between the n + short-circuited portions Wp is 12 μm, which is much smaller. Accordingly, since the number of cells can be increased due to the short Wp, and the total area of the n ⁺ short-circuit portion 203 can be increased, the function of removing carriers at the time of turn-off inherent to the reverse conducting IGBT can be increased. As a result, the turn-off time when the DC power supply voltage is 6 kV and the current density is 50 A / cm can be shortened to 1.2 μs. On the other hand, the 6 kV withstand voltage Si reverse conducting IGBT having the same configuration has a turn-off time of 8.1 μs despite its low withstand voltage. Further, when the n ⁺ short-circuit width Wn and the n ⁺ short-circuit distance Wp are the same as those of the Si reverse conducting IGBT and the other structure is the same SiC reverse conducting IGBT as in the present embodiment, the turn-off time is 3.9 μs. is there.

Further, even after a 500-hour energization test at Jce 100 A / cm ² , the increase in the on-voltage is 0.1 V or less, which is equivalent to that of the Si reverse conducting IGBT, and no significant adverse effect on reliability is found. On the other hand, in the case of the SiC reverse conducting IGBT in which the snapback phenomenon is intentionally generated by extremely reducing the distance between the n ⁺ short-circuited portions Wp, an IGBT that exhibits an on-voltage degradation of 4 V or more is obtained when a similar energization test is performed. Occur.
As described above, according to the semiconductor device according to the second embodiment, the snapback phenomenon can be significantly suppressed, and the performance can be improved by further reducing the high speed and loss, and the on-voltage deterioration can be suppressed and the reliability can be improved. High SiC reverse conducting IGBT 200 can be realized.

(Embodiment 3)
FIG. 4 is a cross-sectional view schematically showing the semiconductor device according to the third embodiment. This is a SiC reverse conducting IGBT with a design withstand voltage of 30 kV, which is provided with a pilot IGBT region in order to suppress the snapback phenomenon. FIG. 4 shows a half thereof and the reverse conducting IGBT1 cell portion.

The n ⁺ short-circuit portion 303 in the SiC reverse conducting IGBT cell may be provided in the vicinity of the center thereof facing the p body 307, and the width thereof may be 4 μm. n ⁺ distance between shorts, which corresponds to the width of the p collector, this width may be 12 μm. On the other hand, the width of the p collector in the pilot IGBT region may be 108 μm.
This SiC reverse conducting IGBT 300 has the same structure as that of the embodiment except that the pilot IGBT region is provided and the concentration and thickness of the n ⁻ drift layer 305, the p collector layer 302, and the n buffer layer 304 are different. It is almost the same as Form 1.

The n ⁻ drift layer 305 in this embodiment may have an impurity concentration of 9 × 10 ¹³ cm ⁻³ and a thickness of 300 μm. Further, the impurity concentration and thickness of the p collector 302 may be, for example, 6 × 10 ¹⁷ cm ⁻³ and 1.5 μm, respectively. The impurity concentration and thickness of the n buffer layer 304 may be, for example, 3.0 × 10 ¹⁶ cm ⁻³ and 17 μm, respectively.

The manufacturing process of this SiC reverse conducting IGBT 300 is substantially the same as that of the first embodiment except for the following points.
An n ⁻ drift layer 305 having a thickness of 320 μm and an n buffer layer 304 having a thickness of 17 μm are sequentially formed on a 300 μm thick off-angle n ⁺ SiC substrate by epitaxial growth. Further, a 1.5 μm thick p collector layer is epitaxially grown. Next, an n short-circuit portion 303 having a thickness of 1.5 μm is sequentially formed by selectively implanting nitrogen ions using a known photolithography technique.
Thereafter, a protective coating film for protecting the p collector 302 and the short-circuit portion 303 is formed on the p collector 302 and the short-circuit portion 303 during polishing of the n ⁺ SiC substrate. Next, the n ⁺ SiC substrate is completely removed by polishing, and the n drift layer 303 is also polished by about 20 μm to a thickness of 300 μm.

Next, characteristics of the SiC reverse conducting IGBT 300 according to the third embodiment will be described.
When a forward voltage is applied between the emitter electrode 314 and the collector electrode 301 in a state where no gate voltage is applied, a leakage current flows, but a good forward blocking characteristic is exhibited, and a voltage indicating a withstand voltage at room temperature, that is, an avalanche breakdown is 31.2 kV. It was near. Moreover, the leakage current before avalanche breakdown was as good as 6.5 × 10 ⁻³ A / cm ² or less at room temperature and 5 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.

When a gate voltage equal to or higher than the threshold voltage was applied to the gate electrode 312 and then a forward voltage was applied between the collector and emitter, an on-current flowed at a built-in voltage of about 2.7 V and a snapback phenomenon was not observed. When the collector-emitter voltage (hereinafter referred to as Vce) was 5 V, Jce was as good as 63 A / cm ² .

In the case of the semiconductor device according to the present embodiment, the width of the n ⁺ short-circuit portion is the same as that of the Si reverse conducting IGBT having the same breakdown voltage and eliminating the snapback phenomenon of the same configuration, but the reverse conducting IGBT cell and the pilot IGBT. Since the n ⁺ short-circuit distance Wp in the region is much smaller, the number of cells can be increased accordingly. For this reason, since the area of the n ⁺ short-circuit portion 303 can be increased, the function of removing carriers at the time of turn-off of the reverse conducting IGBT can be increased. As a result, the turn-off time when the DC power supply voltage is 10 kV and the current density is 50 A / cm is 1.8 μs. On the other hand, a 30 kV-class Si reverse conducting IGBT having the same configuration is difficult to manufacture, and the turn-off time is estimated to be about 20 μs or longer by simulation.

Further, no rapid on-voltage degradation is observed even after the ON / OFF repeated test of Jce 50 A / cm ² with a pulse width of 500 μs for 20 hours. This is an effect due to the fact that the snapback phenomenon can be eliminated by the present embodiment. Note that even after a 500-hour energization test at Jce 50 A / cm ² , the increase in the on-voltage is only 0.1 V or less in most devices, and no on-voltage degradation is observed.

  As described above, according to the semiconductor device according to the third embodiment, the snapback phenomenon can be significantly suppressed, the performance can be improved by further increasing the speed and loss, and the on-voltage deterioration can be suppressed, and the reliability can be improved. In addition, it is possible to realize an ultra-high withstand voltage SiC reverse conducting IGBT.

(Embodiment 4)
FIG. 5 is a cross-sectional view schematically showing a semiconductor device according to the fourth embodiment. Compared to the semiconductor device of the first embodiment described above, except for the point that the width Wn of the n ⁺ short-circuit portion 403 is 12 μm, and the distance between the short-circuit portions, that is, the width Wp of the p collector 402 is 4 μm, It is. Thereby, the SiC reverse conducting IGBT according to the fourth embodiment realizes higher reliability than that of the first embodiment.

That is, in the present SiC reverse conducting IGBT, the ratio Wn / Wp between the width Wn of the n + short-circuit portion and the width Wp of the p collector is increased to 3. Since the width of the cell is the same as 12 μm, the area of the n ⁺ short-circuit portion is increased by increasing the width Wn of the n ⁺ short-circuit portion as compared with the first embodiment, and Wp is reduced by the increase of Wn. The current Isb at which the p-collector junction is built-in is increased. Since the Isb current that flows before the SiC reverse conducting IGBT is turned on is a large number of carry currents and does not cause an increase in stacking faults, it is positively increased in the present embodiment. Due to the increase in Isb, heat generation caused by power loss particularly in the drift layer 405 is increased, so that the device temperature is reduced before the SiC reverse conducting IGBT is turned on, and stacking faults trap and recombine minority carriers to disappear. The temperature is raised to a temperature at which the phenomenon that occurs is suppressed, and the ON voltage deterioration at the ON point is suppressed.

  When the cell width is constant, if the Wn / Wp ratio is too small, it is difficult to increase the temperature to a level that can suppress the on-voltage degradation. Increase. Therefore, it is necessary to set the ratio of Wn / Wp within an appropriate range. On the other hand, the higher the breakdown voltage, the lower the impurity concentration in the drift region and the thicker the thickness, so that the internal resistance of the drift region is large and the device temperature can be increased with a smaller Isb. Therefore, the appropriate range of Wn / Wp varies depending on the breakdown voltage. As a result of various studies, the inventors have determined that the appropriate range of Wn / Wp is 0.2 to 5.0, more preferably 0.3 in a high voltage SiC reverse conducting IGBT of 5 kV or higher. It has been found that the range of ~ 3.0 is good.

The characteristics of the SiC reverse conducting IGBT according to the fourth embodiment will be described below.
When a forward voltage is applied between the emitter electrode 413 and the collector electrode 401 in a state where no gate voltage is applied, a leakage current flows, but a good forward blocking characteristic is exhibited, and a voltage indicating a withstand voltage at room temperature, that is, an avalanche breakdown is 17.3 kV. It is near. Moreover, the leak current before avalanche breakdown is 2.3 × 10 ⁻³ A / cm ² or less at room temperature and 2.8 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.
When a gate voltage higher than the threshold voltage is applied to the gate electrode 412 and then a forward voltage is applied between the collector and the emitter, an on-current flows at a built-in voltage of about 2.7 V and a snapback phenomenon is not observed. When the collector-emitter voltage Vce is 5 V, Jce is as good as about 60 A / cm ² .

Further, the turn-off time is 0.7 μs, which is shorter than that of the first embodiment. This is a reverse conducting IGBT with the same breakdown voltage and the same chip size and cell width, and since the ratio of Wn / Wp is increased, the total area of the n ⁺ short-circuited portion is increased, and thus the discharge capacity of remaining carriers at turn-off is increased. This is because the turn-off time can be shortened. As a result, power loss can be reduced and higher performance can be achieved.

In addition, no rapid deterioration of the on-voltage is observed after a 20-hour on / off repeated test with Jce 60 A / cm ² and a pulse width of 500 μs. This is an effect obtained by eliminating the snapback phenomenon in the present embodiment. Further, the change in the on-voltage of most elements according to the present embodiment is limited to 0.1 V or less, which is equivalent to a commercially available Si reverse conducting IGBT having a low withstand voltage, and no remarkable adverse influence on reliability is found.

In addition, when the above ON / OFF repeated operation test is performed for a long time of 500 hours, the ON voltage deteriorates if the SiC reverse conducting IGBT temperature is reduced to about room temperature (30 ° C or less) after the test is completed. Device is generated. Therefore, when this element is operated at a temperature of about room temperature, there is a concern such as element damage.
However, once the operation is started and the operation test is being performed, the element temperature is higher than 100 ° C. due to self-heating, so that the trapping phenomenon of the stacking fault is suppressed, so that the on-voltage is deteriorated. Even if the element is present, there is no actual damage such as a significant increase in power loss.

As can be seen from the above, the durability on / off repeated operation test is more preferable in confirming the effect of the present embodiment. This test is a test in which the device temperature is cooled to about room temperature after repeated on / off operation for 20 hours, repeated operation is repeated for on / off operation again for 20 hours, and then cooled to about room temperature again.
In the first embodiment, the N ⁺ short-circuit portion 203 has a width Wn of 2 μm, and the distance between the short-circuit portions, that is, the width Wp of the p collector 202 is 14 μm. When an off-repetition operation test is attempted, the on-voltage increases to 15 V or more when it is repeated about 20 times and is easily damaged.
On the other hand, in the case of the SiC reverse conducting IGBT of the fourth embodiment, no element is destroyed even if it is repeated 100 times or more, and higher reliability can be realized. This is the effect of the present embodiment by increasing the above Wn / Wp.

  As described above, according to the semiconductor device of the fourth embodiment, by increasing and optimizing Wn / Wp, it is possible to realize high performance by high speed and low loss, and the temperature immediately before turning on. Thus, it is possible to realize a SiC reverse conducting IGBT that can suppress deterioration of the on-voltage and has high reliability.

(Embodiment 5)
FIG. 6 is a cross-sectional view schematically showing a semiconductor device according to the fifth embodiment. Compared to the semiconductor device of the above-described fourth embodiment, the width Wn of the n ⁺ short-circuit portion 503 is 2.5 μm, the distance between the short-circuit portions, that is, the width Wp of the p collector 502 is 1.5 μm, and four sets in the cell The rest of the structure is the same except that an n ⁺ short circuit part and a p collector are provided.

  In the present SiC reverse conducting IGBT, as in the fourth embodiment, Wn / Wp is increased to 1 as compared with the first embodiment to achieve high performance and high reliability by suppressing on-voltage degradation. On the other hand, Isb can be increased because the width Wp of the p collector 502 in the cell is reduced to 2 μm by chopping compared to the fourth embodiment, so that the increase in device temperature immediately before turning on becomes higher. ing. However, the total width of Wp in the cell is 8 μm, which is twice as large as that in the fourth embodiment. This increases Jce after turning on, while reducing power loss by reducing the on voltage. .

The characteristics of the SiC reverse conducting IGBT according to the fifth embodiment will be described below.
When a forward voltage is applied between the emitter electrode 513 and the collector electrode 501 without applying a gate voltage, a leak current flows, but a good forward blocking characteristic is exhibited, and a voltage at room temperature, that is, an avalanche breakdown, is 17.1 kV. It is near. Moreover, the leakage current before avalanche breakdown is as good as 2.5 × 10 ⁻³ A / cm ² or less at room temperature and 3.1 × 10 ⁻² A / cm ² or less even at a high temperature of 250 ° C.
When Vce is 5 V and the voltage of the gate electrode 512 is 20 V, Jce is good at about 85 A / cm ² , which can be significantly increased as compared with the fourth embodiment. This also means that the on-voltage at a constant on-current can be reduced, and power loss can be reduced. These are the effects of the fifth embodiment. The turn-off time is 0.9 μs.

  In the SiC reverse conducting IGBT of the fifth embodiment, no element is destroyed even if it is repeated 200 times or more in the endurance on / off repeated operation test. This is because the width of Wp is reduced as compared with the fourth embodiment, so that the Isb current flowing before the SiC reverse conducting IGBT is turned on can be increased. Therefore, the temperature of the reverse conducting IGBT is turned on before the reverse conducting IGBT is turned on. This is because the phenomenon of stacking faults trapping minority carriers, recombining them and annihilating them can be greatly suppressed, and significant suppression of on-voltage degradation can be achieved.

  As described above, higher performance and higher reliability can be realized by the SiC reverse conducting IGBT of the fifth embodiment.

  Although the present invention has been described based on the first to fifth embodiments, the present invention is not limited to these, and it is obvious to those skilled in the art that various modifications can be easily made. For example, the numerical values of the structural specifications can be changed to expand to a wide gap semiconductor reverse conducting IGBT having a low breakdown voltage of 3 kV and a higher breakdown voltage of 50 kV. Naturally, various shapes such as a mesh shape can be adopted in addition to the stripe shape which also refers to the cell shape. In addition to the values mentioned for the cell width, the width of the n short-circuited portion, the width of the p collector, and the area ratio between the two, various values can naturally be adopted depending on the specifications of the reverse conducting IGBT. Although the cell structure in which the n short-circuited portion is provided opposite to the p-body near the center of the cell is mainly mentioned, it can be applied to a cell structure in which the n-short-circuited portion is provided at one end or both ends of the cell. Of course. Moreover, although mentioning the n-type reverse conducting SiC-IGBT, it is obvious that the same can be applied to p-type reverse conducting SiC-IGBTs having different polarities. Furthermore, although the reverse conducting SiC-IGBT has been mentioned, it can be applied to reverse conducting IGBTs using other wide gap semiconductors such as GaN and diamond.

  The present invention can be used for a high-voltage inverter directly connected to a power distribution system. In this case, the transformer can be significantly reduced in size and the transformer itself can be removed, so that the system can be significantly reduced in size and weight, and can save energy and resources. It becomes possible. In addition to the current distribution system, it can be used for the smart grid, which is the next generation network. Furthermore, it can be used for control devices for industrial equipment such as large fans, pumps, and rolling mills.

1, 101, 201, 301, 401, 501: collector electrode 2, 102, 202, 302, 402, 502: p collector 3, 103, 203, 303, 403, 503: n ⁺ short circuit 4, 104, 304, 404, 504: n buffer layer 5, 105, 205, 305, 405, 505: n ^- drift layer 6, 106, 306, 406, 506: n charge storage layer 7, 107, 207, 307, 407, 507: p Body region 8, 108, 208, 308, 408, 508: n ⁺ emitter region 9, 109, 209, 309, 409, 509: p ^- channel region 10, 110, 210, 310, 410, 510: p ⁺ contact region 11, 111, 211, 311, 411, 511: Gate oxide films 12, 112, 212, 312, 412, 512: Gate electrode 13, 113, 213, 313, 413, 513: Emitter electrode 14: Center part of p collector junction

Claims (5)

A first semiconductor layer of a first conductivity type;
A second conductivity type first semiconductor layer provided on a back surface of the semiconductor layer; and a plurality of first conductivity type first semiconductor regions penetrating the second conductivity type first semiconductor layer;
A plurality of second conductivity type first semiconductor regions selectively provided on the front surface of the first conductivity type first semiconductor layer;
A first conductivity type second semiconductor region selectively provided on the front surface of each of the second conductivity type first semiconductor regions;
A first main electrode in contact with each of the second conductivity type first semiconductor region and the first conductivity type second semiconductor region;
An insulating film is formed on a surface of each of the second conductive type first semiconductor regions sandwiched between each of the first conductive type second semiconductor regions and the first conductive type first semiconductor layer. A control electrode provided via,
A semiconductor device comprising: a second main electrode in contact with a back surface of the second conductive type first semiconductor layer and the plurality of first conductive type first semiconductor regions;
Each semiconductor layer and each semiconductor region are formed of a wide gap semiconductor, and a distance Wp (WB) between the plurality of first semiconductor regions of the first conductivity type,
The upper limit is the distance Wp (Si) of the semiconductor device having the same breakdown voltage and substantially the same configuration made of Si semiconductor,
The product of the built-in voltage Vbi (WB) of the pn junction of the wide gap semiconductor and the characteristic on-resistance RonS (WB) of the wide gap semiconductor device is calculated by multiplying the built-in voltage Vbi (Si) of the pn junction of the Si semiconductor device by the Si semiconductor device. A semiconductor device, wherein a value obtained by multiplying a value obtained by dividing the product by the product of the characteristic on-resistance RonS (Si) by the distance Wp (Si) between the short-circuit portions is selected from a lower limit. The semiconductor device according to claim 1.
The first conductivity type second semiconductor layer is disposed between the first conductivity type first semiconductor layer, the second conductivity type first semiconductor layer, and the plurality of first conductivity type first semiconductor regions (short-circuit portions). A semiconductor device comprising a semiconductor layer.   3. The semiconductor device according to claim 1, wherein at least one distance Wp (WB) is less than or equal to an upper limit of the range and less than a lower limit among the distances Wp (WB) between the plurality of first conductivity type first semiconductor regions. A semiconductor device characterized in that the value is set to a sufficiently large value and other Wp (WB) values are set to values close to the lower limit of the range.   4. The semiconductor device according to claim 1, wherein a plurality of first semiconductor regions of the first conductivity type are provided in a cell, and a width Wp between the width Wn (WB) and the first semiconductor region of the first conductivity type. A ratio of (WB) to Wn (WB) / Wp (WB) is set to 0.2 to 5.0.   At least at the time of initial operation, a forward voltage is applied between the first main electrode and the second main electrode and a low voltage is also applied to the control electrode so as to be in a forward bias state, and the plurality of first conductivity types A forward current due to majority carriers is passed through the first semiconductor region, and the temperature of the semiconductor device is raised to 40 ° C. or higher by this current, and then the first conductivity type of the first conductivity type is transferred from the second conductivity type first semiconductor layer. Controlling the voltage between the first main electrode and the second main electrode and the voltage of the control electrode, or one of the voltages to a higher voltage so that minority carriers are injected into the first semiconductor layer. The method for operating a semiconductor device according to claim 1, wherein: