CN110504221A - 电子封装 - Google Patents

电子封装 Download PDF

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CN110504221A
CN110504221A CN201910387824.1A CN201910387824A CN110504221A CN 110504221 A CN110504221 A CN 110504221A CN 201910387824 A CN201910387824 A CN 201910387824A CN 110504221 A CN110504221 A CN 110504221A
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package substrate
electronic packaging
interface circuit
speed interface
bare crystalline
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林岷臻
李怡慧
周哲雅
陈南诚
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供了一种电子封装。该电子封装包括矩形的封装基板和芯片封装。该芯片封装包括第一高速接口电路裸晶，安装在封装基板的上表面上，其中芯片封装与封装基板具有同轴配置，且芯片封装相对于封装基板具有角度偏移。根据本发明的电子封装，可以减轻信号扭曲和改善信号延迟，提高芯片封装的电性能。

Description

电子封装
技术领域
本发明总体上涉及用于高数据速率(high-data rate)通信应用的半导体封装领域。更具体地，本发明涉及一种电子封装，其包括具有高速信号处理电路的芯片封装，高速信号处理电路可诸如用于从串行通信链路发送和接收数据的串行器/串并转换器(serializer/deserializer，SerDes)电路。
背景技术
通常，数据通信网络包括多个通信设备和用于将这些通信设备互连或联网的连接基础设施或介质。通信设备可以包括嵌入式控制器。通信设备可以与操作在千兆每秒(Gigabit-per-second，Gbps)数据速率(例如，56Gbps或112Gbps)下的高速模拟串行数据接口或端口连接。根据已知的数据传输标准配置串行数据接口。连接基础设施能够与这种高速模拟串行数据接口交互。
在电子系统中使用高速串行通信链路的情况在持续增长。如本领域中已知的，高速数据链路经由传输线(transmission line)从一个位置向另一个位置传输数据。这些数据链路可以包括串行器/串并转换器(即SerDes)数据链路，其以并行格式(parallelformat)接收数据并将数据转换为串行格式(serial format)以进行高速传输。SerDes数据链路可以是通信系统中底板(backplane)的一部分。
然而，包含SerDes电路的用于高数据速率通信应用的现有技术芯片封装，通常遭受由信号扭曲(signal skew)或信号延迟引起的所谓的SerDes损耗，这反过来恶化了芯片封装的电性能。
发明内容
本发明的一个目的是提供一种用于高数据速率通信应用的改进的半导体电子封装，其能够减少信号扭曲或信号延迟，从而改善半导体电子封装的电性能。
根据一个实施例，公开了一种电子封装。该电子封装包括矩形的封装基板和芯片封装。该芯片封装包括第一高速接口电路裸晶，安装在封装基板的上表面上，其中芯片封装与封装基板具有同轴配置，且芯片封装相对于封装基板具有角度偏移。
根据一个实施例，芯片封装在与上表面正交的垂直轴上相对于封装基板旋转约45度。
第一高速接口电路裸晶包括第一串行器/串并转换器(SerDes)电路块。
根据一个实施例，封装基板的上表面在二维平面中被两个正交轴划分成四个象限。第一高速接口电路裸晶包括直接面向封装基板的顶点的第一边缘，其中沿着第一边缘设置有第一排输入/输出(I/O)焊盘。第一高速接口电路裸晶包括垂直于第一边缘的第二边缘，其中沿着第二边缘设置有第二排I/O焊盘。
沿着在封装基板的顶点处接合的两个侧边布置有第一组焊球，并且其中在封装基板的上表面上的四个象限中的其中一个象限内，第一排I/O焊盘分别通过多个第一迹线电连接到第一组焊球。
沿着在封装基板的顶点处接合的两个侧边其中之一布置有第二组焊球，并且其中在封装基板的上表面上的四个象限中的其中一个象限内，第二排I/O焊盘分别通过多个第二迹线电连接到第二组焊球。
电子封装还包括靠近所述第一高速接口电路裸晶的第二高速接口电路裸晶。第二高速接口电路裸晶包括第二SerDes电路块。第一高速接口电路裸晶通过再分配层结构电连接到第二高速接口电路裸晶。
根据一个实施例，公开了一种电子封装。该电子封装包括矩形封装基板以及包括第一高速接口电路裸晶的芯片封装。该芯片封装安装在封装基板的上表面上，其中第一高速接口电路裸晶的多个I/O焊盘分别通过所述封装基板的所述上表面上的四个象限中的其中一个象限内的多个迹线电连接到所述封装基板的焊球。
根据本发明的电子封装，可以减轻信号扭曲和改善信号延迟，提高芯片封装的电性能。
在阅读了在附图和附图中示出的优选实施例的以下详细描述之后，本领域技术人员无疑能够清楚了解本发明的目的。
附图说明
图1是根据本发明一个实施例的电子封装的透视顶视图。
图2是沿着图1中的线I-I'截取的示意性横截面图。
图3是根据本发明一个实施例的电子封装的透视图。
具体实施方式
在下面对本发明实施例的详细描述中，参考了构成本发明一部分的附图，并且其中通过图示的方式示出了可以实现本发明的特定优选实施例。
充分详细地描述了本发明的实施例以使得本领域技术人员能够实施，应该理解，也可以利用其他实施例并且可以在不脱离本发明的精神和范围的情况下进行机械上、结构上和程序上的改变。因此，以下详细描述不应被视为具有限制意义，本发明的实施例的范围仅由所附权利要求限定。
应当理解，尽管这里可以使用术语第一、第二、第三、主要、次要等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应受这些术语的限制。这些术语仅用于将一个元件、组件、区域、层或部分与另一个元件、组件、区域、层或部分区分开。因此，在不脱离本发明的思想的教导下，下面讨论的第一或主要元件、组件、区域、层或部分也可以称为第二或次要元件、组件、区域、层或部分。
为了便于描述附图中所示的一个元件或特征与另一个元件或特征的关系，本文中使用了空间相对术语，诸如“之下”、“下方”、“下部”、“低于”、“之上”、“上部”、“上方”等。应当理解，除了图中所示的方位(orientation)之外，空间相对术语旨在包括使用或操作中的器件的不同方位。例如，如果图中的器件被翻转，那么被描述为位于其他元件或特征“之下”或“下方”或“下面”的元件将被定向位于其他元件或特征“之上”或“上方”。因此，示例性术语“下面”和“下方”可以包括上方和下方两个方位。器件可以以其他方式定向(旋转90度或以其他方位)，并相应地解释本文使用的空间相对描述语。另外，还应理解，当某个层被称为在两个层“之间”时，它可以是两个层之间的唯一层，或者也可以存在一个或多个中间层。
本文使用的术语仅用于描述特定实施例，并不旨在限制本发明的思想。本文使用的单数形式“一”和“该”旨在也包括复数形式，除非上下文中另有明确说明。将进一步理解，当在本说明书中使用术语“包括”时，是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除存在或者添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或组。本文所使用的术语“和/或”包括所列相关项目中一个或多个项目的任何和所有组合，并且可以缩写为“/”。
应当理解，当某元件或层被称为“位于……上”、“连接到”、“耦接到”或“邻近”另一个元件或层时，它可以直接位于该另一个元件或层其上、与该另一个元件或层直接连接、耦接或相邻，或者可以存在中间元件或层。相反，当元件被称为“直接位于另一元件或层上”、或“直接连接到”、“直接耦接到”或“紧邻”另一元件或层时，则不存在中间元件或层。
串行器/串并转换器(SerDes)是高速通信中常用的一对功能块，以补偿有限的输入/输出。这些块在串行数据和并行接口之间在每个方向上转换数据。术语“SerDes”通常指在各种技术和应用中使用的接口。SerDes的主要用途是在单个线路或差分对线路上提供数据传输，以使I/O引脚(pin)和互连(interconnect)的数量最小化。SerDes数据传输实现可以用于各种通信系统和设备，例如移动设备、台式计算机和服务器、计算机网络和电信网络。
所公开的操作在千兆每秒(Gigabit-per-second，Gbps)数据速率的电子封装，能够减少信号扭曲并因此改善芯片封装的电性能，这适用于高数据速率通信应用，包括但不限于，超大规模数据中心、超高性能网络交换机、路由器或计算应用程序以及4G和5G服务提供商(回程(backhaul))基础设施、AI/深度学习应用和新颖的计算应用。
参照图1至图3。图1是根据本发明一个实施例的电子封装的透视顶视图。图2是沿着图1中的线I-I'截取的示意性横截面图。图3是根据本发明一个实施例的电子封装的透视图。
如图1至图3所示，根据一个实施例，电子封装1包括芯片封装10，芯片封装10以倒装芯片方式(flip-chip manner)安装在封装基板20的上表面201上。当从上面观察时，芯片封装10和封装基板20都具有矩形形状。例如，芯片封装10和封装基板20都可以具有四个边长度相等的正方形形状。芯片封装10具有四个侧边(side)10a～10d。封装基板20具有四个顶点A～D，以及分别在四个顶点A～D之间的四个侧边20a～20d。
如图1所示，封装基板20的上表面201可以在二维平面(平行于上表面201)中由两个正交轴(参考X和Y轴)划分为四个90度象限Q1～Q4。象限Q1和Q3彼此对角地相对。象限Q2和Q4彼此对角地相对。参照图1至图3，示出了与上表面201或X-Y平面正交的参考Z轴。
根据一个实施例，封装基板20可以是包括层压有机材料(laminated organicmaterial)或核心(core)200(诸如环氧树脂等)的有机基板。如图2所示，多个焊球(solderball)230可以设置在封装基板20的底表面202上。芯片封装10通过多个焊点(solderjoint)或凸块(bump)30安装在封装基板20的上表面201上。提供底部填充物(underfill)40，以填充芯片封装10和封装基板20之间的间隙(或间隔)。封装基板20可以包括多个迹线层，例如迹线211和221。
在图2中，迹线211旨在设置在封装基板20的多个迹线层的最顶层中。通常，迹线211被诸如焊接掩模(solder mask)等的保护层280覆盖，但是不限于此。凸块30接合到位于迹线211的一个远端处的对应凸块焊盘210，并与之对齐。迹线211朝向顶点A处的拐角延伸或朝向拐角处的两个相邻侧边20a和20b延伸。
用于电连接对应凸块焊盘210的迹线211通常设置在示例性呈现的象限Q2内。迹线211电耦接到连接焊盘212。可以提供电镀通孔(plated through hole，PTH)213，将连接焊盘212电连接到封装基板20的底表面202处的焊球焊盘214。焊球230焊接在焊球焊盘214上，以进一步与系统板或印刷电路板(printed circuit board，PCB)连接。
为了简单起见，在如图1所示的透视图中仅仅呈现了在象限Q2内的迹线和焊球布置。焊球230在图1中未明确示出。然而，应该理解的是，由于连接焊盘212与焊球焊盘214对齐并因而与焊球230对齐，所以图1中每个连接焊盘212的位置，总体上表示每个焊球230的位置。应当理解，在其他实施例中，在象限Q2中的配置可以用在其他象限Q1、Q3和Q4中。
如图1和图3所示，芯片封装10和封装基板20可以具有相同的中心点CP，因此封装基板20与芯片封装10具有同轴配置(concentric configuration)，其中该芯片封装10相对于封装基板20具有角度偏移。根据一个实施例，优选地，芯片封装10相对于封装基板20绕Z轴旋转大致45度。这里大致45度是指芯片封装10相对于封装基板20的角度偏移与45度之间的差异在本领域技术人员能够理解的预定误差范围内，即使芯片封装10相对于封装基板20的角度偏移不是非常精确的45度，只要在可接受的误差范围内，也基本上能够实现本发明的预定目的和技术效果。根据一个实施例，芯片封装10的四个侧边10a～10d中任何一个都不与封装基板20的四个侧边20a～20d中的任何一个平行。
旋转芯片封装10，使得其一个侧边10a直接面向封装基板20的顶点A处的拐角。封装基板20的两个侧边20a和20b在顶点A处连接。两个侧边20a和20b限定90度象限Q2的边界。
根据一个实施例，芯片封装10包括第一高速接口电路裸晶(die)11，其可以在高于500MHz的频率下以至少1000Mbps的高速数据传输速率操作。如图2所示，第一高速接口电路裸晶11可以封装在模塑料50内。根据一个实施例，第一高速接口电路裸晶11包括第一串行器/串并转换器(SerDes)电路块,该第一SerDes电路块靠近直接面向封装基板20的顶点A处拐角的侧边10a。
根据一个实施例，如图1所示，第一高速接口电路裸晶11包括直接面向封装基板20的顶点A处拐角的第一边缘11a、垂直于第一边缘11a并接合到第一边缘11a的第二边缘11b、垂直于第一边缘11a并接合到第一边缘11a的第三边缘11c。根据一个实施例，第一边缘11a与芯片封装10的侧边10a平行，第二边缘11b与芯片封装10的侧边10d平行，第三边缘11c与芯片封装10的侧边10b平行。第二边缘11b和第三边缘11c与在顶点A和顶点C之间延伸的对角线DL平行。
根据一个实施例，如图1所示，第一排输入/输出(I/O)焊盘111a沿第一边缘11a设置，第二排I/O焊盘111b沿第二边缘11b设置，第三排I/O焊盘111c沿第三边缘11c设置。可以理解，这些I/O焊盘设置在第一高速接口电路裸晶11的底部。
根据一个实施例，可以在第一高速接口电路裸晶11和封装基板20的上表面201之间提供再分配层(redistribution layer，RDL)结构100，以扇出(fan-out)I/O焊盘。本领域已知的RDL结构100可以由电介质层以及电介质层中的互连结构组成，该互连结构用于将高速接口电路裸晶11的I/O焊盘电连接到形成焊点(solder joint)30的相应凸块焊盘101。根据一个实施例，芯片封装10可以是扇出式晶圆级封装(fan-out wafer level package，FOWLP)。
根据一个实施例，第一高速接口电路裸晶11的第一SerDes电路块、边缘11a～11c、I/O焊盘排111a～111c通常设置在示例性象限Q2内。可以理解，芯片封装10被翻转为其有效表面(active surface)以倒装芯片的方式安装在封装基板20的上表面201上。
如图1所示，根据一个实施例，第一组焊球P1(焊球在图1中未明确示出，但与连接焊盘212a对齐)沿着在封装基板20的顶点A处接合的两个侧边20a和20b布置。设置在高速接口电路裸晶11的第一边缘11a处的第一排I/O焊盘111a分别通过封装基板20的上表面201上的象限Q2内的迹线211a电连接到第一组焊球P1。
根据一个实施例，第二组焊球P2(焊球在图1中未明确示出，但与连接焊盘212b对齐)沿着与顶点A处的拐角相邻的侧边20a布置。第二排I/O焊盘111b分别通过封装基板20的上表面201上的象限Q2内的迹线211b电连接到第二组焊球P2。
根据一个实施例，第三组焊球P3(焊球在图1中未明确示出，但与连接焊盘212c对齐)沿着与顶点A处的拐角相邻的侧边20b布置。第三排I/O焊盘111c分别通过封装基板20的上表面201上的象限Q2内的迹线211c电连接到第三组焊球P3。
根据一个实施例，如图2所示，芯片封装10还可以包括靠近第一高速接口电路裸晶11的第二高速接口电路裸晶12。第二高速接口电路裸晶12可以包括SerDes电路块并且可以在封装基板20的上表面201的象限Q4中具有类似的迹线和球布置。第一高速接口电路裸晶11可以通过RDL结构100电连接到第二高速接口电路裸晶12。例如，第一高速接口电路裸晶11的I/O焊盘111c通过RDL结构100中的互连线103电连接到第二高速接口电路裸晶12的I/O焊盘121c。
使用本发明是有利的，因为通过提供旋转的芯片封装配置，封装基板上的相应迹线和球布置集中在四个象限Q1～Q4中其中一个中，导致最大信号长度减少14.3％(例如，对于60×60mm～90×90mm的封装基板，从约35mm到约30mm)以及迹线长度差异(最大长度减去最小长度)从20mm到13mm的显著减小。因此，可以减轻扭曲，并且可以显著改善电子封装的SerDes电路的信号延迟以及电性能(例如，改善18％或约-0.5dB)。
本领域技术人员将容易认识到，可以在保留本发明的教导的同时对装置和方法进行多种修改和变更。因此，上述公开内容应被解释为仅受所附权利要求的范围和界限的限制。

Claims (21)

1.一种电子封装，包括：
矩形的封装基板；以及
包括第一高速接口电路裸晶的芯片封装，所述芯片封装安装在所述封装基板的上表面上，其中所述芯片封装与所述封装基板具有同轴配置，且所述芯片封装相对于所述封装基板具有角度偏移。
2.根据权利要求1所述的电子封装，其中所述封装基板的所述上表面在二维平面中被两个正交轴划分成四个象限，其中所述第一高速接口电路裸晶的边缘与所述芯片封装的边缘彼此平行。
3.根据权利要求2所述的电子封装，其中所述第一高速接口电路裸晶包括直接面向所述封装基板的顶点的第一边缘，其中沿着所述第一边缘设置有第一排输入/输出I/O焊盘。
4.根据权利要求3所述的电子封装，其中所述第一高速接口电路裸晶包括垂直于所述第一边缘的第二边缘，其中沿着所述第二边缘设置有第二排I/O焊盘。
5.根据权利要求4所述的电子封装，其中沿着在所述封装基板的所述顶点处接合的两个侧边布置有第一组焊球，并且其中所述第一排I/O焊盘分别通过所述封装基板的所述上表面上的所述四个象限中的其中一个象限内的多个第一迹线电连接到所述第一组焊球。
6.根据权利要求5所述的电子封装，其中沿着在所述封装基板的所述顶点处接合的所述两个侧边其中之一布置有第二组焊球，并且其中所述第二排I/O焊盘分别通过所述封装基板的所述上表面上的所述四个象限中的所述其中一个象限内的多个第二迹线电连接到所述第二组焊球。
7.根据权利要求1所述的电子封装，其中所述芯片封装在与所述上表面正交的垂直轴上相对于所述封装基板旋转大致45度。
8.根据权利要求1所述的电子封装，其中所述第一高速接口电路裸晶包括第一串行器/串并转换器电路块。
9.根据权利要求1所述的电子封装，还包括：
靠近所述第一高速接口电路裸晶的第二高速接口电路裸晶。
10.根据权利要求9所述的电子封装，其中所述第二高速接口电路裸晶包括第二串行器/串并转换器电路块。
11.根据权利要求9所述的电子封装，其中所述第一高速接口电路裸晶通过再分配层结构电连接到所述第二高速接口电路裸晶。
12.一种电子封装，包括：
矩形的封装基板；以及
包括第一高速接口电路裸晶的芯片封装，所述芯片封装安装在所述封装基板的上表面上，其中所述第一高速接口电路裸晶的多个输入/输出I/O焊盘分别通过所述封装基板的所述上表面上的四个象限中的其中一个象限内的多个迹线电连接到所述封装基板的焊球。
13.根据权利要求12所述的电子封装，其中所述封装基板的所述上表面在二维平面中被两个正交轴划分成所述四个象限。
14.根据权利要求12所述的电子封装，其中所述芯片封装与所述封装基板具有同轴配置，且所述芯片封装相对于所述封装基板具有角度偏移。
15.根据权利要求14所述的电子封装，其中所述芯片封装在与所述上表面正交的垂直轴上相对于所述封装基板旋转大致45度。
16.根据权利要求14所述的电子封装，其中所述第一高速接口电路裸晶包括直接面向所述封装基板的顶点的第一边缘，并且沿着所述第一边缘设置有第一排I/O焊盘，所述第一高速接口电路裸晶包括垂直于所述第一边缘的第二边缘，其中沿着所述第二边缘设置有第二排I/O焊盘。
17.根据权利要求16所述的电子封装，其中沿着在所述封装基板的所述顶点处接合的两个侧边布置有第一组焊球，并且其中所述第一排I/O焊盘分别通过所述封装基板的所述上表面上的所述四个象限的其中一个象限内的多个第一迹线电连接到所述第一组焊球。
18.根据权利要求17所述的电子封装，其中沿着在所述封装基板的所述顶点处接合的所述两个侧边其中之一布置有第二组焊球，并且其中所述第二排I/O焊盘分别通过所述封装基板的所述上表面上的所述四个象限中的所述其中一个象限内的多个第二迹线电连接到所述第二组焊球。
19.根据权利要求12所述的电子封装，其中所述第一高速接口电路裸晶包括第一串行器/串并转换器电路块。
20.根据权利要求12所述的电子封装，还包括：
靠近所述第一高速接口电路裸晶的第二高速接口电路裸晶，其中所述第二高速接口电路裸晶包括第二串行器/串并转换器电路块。
21.根据权利要求20所述的电子封装，其中所述第一高速接口电路裸晶通过再分配层结构电连接到所述第二高速接口电路裸晶。
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