CN110459174B

CN110459174B - Memory-in-pixel display

Info

Publication number: CN110459174B
Application number: CN201910381388.7A
Authority: CN
Inventors: I·克内兹; 郭天健; 林盈侃; 王碧琳; 全刚勋; M·H·克莱恩; 裴浩弼; J·A·多明格斯-卡巴雷罗; 黃俊尧; S·F·毛希丁; 汪柏廷
Original assignee: Apple Inc
Current assignee: Apple Inc
Priority date: 2018-05-08
Filing date: 2019-05-08
Publication date: 2022-06-07
Anticipated expiration: 2039-05-08
Also published as: WO2019217242A1; JP2021523407A; CN114783368B; CN114783368A; KR102321174B1; EP3791380A1; TW201947575A; JP2022191226A; CN110459174A; TWI732213B; KR20200140386A

Abstract

The invention provides a memory in pixel display. An electronic display is disclosed that may include an active area having first pixels formed in the active area, wherein the first pixels emit light in response to image data. The electronic display may also include a controller to transmit the image data to the first pixel. The first pixel may include: an organic light emitting diode that emits light in response to the image data, a memory that digitally stores the image data received from the controller, and a driver circuit that receives the image data from the memory. The driver circuit may cause the organic light emitting diode to emit light in response to the image data.

Description

Memory-in-pixel display

Disclosure of Invention

The following sets forth a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these particular embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, the present disclosure may encompass a variety of aspects that may not be set forth below.

Methods and systems for reducing the amount of bandwidth or concurrent transmission of image data that is transmitted and processed to prepare an image for presentation on an electronic display by implementing memory in pixels of the electronic display may provide significant value. Such an implementation of memory in a pixel may allow for elimination of a frame buffer associated with an electronic display. Having memory in the pixels also reduces the design complexity of the electronic display, since the less image data that is simultaneously transmitted to the pixel array of the electronic display, the simpler the electronic display can be designed. For example, the pixels may be programmed into smaller groups because the memory in the pixels stores values until the presentation time of the image.

The present disclosure describes an electronic display having one or more pixels that include a memory and a driver that can help reduce the bandwidth associated with transmitting and processing image data for presentation on the electronic display. Including a memory in the pixel may enable storing the image data before outputting the image data to the light emitting portion of the pixel. Thus, in-pixel memory may reduce or, in some cases, eliminate reliance on frame buffers in electronic displays by acting as a separate frame buffer for the pixels. The in-pixel memory may be used in conjunction with a driver to cause the emitted light portion of the pixel to emit light.

Drawings

Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

fig. 1 is a schematic block diagram of an electronic device according to an embodiment;

FIG. 2 is a perspective view of a watch representing an embodiment of the electronic device of FIG. 1, according to an embodiment;

FIG. 3 is a front view of a tablet device representing an embodiment of the electronic device of FIG. 1, according to an embodiment;

FIG. 4 is a front view of a computer representing an embodiment of the electronic device of FIG. 1, according to an embodiment;

fig. 5 is a block diagram of a display system of the electronic device of fig. 1, according to an embodiment;

fig. 6 is a block diagram of a pixel array of the display system of fig. 5, according to an embodiment;

fig. 7 is a block diagram of an embodiment of the pixel array of fig. 6, according to an embodiment;

fig. 8 is a block diagram of a pixel of the pixel array of fig. 6 that emits light according to a binary pulse width modulation emission scheme, according to an embodiment;

fig. 9 is a block diagram of an embodiment of a pixel of the pixel array of fig. 6 emitting light according to a single pulse width modulation emission scheme, according to an embodiment;

fig. 10 is a block diagram of another embodiment of a pixel of the pixel array of fig. 6 emitting light according to a pulse density modulated emission scheme, according to an embodiment;

FIG. 11 is a timing diagram of a programming sequence performed by a column driver of the display system of FIG. 5, according to an embodiment;

fig. 12 is a circuit of a first embodiment of a sub-pixel of the pixel array of fig. 6 having a current driver, according to an embodiment;

FIG. 13 is a circuit of a second embodiment of a sub-pixel of the pixel array of FIG. 6 having a hybrid driver and having a memory, according to an embodiment;

fig. 14 is a timing diagram of control signals for operating the subpixels of fig. 13 to display an image according to an embodiment;

FIG. 15 is a graph illustrating currents and voltages generated by simulating transmission of image data corresponding to a binary pulse width modulation emission scheme to the sub-pixel of FIG. 12, in accordance with an embodiment;

FIG. 16 is a graph illustrating currents and voltages generated by simulating transmission of image data corresponding to a binary pulse width modulation emission scheme to the sub-pixels of FIG. 13, in accordance with an embodiment;

FIG. 17 is a circuit diagram of a memory circuit coupled to the sub-pixel of FIG. 12 according to an embodiment;

FIG. 18 is a circuit diagram of an embodiment of the memory circuit of FIG. 17 coupled to the subpixel of FIG. 12 implementing a global anode, according to an embodiment;

FIG. 19 is a process for operating the sub-pixels of FIG. 18 according to an embodiment;

FIG. 20 is a circuit diagram of an embodiment of the subpixel of FIG. 18 implementing a global cathode according to an embodiment;

FIG. 21 is a circuit diagram of an embodiment of the memory circuit of FIG. 13 according to an embodiment;

FIG. 22 is a process for operating the memory circuit of FIG. 21 according to an embodiment;

FIG. 23 is a circuit diagram of an embodiment of the memory circuit of FIG. 13 according to an embodiment;

fig. 24A is a bit plane diagram corresponding to no reordering implemented in the memory circuit of fig. 23, according to an embodiment;

FIG. 24B is an error map corresponding to no reordering implemented in the memory circuit of FIG. 23, according to an embodiment;

FIG. 24C is a bit plane diagram corresponding to two reordering implemented in the memory circuit of FIG. 23, according to an embodiment;

FIG. 24D is an error map corresponding to two reordering implemented in the memory circuit of FIG. 23, according to an embodiment;

FIG. 24E is a bit plane diagram corresponding to the three reordering implemented in the memory circuit of FIG. 23, according to an embodiment;

FIG. 24F is an error map corresponding to three reordering implemented in the memory circuit of FIG. 23, according to an embodiment;

FIG. 24G is a bit plane diagram corresponding to an ideal case of reordering implemented in the memory circuit of FIG. 23, according to an embodiment;

FIG. 24H is an error map corresponding to an ideal case of reordering implemented in the memory circuit of FIG. 23, according to an embodiment;

fig. 25 is a bit plane diagram showing the bit plane diagram of fig. 24C over time and including additional color channels, according to an embodiment;

fig. 26 is a timing diagram illustrating loading and firing processes associated with the third quadrant of the bit plane diagram of fig. 25, according to an embodiment;

FIG. 27 is a circuit diagram of an embodiment of the memory circuit of FIG. 23 implemented for a digital mirror display (digital mirror display), according to an embodiment;

fig. 28 is a circuit diagram of an embodiment of the pixel of fig. 25 for a liquid crystal display according to an embodiment;

FIG. 29 is a block diagram comparing the system display of FIG. 5 with a display system having a smart buffer outside of an active area of an electronic display, according to an embodiment;

FIG. 30 is a circuit diagram of an embodiment of the memory circuit of FIG. 13 for the smart buffer of FIG. 29, according to an embodiment; and is

Fig. 31 is a circuit diagram of a third embodiment of a sub-pixel of the pixel array of fig. 6 for a display system having the smart buffer of fig. 29, according to an embodiment.

Detailed Description

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

When introducing elements of various embodiments of the present disclosure, the articles "a" and "an" and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

Electronic displays are present in many electronic devices, from mobile phones to computers, televisions, automobile dashboards, and the like. Electronic displays have achieved increasingly higher resolution by reducing the size of individual pixels. However, increasing resolution may increase the difficulties associated with: managing an increased amount of image data associated with an increased resolution of processing by the processing circuitry prior to displaying the image, such as by causing an increase in power consumption to process the increased amount of image data. In addition, increasing the resolution may increase the bandwidth for transferring image data from the processing circuitry to the pixel array for rendering the image, as more image data is used to transfer the same image at higher electronic display resolutions.

Embodiments of the present disclosure relate to systems and methods for implementing in-pixel memory circuitry that can be used as a separate frame buffer for each pixel, which can reduce reliance on frame buffers external to the pixel array and drive circuitry of an electronic display. The memory may be implemented in a pixel circuit including a Light Emitting Diode (LED). Organic Light Emitting Diodes (OLEDs) represent one type of LED that may be found in a pixel, but other types of LEDs may also be used in the pixel circuit or light emitting components may be used, such as components for supporting Liquid Crystal Displays (LCDs), plasma display panels, and/or dot matrix displays.

The systems and methods of the present disclosure for implementing in-pixel memory circuits may reduce the transmission bandwidth of image data to a pixel array for display because the pixels may store the image data in memory. In this way, the dependency of a frame buffer external to the pixel for temporarily storing image data is reduced because the pixel has its own memory to store its own image data before displaying the image data.

A general description of a suitable electronic device that may include a self-emissive display, such as an LED (e.g., OLED) display, is provided, along with corresponding circuitry of the present disclosure. OLEDs represent one type of LED that can be found in self-emitting pixels, but other types of LEDs can also be used.

For ease of illustration, FIG. 1 shows an electronic device 10 that includes an electronic display 18. As described in more detail below, the electronic device 10 may be any suitable electronic device, such as a computer, mobile phone, portable media device, tablet computer, television, virtual reality headset, vehicle dashboard, and the like. Accordingly, it should be noted that FIG. 1 is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10. The electronic device 10 may include, among other things, a processing core complex 12, such as a system on a chip (SoC) and/or processing circuitry, a storage device 14, a communication interface 16, an electronic display 18, an input fabric 20, and a power supply 22. The various components described in fig. 1 may include hardware elements (e.g., circuitry), software elements (e.g., a tangible, non-transitory computer-readable medium storing instructions), or a combination of hardware and software elements. It should be noted that the various depicted components may be combined into fewer components or separated into additional components.

As shown, the processing core complex 12 is operatively coupled to a storage device 14. Thus, the processing core complex 12 executes instructions stored in the storage device 14 to perform operations such as generating and/or transferring image data. As such, the processing core complex 12 may include one or more general purpose microprocessors, one or more Application Specific Integrated Circuits (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof. Using pixels containing light emitting components (e.g., LEDs, OLEDs), the electronic display 18 may display images generated by the processing core complex 12.

In addition to instructions, the storage device 14 may also store data to be processed by the processing core complex 12. Thus, in some embodiments, storage device 14 may include one or more tangible, non-transitory computer-readable media. The storage device 14 may be volatile and/or nonvolatile. For example, storage device 14 may include Random Access Memory (RAM) and/or Read Only Memory (ROM), rewritable non-volatile memory (such as flash memory, hard drives, optical disks, etc.), or any combination thereof.

As shown, the processing core complex 12 is also operatively coupled with a communication interface 16. In some embodiments, communication interface 16 may facilitate the transfer of data with another electronic device and/or a network. For example, the communication interface 16 (e.g., a radio frequency system) may enable the electronic device 10 to communicatively couple to a Personal Area Network (PAN), such as a bluetooth network, a Local Area Network (LAN), such as an 1622.11x Wi-Fi network, and/or a Wide Area Network (WAN), such as a 4G or Long Term Evolution (LTE) cellular network.

Additionally, as depicted, the processing core complex 12 is also operatively coupled to a power source 22. In some embodiments, the power source 22 may provide power to one or more components in the electronic device 10 (such as the processing core complex 12 and/or the electronic display 18). Accordingly, the power source 22 may include any suitable energy source, such as a rechargeable lithium-polymer (Li-poly) battery and/or an Alternating Current (AC) power converter.

As shown, the electronic device 10 is also operatively coupled with one or more input structures 20. In some embodiments, the input structures 20 may facilitate user interaction with the electronic device 10, for example, by receiving user input. Thus, the input structures 20 may include buttons, a keyboard, a mouse, a touch pad, and the like. Additionally, in some embodiments, the input structure 20 may include touch sensing components located in the electronic display 18. In such embodiments, the touch sensing component may receive user input by detecting the occurrence and/or location of an object touching the surface of the electronic display 18.

In addition to enabling user input, the electronic display 18 may include a display panel having one or more display pixels. As described above, the electronic display 18 may control light emitted from the display pixels to present a visual representation of information, such as a Graphical User Interface (GUI) of an operating system, an application interface, a still image, or video content, through the display frame based at least in part on the corresponding image data. As depicted, the electronic display 18 is operably coupled to the processing core complex 12. In this manner, the electronic display 18 may display the frame based at least in part on the image data generated by the processing core complex 12. Additionally or alternatively, the electronic display 18 may display frames based at least in part on image data received via the one or more communication interfaces 16 and/or the input structure 20.

As can be appreciated, the electronic device 10 may take a variety of different forms. As shown in fig. 2, the electronic device 10 may take the form of a watch 30. For purposes of illustration, watch 30 may be any Apple available from Apple Inc. (Apple Inc.)

The model number. As shown in the figureThe watch 30 is shown to include a case 32 (e.g., an outer shell). In some embodiments, the housing 32 may protect the internal components from physical damage and/or shield the internal components from electromagnetic interference (e.g., encapsulating the components). Strap 34 may enable watch 30 to be worn on an arm or wrist. Electronic display 18 may display information related to the operation of watch 30. The input structures 20 may enable a user to enable or disable the watch 30, navigate a user interface to a home screen, navigate a user interface to a user-configurable application screen, activate voice recognition features, provide volume control, and/or switch between vibrate and ringer modes. As shown, the input structure 20 may be accessible through an opening in the housing 32. In some embodiments, the input structure 20 may include, for example, an audio jack that connects to an external device.

The electronic device 10 may also take the form of a tablet device 40, as shown in FIG. 3. For illustrative purposes, the tablet device 40 may be any available from Apple Inc. (Apple Inc.)

The model number. Depending on the size of the tablet device 40, the tablet device 40 may be used as a handheld device such as a mobile phone. Tablet device 40 may include a housing 42 through which a number of input structures 20 may protrude. In some examples, the input structure 20 may include a hardware keyboard (not shown). The housing 42 also holds the electronic display 18. Input structures 20 may enable a user to interact with a GUI of tablet device 40. For example, the input structure 20 may enable a user to type a Rich Communication Service (RCS) text message, a Short Message Service (SMS) text message, or make a telephone call. The speaker 44 may output the received audio signals, and the microphone 46 may capture the user's voice. Tablet device 40 may also include a communication interface 16 to enable tablet device 40 to connect to another electronic device via a wired connection.

FIG. 4 illustrates a computer 48 that represents another form that the electronic device 10 may take. For purposes of illustration, the computer 48 may be any available from Apple Inc. (Apple Inc.)

Or

The model number. It should be appreciated that the electronic device 10 may also take the form of any other computer, including a desktop computer. The computer 48 shown in FIG. 4 includes an electronic display 18 and an input structure 20 including a keyboard and a touchpad. The communication interface 16 of the computer 48 may include, for example, a Universal Serial Bus (USB) connection.

In any case, as described above, operating the electronic device 10 to communicate information by displaying images on its electronic display 18 typically consumes power. Additionally, as noted above, electronic device 10 typically stores a limited amount of power. Thus, to help improve power consumption efficiency, in some embodiments, the electronic device 10 may include an electronic display 18 that implements in-pixel memory as a method for reducing or eliminating the use of an external frame buffer when displaying an image, and thus reduces the power consumed using a frame buffer when displaying an image and/or reduces the bandwidth of image data received into the electronic display 18. In some cases, an internal frame buffer may be used (e.g., located in electronic display 18, such as in a display driver integrated circuit of electronic display 18) instead of or in addition to in-pixel memory technology. By implementing in-pixel memory or related techniques, the electronic display 18 can be programmed with a smaller bandwidth of image data, thereby further achieving power consumption savings. In addition, electronic display 18 using in-pixel memory or an on-board frame buffer may have a less complex design than electronic display 18 without in-pixel memory or an on-board frame buffer. These benefits may be realized because the pixel retains the data transferred to its memory until new image data is written to the memory.

Similarly, portions of the image data may program a subset of the pixels associated with the electronic display 18 at once. The image to be displayed is usually converted into digital data or image data so that the image can be electronically displayedThe components of the display 18 are explained. In this manner, the image data itself may be divided into small "pixel" portions, each of which may correspond to a pixel portion of the electronic display 18, or a pixel portion of a display panel corresponding to the electronic display 18. In some embodiments, the image data is represented by a combination of red-green-blue light, such that what appears to be a single color is actually three sub-pixels that emit a proportion of red, green, and blue light, respectively, to produce the single color. In this way, the numerical value or image data quantifying the combination of red-green-blue light may correspond to a digital luminance level or gray scale that correlates the luminance intensity (e.g., brightness) of the colors of the image data for these particular subpixels. It will be appreciated that the number of gray levels in an image generally depends on the number of bits used to represent the gray levels in a particular electronic display 18, which may be represented as 2^NA number of gray levels, where N corresponds to the number of bits used to represent the gray level. By way of example, in embodiments where the electronic display 18 uses 8 bits to represent gray levels, the gray levels range from 0 (black or no light) to 255 (maximum light and/or full light), for a total of 256 potential gray levels. Similarly, the use of a 6-bit electronic display 18 may use 64 gray levels to represent the intensity of luminescence of each sub-pixel.

Having memory in the pixels of the electronic display 18 enables image data to be transferred to the sub-pixels associated with one color without having to transfer the image data to additional sub-pixels associated with a second color at the same time. For purposes of this disclosure, subpixels are discussed in terms of red-green-blue color channels, where a color channel is a layer of image data that includes gray levels of a single color that, when combined with additional color channels, produces an image of the true or desired color, and where the image data of the color channels corresponds to the image data transmitted to the subpixels for the color channels. However, it should be understood that any combination of color channels and/or sub-pixels may be used, such as blue-green-red, cyan-magenta-yellow, and/or cyan-magenta-yellow-black.

To aid in illustration, a display system 50 associated with the electronic display 18 that does not implement in-pixel memory, and a display system 52 associated with the electronic display 18 that implements in-pixel memory are shown in FIG. 5, which may be separately implemented in the electronic device 10. The display system 50 includes: a timing controller 54 for receiving image data 56, a frame buffer 58, a row driver 60, and a column driver 62 communicatively coupled to timing controller 54 by a communication link 64, and a pixel array 66 that receives control signals from column driver 62 and row driver 60 to produce an image on electronic display 18. Further, the display system 52 includes: a timing controller 54 for receiving image data 56, a row driver 60 and a column driver 62 communicatively coupled to timing controller 54 by a communication link 68, and a pixel array 69 implementing in-pixel memory technology that receives control signals from column driver 62 and row driver 60 to produce an image on electronic display 18.

In preparation for displaying an image, display system 50 may receive image data 56 at timing controller 54. Timing controller 54 may receive and use image data 56 to determine clock signals and/or control signals to control the provision of image data 56 to pixel array 66 via column drivers 62 and row drivers 60. Additionally or alternatively, in some embodiments, image data 56 is received by frame buffer 58.

In either case, frame buffer 58 may serve as an external memory for timing controller 54 to store image data 56 before outputting the image data to column driver 62 and/or row driver 60. The timing controller 54 may output the image data 56 from the frame buffer 58 to the column driver 62 and/or the row driver 60 via a communication link 64.

Communication link 64 is large enough (e.g., determined by the transmission bandwidth of the image data) to simultaneously transmit image data 56 associated with all channels to row driver 60 and/or column driver 62, e.g., image data 56 associated with the red, green, and blue channels. In this manner, the communication link 64 simultaneously transmits image data 56 associated with respective pixels of the pixel array 66 for the red, green, and blue color channels. Column driver 62 and row driver 60 may transmit control signals to pixel array 66 based on image data 56. In response to the control signals, the pixel array 66 emits light to convey an image at different luminances, or brightnesses indicated by gray levels ranging from, for example, 0 to 255.

However, the display system 52 receives image data 56 at the timing controller 54. Timing controller 54 may use image data 56 to determine a clock signal for providing image data 56 to in-pixel memory pixel array 69. Timing controller 54 transmits image data 56 to row driver 60 and/or column driver 62 to program the memory of pixel array 69 with digital data signals associated with image data 56, wherein the digital data signals indicate the emission brightness/gray scale of the pixels of pixel array 69.

By implementing an in-pixel memory storage system and method, display system 52 can reduce the bandwidth of signals transmitted over communication link 68, for example when compared to the bandwidth of signals transmitted over communication link 64. In some cases, a single channel of image data 56 may be transmitted over communication link 64 (e.g., a red channel), as opposed to all channels (e.g., red-green-blue channels) being transmitted simultaneously to pixel array 66. In this manner, communication link 68 transmits image data 56 associated with respective pixels of pixel array 66 for the red, green, and blue channels at different times, resulting in a reduction in the overall bandwidth of signals used to transmit image data 56. Reducing the overall bandwidth of the communication link 68 may result in a reduction in power consumption of the electronic device 10, as processing less data (e.g., a single channel of image data) at a given time may consume less processing resources than processing more data (e.g., three channels of image data).

To illustrate the operation of the pixel array 69 with in-pixel memory to display images, an example of a display system 52A implementing in-pixel memory is shown in FIG. 6 having a timing controller 54 linked to a row driver 60 and/or a column driver 62 by a communication link 68. Display system 52A includes an L row by M column array of pixels 69 in which one or more pixels 70 each have a subpixel 72 corresponding to a color channel of electronic display 18, e.g., a red subpixel 72R, a green subpixel 72G, and a blue subpixel 72B, where each subpixel 72 includes a memory 78 for storing up to N bits and a Driver (DRV)80 for operating subpixel 72 to emit light, as described in fig. 6. It should be understood that the depicted display system 52A is merely illustrative and not limiting. For example, in some embodiments, pixel array 69 may include subpixels 72 to emit various amounts of cyan, yellow, and magenta light corresponding to cyan-yellow-magenta channels instead of or in addition to red-green-blue channels.

In explaining the operation of display system 52A, timing controller 54 receives image data 56 corresponding to a next image to be displayed on an electronic display having a pixel array 69. Timing controller 54 generates control signals and/or timing signals in response to image data 56 and transmits signals related to the rows of operational pixels 70 to row driver 60 and signals related to the columns of operational pixels 70 to column driver 62. The row driver 60 is responsive to signals associated with the image data 56 transmitted from the timing controller 54 and generates an emission control signal 82 and a write control signal 84 for each red-green-blue (RGB) channel. The column driver 62 also generates image data 86 to be transferred to the memory 78 of each pixel 70 in response to signals associated with the image data 56 transferred from the timing controller 54. Column driver 62 may generate image data 86 in response to signals associated with image data 56 and/or image data 56, however, in some embodiments, image data 56 is transmitted to each pixel 70 as image data 86. The column driver 62 generates data of size N bits for each sub-pixel 72 to match the size of the memory 78 (which is also of size N bits).

In general, through the transmission of emission control signals 82, write control signals 84, and image data 86, pixels 70 are operated to emit light to produce an image on electronic display 18. Each pixel 70 receives a respective emission control signal 88 of emission control signals 82 transmitted from row driver 60, a respective three write control signals 90 of write control signals 84, and a respective image data 92 for a channel of pixel 70, e.g., N-bit image data for the red channel (image data-R) 92R, N-bit image data for the green channel (image data-G) 92G, and N-bit image data for the blue channel (image data-B) 92B. The write control signal 84 may enable the memory 78 of the pixel 70 to be programmed with image data 86 transmitted by the column driver 62. Further, a corresponding emission control signal 88 of the emission control signals 82 may control whether the pixel 70 is capable of emitting light. The emission control signal 88 is transmitted to the corresponding pixel 70 of the column. The enabled emission control signal 88 may activate the driver 80, causing digital image data 92 to be transferred from the memory 78 to a light emitting portion of the pixel 70, such as a Light Emitting Diode (LED) associated with the sub-pixel 72, which uses the analog data signal to generate light emitted from the pixel 70. In the depicted embodiment, the columns of pixels 70, e.g., pixels 70R1C1, R2C1, R3C 1-RLC 1 in the first column receive the same transmit control signal 88. Image data 92 transmitted to the pixels 70 causes the pixels 70 to emit light of the entire color and/or brightness.

The perceived color emitted from the pixel 70 changes based on the light emitted from each of the three channels of the pixel 70 (i.e., the light emitted from each respective sub-pixel). For example, operating each subpixel to output a luminance of 0 makes the pixel 70 appear to be off, while operating the red subpixel 72R to output a luminance of 100%, operating the green subpixel 72G to output a luminance of 50%, and operating the blue subpixel 72B to output a luminance of 0% may cause the pixel 70 to emit the overall color perceived as orange. Thus, data is rendered and transmitted to each sub-pixel 72 to correspond to a separate color channel of the pixel 70.

Implementing memory 78 in pixel 70 enables image data 92 to be programmed into pixel 70 prior to the desired presentation time of the image. In some embodiments, the write control signal 90 being enabled causes the memory 78 to clear (or overwrite) the stored image data 92, and the memory 78 may be caused to retain the programmed image data 92 without enabling the write control signal 90. For example, to write new image data, the write control signal-R90R may cause the memory 78 of the red subpixel 72R to clear, thereby enabling the writing of new image data to be loaded into the memory 78, i.e., the image data-R92R. In this example, write control signal-B90B is not enabled, so memory 78 of blue subpixel 72B is not cleared and continues to hold its programmed image data, i.e., image data-B92B. Having the memory 78 in the pixel 70 is an improvement over display technology and processing technology because the memory 78 enables writing portions of the image data 86 at once instead of an entire frame of data, resulting in improved use of available bandwidth for transferring image data for display on the electronic display 18, and improved power consumption for processing image data, as explained previously with reference to FIG. 5.

In pixel array 69, image data 86 is transferred from column drivers 62 to subpixels 72 via a direct communication coupling (e.g., via communication coupling 94). In some embodiments, multiplexing circuitry may be used to control the transmission of image data 86 to subpixels 72 such that column driver 62 arbitrates the transmission of image data 98 to subpixels 72 using a multiplexed control signal, e.g., where red subpixel 72R may not receive image data 98 at the same time as blue subpixel 72B or green subpixel 72G.

In detail, an example embodiment of a display system 52B associated with an electronic display 18 implementing in-pixel memory is shown in fig. 7, which includes a timing controller 54 linked to a row driver 60 and a column driver 62 by a communication link 68. Similar to the display system 52A shown in fig. 6, the display system 52B includes an L row by M column array 69 of pixels, wherein one or more pixels 70 each have a sub-pixel 72, such as a red sub-pixel 72R, a green sub-pixel 72G, and a blue sub-pixel 72B, wherein each sub-pixel 72 includes a memory 78 for storing up to N bits and a Driver (DRV)80 for operating the sub-pixel 72 to emit light, as described in fig. 6. It should be understood that the depicted display system 52B is merely illustrative and not limiting. It should be noted that the functionality and/or description of display system 52 is common to both fig. 6 and 7, as relied upon herein.

In the exemplary embodiment of display system 52B in FIG. 7, pixel array 69 includes multiplexing circuitry 96 that receives image data 98 of size N bits from column driver 62. The multiplexing circuits 96 are responsive to respective multiplexing control signals (MUX control signals) 100 of multiplexing control signals 101. The MUX control signals 100 may cause the multiplexing circuit 96 to output data to the subpixels 72 of the pixels 70. In this manner, by the emission of MUX control signals 100, column driver 62 may operate to program sub-pixels 72 (e.g., one color channel) of pixels 70 at a time via, for example, communication coupling 94. For pixel array 69, various embodiments of sub-pixel 72 circuitry may be used.

Examples of embodiments of sub-pixels 72 implementing in-pixel memory technology include memory 78, driver 80, current source 102, LED 103, switch 104, and counter 105, where sub-pixels 72 receive various signals including image data 98, bit plane clock 106, reset signal 108, common voltage 110, first reference voltage 112, second reference voltage 114, and data clock 116, as shown in fig. 8. It should be understood that the depicted sub-pixels 72 are merely illustrative and not limiting. For example, the memory 78 is depicted as a 12-bit register, but may be any suitable memory circuit for storing any suitable number of bits.

The depicted subpixels 72 may emit according to a binary pulse width modulation emission scheme. To explain the operation of subpixel 72, image data 98 is transferred from, for example, column driver 62 to memory 78. Additionally or alternatively, image data 92/image data 56 or any suitable image data may be transferred to memory 78 for storage. Upon receiving image data 98, memory 78 stores image data 98 clocked by data clock 116. Image data 98 may be represented by binary data such that any given bit may be equal to either a zero "0" or a one "1", where 0 corresponds to a logical low voltage value of the system and 1 corresponds to a logical high voltage value of the system. Based on the timing signal generated by the combination of the counter 105 and the bit plane clock 106, the memory 78 may output the image data 98 to the switch 104, for example, bit by bit in order from the least significant bit to the most significant bit.

As shown, bit plane clock 106 has a timing period that increases with time to correspond to the level of influence of a particular bit in image data 98. In this manner, the least significant bits of image data 98 may be associated with a smaller timing period than the most significant bits of image data 98.

When memory 78 outputs image data 98, such as on a rising edge of bit plane clock 106, image data 98 operates switch 104 to open or close. Bit 0 causes switch 104 to open, thereby causing LED 103 to emit no light, and bit 1 causes switch 104 to close, thereby causing LED 103 to emit light. The operation of the switch 104 occurs at different emission periods as a way of modulating the emission of light from the LED 103, such that the perceived brightness of the sub-pixel 72 changes as the modulation changes. Therefore, by the relationship between the image data 98 output from the memory 78 and the switch 104, the image data 98 equal to "000000000000" may cause the LED 103 not to emit light, and the image data 98 equal to "101011000111" may cause the LED 103 to be perceived as brighter. Image data 98 equal to "101011000111" may be perceived as brighter because subpixel 72 emits light in response to each logic high value of "1", by which switch 104 is activated to allow light to be emitted. The more times the switch 104 is activated during the emission period, the brighter the pixel is perceived as the more light is emitted over time (e.g., light is emitted in response to a "1" and light is not emitted in response to a "0"). In this manner, image data 98 may be derived from the desired gray levels of subpixels 72, rather than an accurate binary representation of the gray levels. It should be noted, however, that there may be cases where: the desired gray level of subpixel 72 is indeed equal to the binary representation transmitted via image data 98.

When switch 104 is closed, an electrical connection is made between common voltage 110 and first reference voltage 112. This causes current from the current source 102 to be transmitted through the LED 103, thereby enabling light to be emitted from the sub-pixel 72. Accordingly, the emission period of the sub-pixel 72 may be varied to control the perceived light emitted from the sub-pixel 72, where the emission period corresponds to the bit placement (e.g., most significant bit, least significant bit) of the image data 98 stored in the memory 78 such that the closer the bit of the image data 98 is to the location of the most significant bit, the longer the emission period corresponding to that bit of the image data 98. Once the counter 105 counts up to 11, the counter 105 restarts and causes the bit-plane clock 106 to restart its timing interval, e.g., corresponding to the next least significant bit after the last most significant bit transmission period. Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to vary the total current value used to control the light emitted from the LED 103. For example, the second reference voltage 114 may increase the sensitivity of the LED 103 to current changes, such that a lower current value may be used to cause light to be emitted from the LED 103, or to enable the LED 103.

This emission scheme is commonly referred to as a binary pulse width modulation emission scheme for subpixels 72 because image data 98 is binary data selected to modulate the light emission from subpixels 72 in a manner that changes the perceived brightness of subpixels 72. Graph 118 depicts an emission period of subpixel 72 resulting from a binary pulse width modulation emission scheme. Under the use of a binary pulse width modulation emission scheme, the subpixels 72 are operated to vary the perceived brightness of light emitted by different emission periods of light. As depicted by graph 118, image data 98 received by subpixel 72 is represented by five-bit binary data. Thus, when the image data 98 is equal to 01111, the sub-pixel 72 emits light corresponding to a first range 120 having an emission period 124A for a least significant bit and

emission periods

124B, 124C, and 124D for subsequent bits. In this embodiment, the least significant bit of the image data 98 from the memory 78 operates the switch 104 first, and thus this is why the least significant bit corresponds in time to the first transmission period 124A. In this way, between the transmissions of the bits for operating the switch 104, the transmission is temporarily stopped, as seen with respect to the no transmission period between the first transmission period 124A and the transmission period 124B. Further, when the image data 98 equals 11111, the emission period for the sub-pixel 72 corresponds to the second range 122, which is equal to the first range 120 plus the last emission period 124E corresponding to the most significant bit (e.g., because the most significant bit is now enabled as 1).

When the binary pulse width modulation transmission scheme is followed, image data 98 with data 01111 is perceived as less bright than image data 98 with data 11111, which is the way light is perceived by an observer of electronic display 18. This is because the more emission periods occur during the total emission period (e.g., as indicated by all 1s in image data 98, i.e., 11111), the brighter the light emitted from the sub-pixel 72 is perceived. As such, if sub-pixel 72 is to be emitted for the last emission period 124E other than the first range 120 (e.g., if the most significant bit of image data 98 is a 1), sub-pixel 72 may be perceived as brighter on electronic display 18 than sub-pixel 72 emitted for the first range 120 alone.

Another example of an embodiment of a sub-pixel 72 including a memory 78, a driver 80, a current source 102, an LED 103, a switch 104, a counter 130, and a comparator 132 is shown in fig. 9, where the sub-pixel 72 receives various signals including image data 98, a gray scale clock 134, a common voltage 110, a first reference voltage 112, a second reference voltage 114, and a data clock 116. It should be understood that the depicted sub-pixels 72 are merely illustrative and not limiting. For example, the memory 78 is depicted as an 8-bit register, but may be any suitable memory circuitry for storing any suitable number of bits.

The depicted sub-pixels 72 with in-pixel memory may emit according to a single pulse width emission scheme. To explain the operation of subpixels 72, image data 98 is transferred from, for example, column driver 62 to memory 78 for storage. Additionally or alternatively, image data 92/image data 56 or any suitable image data may be transferred to memory 78 for storage. In some embodiments, image data 98 may be clocked into memory 78 by data clock 116, for example on the rising edge of data clock 116. Image data 98 communicated to subpixel 72 may correspond to a desired gray scale level at which subpixel 72 will emit light. Using image data 98 stored in memory 78, comparator 132 determines whether the current number represented by counter 130 is less than or equal to image data 98 in memory 78. In other words, the counter 130 counts up to the number indicated by the image data 98, and in response to the number indicated by the counter 130 satisfying a condition (e.g., less than or equal to the number indicated by the image data 98), the comparator 132 outputs a control signal to close the switch 104 when the condition is satisfied. When the condition is not satisfied, the comparator 132 does not output the control signal and turns off the switch 104. Additionally or alternatively, the comparator 132 may enable the disable control signal to cause the switch 104 to open. For example, if the memory 78 stores a binary sequence 10110101 corresponding to a number 181, the comparator 132 will check whether the counter 130 has counted to the number 181, and when the counter 130 exceeds the number 181, the comparator 132 transmits a signal to open the switch 104 to stop transmission.

When switch 104 is closed, an electrical connection is made between common voltage 110 and first reference voltage 112. This causes current from current source 102 to be transmitted through LED 103, causing light to be emitted from subpixel 72. Thus, by changing the number indicated by image data 98, the emission period of subpixel 72 may be changed to control the perceived light emitted from subpixel 72. Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to vary the total current value used to control the light emitted from the LED 103. For example, the second reference voltage 114 may increase the sensitivity of the LED 103 to current changes, such that a lower current value may be used to cause light to be emitted from the LED 103, or to enable the LED 103.

The counter 130 counts from 0 to 255 and increments based on the gray scale clock 134, for example, at the rising edge of the gray scale clock 134. The period of the gray scale clock 134 represents the time difference between increments of gray scale levels of the electronic display 18, e.g., the emission difference between the emission gray scale level 100 and the emission gray scale level 101. In this manner, the counter 130 counts up to the number represented by the image data 98 stored in the memory 78, thereby subsequently causing emission to occur within a time period corresponding to the desired gray scale level. The counter 130 may continue to count beyond the number represented by the image data 98 stored in the memory 78 to a maximum value (e.g., 255) and may resume counting at a minimum value (e.g., 0). Thus, in some embodiments, the count range of the counter 130 may be defined by the design of the counter 130, for example, by a plurality of registers and/or logic components included in the counter 130. By the time counter 130 restarts counting at 0, additional image data 98 may be stored in memory 78 to begin comparison during the next emission period of the gray scale associated with additional image data 98.

By following this emission scheme, the sub-pixels 72 may follow a single pulse width modulation emission scheme. A representation of light emission from a subpixel 72 following a single pulse width modulation emission scheme is shown in graph 136. Graph 136 includes an actual transmission period 138 and a total transmission period 140. Total emission period 140 corresponds to the total length of emission represented by the maximum number (e.g., 255) transmitted as image data 98, and may correspond to the maximum perceived brightness of light emitted from subpixel 72. The actual emission period 138 corresponds to a period in which the sub-pixel 72 emits light according to a number less than the maximum value (e.g., from the counter 130) transmitted as the image data 98. The counter 130 increments from 0 to 255, which takes the amount of time represented by the total emission period 140, while the comparator 132 enables light to be emitted for the amount of time represented by the actual emission period 138. In this way, the sub-pixels 72 may emit light having different perceived brightness.

Another example of an embodiment of a subpixel 72 including a memory 78, a driver 80, a current source 102, an LED 103, a switch 104, an accumulator 150, and an adder 152 is shown in fig. 10, where subpixel 72 receives various signals including an emission clock 154, image data 98, a common voltage 110, a first reference voltage 112, a second reference voltage 114, and a data clock 116. It should be understood that the depicted sub-pixels 72 are merely illustrative and not limiting. For example, memory 78 is depicted as being capable of storing 8 bits of image data 98, but may be any suitable memory circuit for storing any suitable number of bits.

The depicted sub-pixels 72 with in-pixel memory may emit according to a pulse density modulated emission scheme. In a pulse density modulated emission scheme, each pulse has a constant emission light and a constant emission period, but has a variable separation interval between pulses-where the brighter light emitted from the subpixel 72 corresponds to a higher number of pulses during the same time period. To explain the operation of the subpixels 72 for a pulse density modulation emission scheme, image data 98 is transferred from, for example, the column driver 62 to the memory 78 for storage. Additionally or alternatively, image data 92/image data 56 or any suitable image data may be transferred to memory 78 for storage. Image data 98 transmitted to subpixel 72 is generated based at least on the desired gray scale level at which subpixel 72 will emit light.

Upon receiving image data 98, memory 78 stores image data 98 according to data clock 116, e.g., loading bits of image data 98 bit-by-bit on each rising edge of data clock 116. The memory 78 outputs image data 98 to be added to the binary data stored in the accumulator 150. Although the accumulator 150 is shown as an 8-bit accumulator, it should be understood that any suitable accumulator or register may be used to temporarily store data. Adder 152 may perform a binary addition of image data 98 and binary data of accumulator 150 in response to transmit clock 154 (e.g., a rising edge of transmit clock 154). The sum from adder 152 is transmitted for storage in accumulator 150 for use with the next image data 98 while the carry is used to open and/or close switch 104.

When switch 104 is closed, an electrical connection is made between common voltage 110 and first reference voltage 112. This causes current from the current source 102 to be transmitted through the LED 103, generally enabling light to be emitted from the sub-pixel 72. In this manner, the variable separation interval between pulses generated by emission clock 154 and adder 152 that carries the carry from the addition may help to vary the light emission from subpixel 72. Accordingly, the spacing of the emission pulses separating subpixels 72 may be varied to control the light emitted from subpixels 72, where brighter light may be emitted in response to smaller spacing of the separation pulses (e.g., higher density of pulses corresponding to brighter sensed light emitted from LEDs 103). Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to vary the total current value used to control the light emitted from the LED 103. For example, the second reference voltage 114 may increase the sensitivity of the LED 103 to current changes, such that a lower current value may be used to cause light to be emitted from the LED 103, or to enable the LED 103.

Graph 156 depicts transmit pulses and variable separation intervals between pulses resulting from a pulse density modulated transmission scheme. Under the use of a pulse density modulated emission scheme, subpixels 72 emit pulses separated by emission intervals of different lengths to vary the total light emitted from subpixels 72. As shown in graph 156, image data 98 may cause the sub-pixels to emit emission pulses 158 and not emit during the period of the non-emission interval 160. For example, the no-emission interval of emission pulse 162 separating the respective emission pulses is smaller than emission interval 160, and thus LED 103 of subpixel 72 may emit light within emission pulse 162 that is perceived as brighter than the light emitted from LED 103 due to emission pulse 158.

Thus, in summary, by using in-pixel memory technology, timing controller 54 may program image data 98 into display system 52 in a smaller portion of image data 98, rather than programming image data for all subpixels 72 simultaneously. To illustrate, a timing diagram of signals transmitted within the display system 52 in preparation for transmitting image data for storage in the one or more memories 78 shows a red image data transmission period 174R, a green image data transmission period 174G, a blue image data transmission period 174B, one or more copy periods 176, and one or more enable periods 178, as shown in fig. 11.

As shown, the column driver 62 may receive a signal to initiate copying of red data into one or more memories 78 of one or more red subpixels 72R. Upon receiving the signal, the column driver 62 may enter the copy period 176 in preparation for transmitting red data to the red subpixel 72R. During the copy period 176, the column driver 62 (e.g., via internal circuitry such as a row decoder) may prepare to enable the multiplexing circuits 96 associated with the pixels 70 of the display system 52. The column driver 62 or other suitable circuitry may operate the multiplexing circuit 96 to allow programming of the memory 78 of the red subpixel 72R, and may operate the multiplexing circuit 96 to disallow programming of the memories 78 of the blue and

green subpixels

72B, 72G, for example, by enabling and/or disabling the multiplexing control signal 101. In this way, red image data may be transferred and stored in the memory 78 corresponding to the red subpixel 72R. At the end of the copy period 176, the column driver 62 may transfer red image data to the red subpixel 72R during the red image data transfer period 174R. The transferred red image data is transferred to the corresponding memory 78 of the red subpixel 72R for programming with new red image data. In transmitting red image data to the red sub-pixel 72R, the column driver 62 and row decoder may repeat the described process for green image data and blue image data, thereby enabling the various color channels associated with each pixel 70 to be selectively programmed.

In general, the subpixels 72 are operated to emit light by receiving one or more control signals (e.g., from the column driver 62 and/or the row driver 60). The row driver 60 and the column driver 62 may control the operation of the subpixels 72 by controlling components of the subpixels 72, such as current drivers for the subpixels 72, using control signals. As described above, the column driver 62 may be responsible for at least transmitting image data to the subpixels 72, while the row driver 60 may be responsible for one or more control signals to control the emission transmitted to the subpixels 72. The sub-pixels 72 may include any suitable controllable elements responsive to these control signals and image data, such as transistors, an example of which is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). However, any other suitable type of controllable element may be used, including Thin Film Transistors (TFTs), p-type and/or n-type MOSFETs, and other transistor types.

In some embodiments, row driver 60 and/or column driver 62 may perform an initialization process, a charging process, a programming process, and an emission process on subpixels 72 in preparation for displaying an image on electronic display 18. By performing these processes, row driver 60 and/or column driver 62 of electronic display 18 may initialize subpixels 72 to be programmed, may charge capacitors for programming, may program subpixels 72 with signals corresponding to drive currents designed to cause subpixels 72 to emit light, and may enable image data to control light emission from subpixels 72. In some embodiments, a current driver may be responsible for generating the drive current in the sub-pixel 72.

To help illustrate the sub-pixel circuit with current driver in detail, an embodiment of the sub-pixel 72 including an initialization transistor (MINI)220, a driving transistor (MDR)222, a selection transistor (MSEL)224, a switching transistor (MS)226, a reset transistor (MRST)228, a light emitting portion such as an LED 230, a capacitor 232, and an auto-zero transistor (MAZ)234 is depicted in FIG. 12. It should be understood that the depicted sub-pixels 72 are illustrative and not limiting. For example, row driver 60 and column driver 62 are described herein as outputting image data and control signals related to displaying a next image on electronic display 18, however, it should be understood that any suitable components may be used to transmit control signals to perform the described processes to display a next image. Further, the circuitry shown in fig. 12 is merely an example of circuitry implemented in the sub-pixel 72 and/or the pixel 70 and should not be construed as limiting. For example, a voltage drive circuit (e.g., a voltage driver) may be used with the sub-pixel 72 instead of a current drive circuit (e.g., a current driver).

During the initialization process, the row driver 60 may enable the reset control (CSreset) signal 235 and disable the auto-zero control (csauto. CSreset signal 235 may be transmitted to MRST 228. In response to receiving CSreset signal 235, MRST 228 may activate and allow the draining of residual signals from the display of the first image from subpixels 72. These residual signals may be drained through a node coupled to a voltage reset (Vreset) signal 239 designed to facilitate draining of residual signals (e.g., 0 volts), such as system ground or a system reference voltage. In addition, the row driver 60 may enable a select control (CSselect) signal 241. CSselect signal 241 can be transmitted to MSEL 224. In response to receiving the CS select signal 241, the MSEL 224 can activate and allow a voltage data (Vdata) signal 242 to be transmitted to the node of the capacitor 232. To complete the initialization process, the row driver 60 may also enable an initialization control (CSinitialization) signal 243. The csinitilization signal 243 may be transmitted to the MINI 220. In response to receiving the CSinitialization signal 243, the MINI 220 may activate and allow initialization of the capacitor 232 to occur. In this state, the capacitor 232 may be charged with a voltage corresponding to the voltage difference between the Vdata signal 242 and the initialization voltage (initialization) signal 244. In this way, the voltage difference can be programmed by: different values are selected for the Vdata signal 242 and the visualization signal 244 based on the desired voltage level used by the initialization capacitor 232 while protecting the subpixel 72 from receiving additional signals that may interfere with initialization or that may cause unintentional light emission from the LED 230. The row driver 60 may continue the initialization process until the row driver 60 disables the CSinitialization signal 243, thereby disabling the MINI 220.

After the initialization process, the row driver 60 may perform a charging process while the MINI 220 and the MRST 228 are deactivated. During the charging process, MAZ 234 and MINI 220 remain deactivated, while MSEL 224 remains activated. When MSEL 224 is activated, capacitor 232 charges based on the Vdata signal 242 and a reference voltage (Vreference) signal 246. Charging capacitor 232 may enable drive current to be transmitted through MDR 222 even when MSEL 224 is disabled. In some implementations, the capacitor 232 stores the voltage value of the Vdata signal 242 so that the MDR 222 remains activated throughout the emission — thereby allowing the subpixel 72 to generate a constant drive current through the LED 230 for emission. In this way, subpixel 72 has a current driver — because the drive current enables light to be emitted from LED 230 when MS 226 is activated.

During the programming process, the row driver 60 may enable the CSauto. zero signal 237, causing the MAZ 234 to be activated. When MAZ 234 is activated, an electrical coupling is formed between the node of capacitor 232 and the source node of MS 226, causing the voltage value of the source node of MS 226 to increase to a voltage value equal to the gate voltage (Vg)245 of MDR 222. After a period of time sufficient to increase the voltage of the source node of MS 226 to a value equal to the voltage of Vg 245, row driver 60 may disable csauto. In this state, subpixel 72 is programmed with an electrical signal ready to be transmitted to LED 230 upon activation of MS 226. That is, in this state, subpixel 72 is ready to pass the drive current generated by the programming signal in response to the csimage.data signal 247 enabling MS 226.

After the programming process is complete, row driver 60 may operate subpixels 72 to perform the emission process. During the emission process, subpixels 72 emit light in accordance with image data control (csimage. data) signals 247, for example, transmitted from column driver 62 to MS 226. Subpixel 72 can receive csimage.data signal 247 from any suitable component of electronic device 10 that can create and/or generate image data for display via subpixel 72. MS 226 activates in response to an enabled csimage data signal 247, e.g., has a voltage logic high sufficient to switch the value of MS 226 (e.g., large enough to overcome the programming voltage at the source node of MS 226 and the threshold voltage of MS 226). Upon activation of MS 226, the voltage stored at the source node of MS 226 is transmitted as a drive current through LED 230. If the drive current exceeds a threshold voltage of the LED 230, where the threshold voltage of the LED represents a voltage value at or above which light is emitted from the LED, the LED 230 may emit light based at least in part on the value of the drive current.

It is to be appreciated that the csimage.data signal 247 can be binary and/or digital data representing image data for operating the subpixels 72 to emit at a particular gray scale for transferring an image (e.g., a second image). As previously discussed, the subpixels 72 may operate according to various transmission schemes, and thus, the csimage data signal 247 transmitted to the MS 226 may vary between embodiments. In an embodiment, however, the csimage data signal 247 is derived from an image to be displayed on a display. Further, the enabling and/or disabling of the csimage.data signal 247 at least partially causes the LED 230 to emit light or not to emit light, and thus enables the csimage.data signal 247 to modulate the light emission from the subpixel 72.

Upon completion of the transmit process, row driver 60 may disable CSselect signal 241 and enable CSreset signal 235, thereby causing deactivation of MSEL 224 and activation of MRST 228. With MSEL 224 disabled, subpixel 72 may no longer operate to emit light because capacitor 232 no longer receives charge and because the residual signal from the emission process is allowed to drain by enabling MRST 228.

The described sub-pixel 72 is considered a current driven pixel because the sub-pixel 72 has a primary current that drives the LED 230 to emit light or not to emit light. A primary or drive current is passed through the MS 226 in response to various control signals that control the timing of light emission from the subpixels 72. The described sub-pixel 72 circuit may have particular advantages, including how a digital output can control the emission from the LED 230 without further conversion to an analog output. Furthermore, the inclusion of the capacitor 232 may enable compensation for changes in the threshold voltage associated with the sub-pixel 72 resulting from substrate bias effects, i.e., side effects associated with applying a voltage to the gates of some of the transistors.

Further improvements to subpixel 72 may be made if a voltage driver is included in addition to the current driven configuration of subpixel 72 in fig. 12. At the beginning of the emission process, the voltage driver is enabled for a period of time to provide a boost to the anode of the LED 230 to facilitate the initial emission of light, where a lower drive current can be used to achieve light emission rather than boosting the anode of the LED 230. A smaller drive current value may be used to drive the LED 230 to emit light because the LED 230 may operate in a forward biased region or an operating region of the LED 230 that is more sensitive to small changes in current (due to the boost provided by the voltage driver).

For illustration, a second embodiment of a sub-pixel 72 having a hybrid driver including a current driver 270 and a voltage driver 272 and having a memory 78 is shown in fig. 13. It should be understood that the depicted sub-pixels 72 are illustrative and not limiting. For example, current driver 270 and voltage driver 272 are shown as separate elements in subpixel 72, but one or both of the drivers may be included in driver 80 described previously.

The row driver 60 and/or the column driver 62 may operate the subpixels 72 to emit light by enabling and/or disabling the control signals. The row driver 60 and/or the column driver 62 may use the control signals to perform various processes to cause the subpixels 72 to emit light, including an initialization process, a charging process, a programming process, and an emission process for the subpixels 72 to enable display of image data corresponding to an image to be displayed.

To help illustrate the interaction of control signals emitted by the row driver 60 and/or column driver 62 of FIG. 13 with the subpixels 72, a timing diagram 279 corresponding to the signals for display, including the Vdata signal 242, the CSinitiation signal 243, the CSselect signal 241, the CSauto. zero signal 237, the CSimage. data signal 247, the CSselect signal 280, and the CSreset signal 235, is shown in FIG. 14. It should be understood that the timing diagram is intended to be illustrative and not limiting, for example, the control signals shown in FIG. 14 may represent more or less control signals than are implemented in the subpixels 72.

The initialization process described above corresponds to time period 282. During time period 282, the row driver 60 may provide a high voltage for the Vdata signal 242, may enable the CSinitialization signal 243 for the duration of the initialization process, may enable the Csselect signal 241 for time period 284, may disable the csauto. zero signal 237, may disable the CSreset signal 235, and may disable the Csselect signal 280.

Referring again to fig. 13, the control signals output by the row driver 60 to perform the initialization process cause activation and/or deactivation of the various switching elements, as previously described. The control signals of fig. 14 that effect access to subpixel 72 cause MINI 220 to activate in response to the enabled CSinitialization signal 243, MSEL 224 to activate in response to the enabled CSselect signal 241, MAZ 234 to deactivate in response to the disabled csauto. zero signal 237, MRST 228 to deactivate in response to the disabled CSreset signal 235, and voltage driven switching element (MVD)285 to deactivate in response to the disabled CS select signal 280. This arrangement enables the difference in voltage values between the Vdata signal 242 and the visualization signal 244 to charge the capacitor 232. The row driver 60 may continue the initialization process until the row driver 60 disables the CSinitialization signal 243 to disable the MINI 220 and thereby end initialization.

Referring again to FIG. 14, timing diagram 279 shows that after the initialization process, row driver 60 disables CSinitialization signal 243 to perform a charging process for subpixel 72. During the charging process, the Vdata signal 242, csauto.zero signal 237, csimage.data signal 247, CSselect signal 280, and CSreset signal 235 remain in their previous states. Timing diagram 279 shows the Vdata signal 242 at a high voltage level (DVDD) for the subpixel 72 circuit, e.g., corresponding to a logic high value in the binary data of subpixel 72 and/or electronic device 10. In some embodiments, DVDD equals the voltage value of Vreference signal 246.

Referring again to fig. 13, the control signals output by the row driver 60 activate and/or deactivate various switching elements to perform the charging process. Upon disabling 243 of the CSinitialization signal and disabling of the MINI 220, the capacitor 232 charges based on the Vdata signal 242 and the Vreference signal 246. Charging capacitor 232 may cause current driver 270 to remain in use during the emission process, even when MSEL 224 is disabled. In some embodiments, the capacitor 232 holds the voltage value of the Vdata signal 242 after the charging process so that the MDR 222 can remain activated throughout the discharging process — thereby allowing the current driver 270 to generate a constant drive current through the LED 230 for emission.

After a set period of time suitable for charging the capacitor 232, the row driver 60 may perform a programming process. Referring briefly to fig. 14, to perform the programming process, the row driver 60 enables the csauto. zero signal 237 for a time period 286 and maintains the CSinitialization signal 243, the Vdata signal 242, the csimage. data signal 247, the CSselect signal 280, and the CSreset signal 235 in their previous states. As shown, the row driver 60 also transmits a ground voltage (GND) as the Vdata signal 242 for a duration 288 during the programming process. GND may be equal to zero volts or any suitable ground reference voltage associated with the electronic display 18, electronic device 10, and/or subpixel 72.

Returning to fig. 13, the MAZ 234 activates in response to the enabled csauto. When MAZ 234 is activated, an electrical coupling is formed between the node of capacitor 232 and the source node of MS 226, causing the voltage value of the source node of MS 226 to increase to a voltage value equal to Vg 245. After a time period 286, the row driver 60 disables the CSauto. zero signal 237 and the MAZ 234 is disabled. In this state, subpixel 72 is programmed with an electrical signal ready to be transmitted to LED 230 when MS 226 is activated. That is, in this state, subpixel 72 is ready to pass the drive current generated by the programming signal in response to the csimage.data signal 247 that enables MS 226. Once the source node of MS 226 is programmed with the Vg 245 voltage, row driver 60 transmits the Vdata signal 242 equal to GND and disables CSselect signal 241 at the end of time period 284, thereby disabling MSEL 224. At the completion of the programming process, the row driver 60 may enable and/or disable the control signals to perform the emission process.

Referring to fig. 14, during the transmit process, the row driver 60 may return the Vdata signal 242 to the DVDD, may continue to disable the CSinitialization signal 243, may continue to disable the CSselect signal 241, may enable the csimage data signal 247 for a time period 290, may enable the CS select signal 280 for a time period 292, and may continue to disable the CSreset signal 235. As shown, the CSselect signal 280 is enabled at the same time as the csimage.data signal 247, but is disabled earlier than the csimage.data signal 247. This is because the CSselect signal 280 is used to activate the switching element to provide a boost to the anode of the LED 230 of the subpixel 72.

Returning to fig. 13, the voltage driven switching element (MVD)285 of the subpixel 72 is activated in response to the enablement of the CS select signal 280, thereby activating the voltage driver 272. In response to MVD 285 activation, a reference voltage (Vreference) signal 300 is transmitted to the anode of LED 230 when csimage.data signal 247 enables switch transistor (MS)302 and MS 226 for the first transmitted csimage.data signal 247. This causes Vreference signal 300 to be transmitted at the anode of LED 230, enabling or "boosting" a smaller programmed value of the source from MS 226 to cause emission of light from LED 230. Boosting may continue for a time period 292, where at the end of time period 292, row driver 60 disables CS select signal 280, thereby disabling MVD 285 and MS 302.

In general, the launch process may continue for a period 290 with boosting for a shorter period of time (e.g., period 292). During the emission process, subpixel 72 is programmed to deliver a drive current through LED 230 in response to activation of MS 226. As previously described, the memory 78 of the sub-pixel 72 stores digital data and outputs the digital data. With the described hybrid driver, stored digital data is transferred from the memory 78, since the digital data becomes a control signal to control light emission from the sub-pixels 72 with less overhead and without increasing power consumption. At the end of boosting, in some embodiments, the subpixels 72 may be reset via enabling the CSreset signal 235 for a duration such as time period 294. Thus, the light emitted from the LED 230 may follow various emission schemes (as previously explained with respect to fig. 8-10) in order to convey the gray scale associated with the image, since the binary data output from the memory 78 is used to modulate the light emitted via the LED 230.

To help illustrate the effect of "boosting" on the anode voltage of the subpixel 72, a graph 348 showing an exemplary csimage data signal 350, a voltage signal 352 corresponding to the voltage at the anode of the LED 230, and a current signal 354 corresponding to the current through the LED 230 for a subpixel 72 that does not implement a hybrid driver are shown in fig. 15. It should be understood that the timing diagrams are illustrative and not limiting.

In this simulation, the binary pulse width modulation transmission scheme was tested by providing wider and wider binary pulses as the csimage. The simulation results shown in graph 348 generally have two portions. The first portion 356 may correspond to a slower emission response time and the second portion 358 may correspond to a normal emission response time, where emission response time generally refers to the relative responsiveness of the LED 230 to the voltage applied thereto. It is also noted that an LED (e.g., LED 230) operates to turn on based on a voltage difference between the anode and cathode of the LED. If the voltage difference between the anode and the cathode is greater than the threshold voltage, the LED emits light according to the value of the current transmitted through the LED. In graph 348, the current signal 354 may generally correspond to the LED 230 emission, wherein the closer the value of the current signal 354 matches the state of the csimage data signal 350, the better the emission response time of the LED 230. In graph 348, the effect of the slow charging effect on the anode voltage of the LED 230 is clear. During the first portion 356, the current signal 354 appears to be less responsive to changes in the state of the csimage data signal 350 than the second portion 358, as indicated by the overall matching of the amplitudes of the current signal 354 and the csimage data signal 350 during the second portion 358 and during the first portion 356 in the absence thereof. Boosting the anode at the beginning of the emission period may reduce or eliminate the slow charging effect of the anode voltage.

Proceeding to fig. 16, for comparison, a graph 370 showing an exemplary csimage.data signal 350, a voltage signal 374 corresponding to the voltage at the anode of the LED 230, and a current signal 376 corresponding to the current through the LED 230 for the subpixel 72 with a hybrid driver are shown in fig. 16. It should be understood that the timing diagrams are illustrative and not limiting. For example, while the csimage.data signal 350 is shown to follow a binary pulse width modulation transmission scheme, any suitable transmission scheme may yield the same improvement in responsiveness, as described below.

In this simulation, the binary pulse width modulation transmission scheme was tested by providing increasingly wider binary pulses as the csimage.data signal 350, similar to graph 348. However, unlike the graph 348, the graph 370 shows the current signal 376 in response to changes in the csimage.data signal 350. This improved responsiveness is due, at least in part, to the addition of the voltage driver 272 to the sub-pixel 72. Because the voltage driver 272 of the hybrid driver "boosts" the anode of the LED 230, a smaller change in the voltage at the anode of the LED 230 may result in the same and/or similar responsiveness of the second portion 358 of the graph 348. Accordingly, graph 370 illustrates the benefits and improvements to the display technology provided by implementing hybrid drive in at least sub-pixel 72.

As described above, a display implementing in-pixel memory technology can implement various pixel circuit embodiments and various memory circuit embodiments to achieve the benefits previously described in this disclosure. An exemplary embodiment is a memory circuit supporting a binary pulse width emission scheme in which digital data stored in the memory circuit is output to a driver circuit to control light emission from a pixel. As a reminder, binary pulse width transmission schemes work in series with timing signals (e.g., bit plane clocks) to assign contribution weights to different portions of the digital data transmitted from the memory circuit. In some implementations, the timing signal is used to clock a register to output stored digital data from the memory circuit. However, in some embodiments, the system clock and/or the row driver 60 may control the light emission duration by the length of time the emission enable signal is enabled.

To help illustrate the memory circuitry that facilitates controlling emission via the emission enable signal, the subpixel 72 including the memory circuit 400A, the analog driver circuit 402, and the light emitting circuit 404 is shown in fig. 17. It should be understood that the sub-pixels 72 are illustrative and not limiting. For example, although the memory circuit 400A is shown as storing twelve bits of digital data, any suitable memory circuit may be used, such as a circuit that stores more or less than twelve bits of digital data.

The memory circuit 400A may include a write enable transistor (MWR)406, one or more inverter pairs 408, and a transfer select transistor (MSEL) 410. The memory circuit 400A receives digital DATA (DATA)412 from, for example, the column driver 62 and stores the digital DATA. Before the memory 400A stores the DATA412, the row driver 60 may enable a write, such as an enable control signal (write _ en)414 to activate the MWR 406, allowing image DATA to be written to the memory (e.g., inverter pair 408) so the memory can remember the image DATA. Upon receiving DATA412, the inverter pair 408 stores the DATA412 value. It should be emphasized that the use of the memory circuit 400A allows for parallel transmission of the DATA412 such that, in addition to bitwise transmission, all bits of the DATA412 are stored in a corresponding inverter pair 408 at the same time or in the same write cycle (e.g., when the write _ en signal 414 is enabled), with each bit of the DATA412 storing one bit at a time. The MSEL 410 activates in response to an enabled select control signal (Sel)415 transmitted by, for example, the row driver 60, which operates the MSEL 410 targeted for activation as a memory bit transmitted to the analog driver circuit 402. In this manner, the MSEL 410A may be activated while the MSEL 410B is deactivated. Thus, before the transmission process begins, the memory circuit 400A is loaded with one or more DATA412 bits and the DATA412 is read bit-by-bit by activating the corresponding MSEL 410.

At the beginning of a transmit process (e.g., as described in fig. 14), row driver 60 may enable Precharge control signal (Precharge)416 as a way to initially enable light emission based at least in part on the activation of transmit transistor (MEM) 419. MEM 419 may be activated in response to the row driver 60 enabling the emission control signal (Emit en) 420. In some embodiments, row driver 60 may enable Precharge signal 416 simultaneously with Emit en signal 420 to allow Vreference signal 246 to be transmitted to MS 226 to Precharge or boost the anode of LED 230 prior to activating MSEL 410. After the precharge is complete and during the transmit process, the Emit _ en signal 420 may continue to be enabled by the row driver 60. While row driver 60 disables the Precharge signal 416 after precharging so that the stored DATA412 at least partially controls the activation of MEM 419. In this manner, stored DATA412 transmitted from inverter pair 408 may cause MEM 419 to activate in response to a logic value (e.g., "1" or "0") of the stored value. It should be noted that in some embodiments, a logic high value is equal to Vreference signal 246 and a logic low value is equal to Vreference signal 248.

As the stored DATA412 is transmitted from the memory circuit 400A, the light emitting circuit 404 receives the stored DATA412 at the gate of the MS 226. The MS 226 activates in response to the stored DATA412 value, thereby enabling the current generated by the analog driver circuit 402 to be transmitted to the LED 230 to cause light emission. Transmission may continue as long as the stored DATA412 is applied as the csimage DATA signal 247. In this manner, light is emitted from the sub-pixel 72 after the initialization process, charging process, programming process, and emission process generally described with respect to fig. 12-14.

An additional embodiment of a subpixel 72 having a memory circuit 400B and an analog driver circuit 442 and including a light emitting circuit 404 is shown in fig. 18. It should be understood that the sub-pixels 72 are illustrative and not limiting. For example, although memory circuit 400B is shown storing sixteen-bit digital data, any suitable memory may be used, such as circuits that store more or less than sixteen-bit digital data. Further, although the sub-pixel 72 is depicted as having the LED 230 included in the light emitting circuit 404, any suitable light emitting circuit 404 may be combined with the in-pixel memory techniques described.

Memory circuit 400B is depicted as including one or more write enable transistors (MWR)406, one or more inverter pairs 408, and one or more select transistors (MSEL) 410. For example, data412 from the column driver 62 is received into the memory circuit 400B. To transfer the DATA412 to the memory circuit 400B, the row driver 60 may enable the write _ en signal 406 and the inverse of the write _ en signal (invert write _ en)444 to enable bitwise memory storage of the DATA 412. For example, row driver 60 may enable storage of the last bit of DATA412 in inverter pair 408B by activating MWR 406D and/or MWR 406C. Thus, the row driver 60 and the column driver 62 may operate to enable bit-wise transfer and storage of the DATA412 into the memory circuit 400B.

While storing the DATA412 in the inverter pair 408, the memory circuit 400B stores the DATA412 value until the row driver 60 selects the corresponding bit for transmission. Prior to selecting the respective bit for transmission, row driver 60 precharges sense amplifiers 440 via the enabling of Precharge (Precharge) signal 416. By precharging sense amplifier 440 and subsequent analog driver circuit 442, the responsiveness of subpixel 72 to transmitted electrical signals may be improved as compared to a subpixel 72 that is not precharged. As previously described, precharging the subpixels 72 can make switching states easier and less demanding on the circuit (e.g., by increasing circuit responsiveness).

Upon completion of the precharge, the row driver 60 selects the bit for transmission to the analog driver circuit 442 to cause transmission in accordance with the stored DATA 412. To transfer a bit to the analog driver circuit 442, the row driver may cause the Sel signal 415 to activate the MSEL 410 corresponding to the inverter pair 408. For example, the row driver 60 may enable the Sel signal 415A to activate MSEL 410A and MSEL 410B to cause transmission of DATA412 stored in the inverter pair 408A for transmission to the analog driver circuit 442.

In some implementations, the DATA412 is transmitted through the sense amplifier 440 before being transmitted to the analog driver circuit 442. Sense amplifier 440 is used to sense the logic state of DATA412 and may amplify the sensed logic state to an interpretable logic state for adjacent circuitry (e.g., by increasing signal amplitude). The interpretable logic state may be based at least in part on a threshold voltage of the MS 226 of the analog driver circuit 442. For example, the bit transmitted to node 446 is output at node 448 as having a larger voltage value, which is caused by the transmission through sense amplifier 440 and is based at least in part on the voltage difference between Vreference signal 248 and Vreference signal 246, thereby representing any suitable voltage value common to display systems (e.g., display system 52).

After amplifying the DATA412, the amplified DATA412 is transmitted as a csimage DATA signal 247 to the analog driver circuit 442 to activate or deactivate the MS 226. For example, in some embodiments, MS 226 is deactivated in response to a transmitted logic high DATA412 (e.g., transmitted as a csimage DATA signal 247) and activated in response to a transmitted logic low DATA 412. In this way, the voltage value of the digital data transmitted as the csimage.data signal 247 corresponds to the bias voltage of the MS 226 or the voltage value at which the MS 226 is operated to change state. Upon activation of MS 226, a drive current generated by analog drive circuit 442 based at least in part on a voltage difference between Vreference signal 450 and Vreference signal 451 is transmitted through LED 230, thereby enabling subpixel 72 to emit light. Thus, in the manner described, the DATA412 stored in the memory circuit 400B may drive light emission from the pixel circuit (e.g., subpixel, pixel).

To summarize the operation of the subpixel 72 embodiment of fig. 17 and 18, an example of a process 461 for controlling the operation of the subpixel 72 coupled to the memory circuit 400 is described in fig. 19. In general, process 461 includes: loading the memory with the current bit (block 462), determining whether the current bit is the last bit to be loaded into the memory (block 464), in response to the current bit not being the last bit, loading the memory with the next current bit (block 462), and in response to the current bit being the last bit, enabling the select signal to allow the bit to be read from the memory (block 466), waiting for the bit to be emitted in the pixel circuit (block 468), and determining whether the bit is the last bit to be read from the memory (block 471). In response to the bit being the last bit, the display cycle is completed (block 472), and in response to the bit not being the last bit, the next select signal is enabled to allow the next bit to be read from memory (block 466). In some embodiments, process 461 may be implemented, at least in part, by: the instructions stored in the tangible, non-transitory computer-readable medium, such as the one or more storage devices 14, are executed using processing circuitry, such as the processing core complex 12. Additionally or alternatively, the process 461 may be implemented based at least in part on circuit connections formed in display control circuitry, such as the row driver 60, the column driver 62, and/or the timing controller 54.

Thus, in some embodiments, the row driver 60 may load the memory circuit 400 with the current bit (block 462). As described above, the row driver 60 selectively enables the respective switching element (such as MWR 406B or MWR 406D) to enable bitwise loading of the current bit of DATA412 into the memory circuit 400. When MWR 406 is enabled, the bit corresponding to the current bit of DATA412 is transferred for storage, such as in inverter pair 408, with the value of the current bit being successively inverted until the bit is selected for transfer.

After loading the current bit into memory, the row driver 60 may determine whether the current bit is the last bit (block 464). The last bit represents the final bit of the DATA412 (e.g., the last bit to be stored in the memory circuit 400). Thus, checking whether the current bit is the last bit checks whether all DATA412 has been transferred from the column driver 62 for storage. Various techniques may be implemented to determine whether the current bit is the last bit, including, for example, maintaining a separate count to track the position of the current bit relative to the position of the last bit.

In response to the current bit not being the last bit, the row driver 60 may load the memory circuit 400 with the next current bit (block 462). As described above, the row driver 60 enables the next corresponding switching element to bitwise transfer the next bit of DATA412 into the memory circuit 400 as the next current bit. Thus, process 461 repeats until the last bit of DATA412 is stored in the memory circuit 400.

However, in response to the current bit being the last bit, the row driver 60 may enable the select signal to transfer the bit from memory (block 466). When the current bit is the last bit, the row driver 60 determines that the target DATA to be stored in the memory circuit 400 has completed loading into the memory — therefore, at this time, the row driver 60 transmits the stored DATA412 to the analog driver circuit 442 bit by bit or bit by bit to cause light emission from the sub-pixels 72 at a gray level or brightness corresponding to the DATA 412. In some embodiments, the row driver 60 transfers the stored bits in order from the least significant bit to the most significant bit, although any suitable order of the memory circuit 400 and the display system 52 may be used. To cause a transfer, the row driver 60 enables the Sel signal 415 corresponding to the target bit from the memory circuit 400 to be read. When the Sel signal 415 is enabled, the target bit is transmitted to the sense amplifier 440 and/or the analog driver circuit 442 to cause light emission.

Next, the row driver 60 may wait a programmed time period of the transfer bit from the memory to cause light to be emitted from the sub-pixel 72 (block 468). While the row driver 60 is waiting, the bits stored in the inverter pair 408 are transferred to the MS 226. The analog driver circuit 442 allows drive current to pass through the LED 230 when the MS 226 is activated, resulting in light emission from the subpixel 72. As previously described with reference to fig. 8, the bit plane clock 106 may be used to modulate the width of the light emission to correspond to the importance of the bits from the memory to the overall perceived gray level. The row driver 60 may use the bit plane clock 106 to modulate light emission from the subpixels 72, such as by modulating the overall emission of the subpixels 72 (e.g., via enabling the Emit en signal 420) and/or by modulating a time period during which bits are selected for transmission from the memory circuit 400 (e.g., via enabling a time period corresponding to the significance of the bits of the Sel signal 415 to activate the MSEL 410). It should be noted that in some embodiments, the row driver 60 does not wait and continues to determine whether the bit read from the memory circuit 400 is the last bit of the stored DATA 412.

After reading the bit, the row driver 60 may determine whether the bit is the last bit of the stored DATA412 (block 471). The row driver 60 determines whether the last bit has been read and/or transmitted to the analog driver circuit 442. The row driver 60 may manage this determination in various ways, such as maintaining a counter that is incremented in series with the enabling of the Sel signal 415 to indicate when the row driver 60 has read the expected number of bits from the memory circuit 400.

If the bit is the last bit, row driver 60 may complete the display cycle (block 427). The display period may include the entire process 461 such that when the block 427 is reached, the row driver 60 has emitted light corresponding to the gray level of the DATA 412. After the display period is complete, the row driver 60 may be ready to accept new DATA412 corresponding to the same or different gray levels for emission.

However, in response to the bit not being the last bit, the row driver 60 may enable the next select signal to allow the next current bit to be read from memory (block 466). The row driver 60 may manage the enabling of the next select signal in various ways, such as keeping a separate count to track the position of the current transmitted bit relative to the position of the final transmitted bit. In any case, the row driver 60 determines the Sel signal 415 to be enabled (e.g., the Sel signal 415 corresponding to the bit to be transmitted next from the memory circuit 400). When the row driver 60 determines which Sel signal 415 is to be enabled, the row driver 60 enables that Sel signal 415, causing activation of the MSEL 410 corresponding to the target bit for transmission. The row driver 60 may repeat transmitting the stored bits of the DATA412 until the last bit is reached. Upon reaching the last bit, the row driver 60 completes the emission cycle and may prepare for the next emission cycle (block 427).

For fig. 18 and 19, the subpixel 72 implementation is depicted with an analog driver circuit 442 with a global anode. Additional embodiments of subpixel 72 may have analog driver circuit 442 with a global cathode.

A sub-pixel with a global cathode is shown in fig. 20, which includes a memory circuit 400C, an analog driver circuit 442, and has a light emitting circuit 404. It should be understood that the sub-pixels 72 are illustrative and not restrictive. For example, although memory circuit 400C is shown storing sixteen-bit digital data through bitwise transmission of data, any suitable memory circuit may be used, such as circuits that store more or less than sixteen-bit digital data and/or circuits that allow parallel transmission of data.

In the depicted embodiment, the cathode of LED 230 is coupled to a reference voltage (Vreference) signal 470 and the anode of LED 230 is coupled to a reference voltage (Vreference) signal 473 through MS 226A, MS 226B, MS 276 and MS 278. As previously described, after data412 is stored in memory circuit 400C, and in some embodiments, after the circuit is precharged via Precharge signal 416, row driver 60 may enable Emit _ en signal 420 to cause light emission. Upon activation of

MEMs

480 and 482, the stored DATA412 bits are transmitted through the sense amplifier 440 and the amplified bits are transmitted to MEM 480, while the inverted version of the stored DATA412 bits is transmitted to MEM 482 without amplification. The inverted and amplified bits are used as control signals to activate

MSs

226A and 226B, effectively acting as data signal 247 from the csimage. Upon activation of MS 226A and MS 226B, analog driver circuit 442 generates a drive current to transmit through LED 230 to cause light emission based at least in part on a voltage difference between Vreference signal 473 and Vreference signal 470.

In a similar manner to the global anode implementation, the global cathode subpixel 72 may create different gray levels by following a binary pulse width modulation scheme. The binary pulse width modulation scheme may use a bit plane clock to partially control the control signals output from the row driver 60. In this manner, the Emit _ en signal 420 may be enabled for shorter periods of time for bits of lesser importance on the perceptual gray level (e.g., the least significant bit of DATA 412) and may be enabled for longer periods of time for bits of greater importance on the perceptual gray level (e.g., the most significant bit of DATA 412). In some embodiments, Sel signal 415 may be modulated to cause light to be emitted from sub-pixels 72 according to different gray levels.

As illustrated in fig. 9, the use of in-pixel memory technology and comparators may enable the row driver to create a single pulse width modulation emission scheme. Thus, an embodiment of subpixel 72 including comparator 490, memory circuit 491 and memory circuit 492 is shown in FIG. 21. It should be understood that the sub-pixels 72 are illustrative and not restrictive. For example, although memory circuit 492 is shown as an LED driver circuit and a light emitting circuit coupled to subpixel 72, memory circuit 492 may be coupled to any suitable light emitting circuit and/or driver circuit.

In the depicted subpixel 72, following a similar process as previously described, an n-bit sized DATA412 is received into the memory circuit 491, i.e., the row driver 60 operates to enable the write _ en signal 494 to cause the DATA412 to be transmitted into the inverter pair 496. In some implementations, the row driver 60 operates in series with the column driver 62 to cause all bits associated with DATA412 to be transmitted in parallel to the inverter pair 496 by simultaneously enabling the write _ en signal 494. Additionally or alternatively, the row driver 60 may cause a bitwise transmission of the bits associated with the DATA412 by selectively enabling the write _ en signal 494, e.g., by selectively enabling the write _ en signal 494A to load the bits into the inverter pair 496A to cause the first bit of the DATA412 to be transmitted.

Once the DATA412 is stored in the inverter pair 496, the comparator 490 uses the stored DATA412 bits and the bits transmitted from the counting circuit (e.g., counter 130) to perform a comparison between the two sets of bits. As a reminder, in a single pulse width modulation transmission scheme, a counting circuit (e.g., counter 130) increments on the rising edge of a timing signal (e.g., gray scale clock 134) up to a maximum gray scale level, where it is transmitted from subpixel 72 until the counting circuit counts a number equal to and/or exceeding the number represented by stored data 412. In this manner, comparator 490 compresses all bits of DATA412 into a single bit that indicates whether DATA412 is the same as the count transmitted from the counting circuit. Thus, comparator 490 performs bitwise XNOR compression on a single bit of an implementation having memory circuit 491 and memory circuit 492, with the output from comparator 490 being a logic low (e.g., "0") value unless each bit matches. If each bit matches, comparator 490 outputs a logic high value. The output from comparator 490 is stored in memory circuit 492 with the value remaining in inverter pair 498 until row driver 60 enables emit en 420 to have the stored comparator 490 output transmitted to the LED driver and lighting circuit to drive light emission as previously described. It should be noted that CNT _ b [ n:0] corresponds to the inversion of CNT [ n:0] and is used to compare the inverted output from inverter pair 496 with the inverted bits of CNT [ n:0 ].

It should be appreciated that in some embodiments, the count circuit may decrement, the comparator 490 may output a logic low value when each bit matches, or any combination thereof. In other words, various efficient implementations may apply the described in-pixel memory technology. In addition, an optional transistor 500 may be included in the subpixel 72 to provide power saving benefits by precharging a common output (e.g., MTCH) node of the comparator 490, thereby making the circuit better responsive to changes in the output from the comparator 490.

To illustrate the operation of the subpixel 72 shown in FIG. 21 in detail, a process 520 for operating the subpixel 72 having a comparator 490 and a memory circuit 491 is described in FIG. 22. In general, process 520 includes: the memory circuit is initialized (block 522), the common output from the comparator is precharged (block 524), the count of the count circuit is incremented (block 526), the transmission is caused based on an automatic comparator determination stored in the memory circuit (block 528), and a determination is made whether the count circuit has reached a maximum count (block 530). In response to the count circuit reaching the maximum count, the next image is prepared (block 532), and in response to the count circuit not reaching the maximum count, the common output from the comparators is precharged (block 524). In some embodiments, process 520 may be performed, at least in part, by: the instructions stored in the tangible, non-transitory computer-readable medium, such as the one or more storage devices 14, are executed using processing circuitry, such as the processing core complex 12. Additionally or alternatively, the process 461 may be implemented based at least in part on circuit connections formed in display control circuitry, such as the row driver 60, the column driver 62, and/or the timing controller 54.

Thus, in some embodiments, row driver 60 may initialize memory circuit 492 (block 522). To initialize the memory circuit 492, the row driver 60 may enable the control signals to force the nodes of the memory circuit 492 to a low voltage value. With reference to fig. 21, for example, to initialize the memory circuit 492, the row driver may enable the S reset (S _ rst) signal to reset a voltage value of a node (e.g., the S node) of the memory circuit 492. Initializing the node of memory circuit 492 enables the light emitting circuit to emit until the comparator outputs a logic high to stop light emission from subpixel 72 (e.g., in response to the counter circuit reaching a gray level stored in memory). In other words, for one or more sub-pixels 72 implementing the comparator 490, the sub-pixels 72 may start light emission at the same time but stop light emission at different times — with the respective durations of light emission corresponding to the target gray levels for the respective sub-pixels 72.

After initializing memory circuit 492, row driver 60 may precharge comparator 490 (block 524). To Precharge the comparator 490, the row driver 60 may enable the Precharge signal to cause the voltage to boost the circuit, thus enabling the subpixel 72 to respond better to changes in the output from the comparator 490. To Precharge the comparator 490, the row driver 60 may enable a "Precharge" signal that works with the inverted emit en signal 420 to pass a voltage (e.g., DVDD) to the comparator 490 (e.g., MTCH node of the comparator 490) to boost the circuit. Although specific circuitry is depicted that operates to Precharge the comparator 490 in response to the Precharge signal, it should be understood that various effective circuit arrangements may be used to facilitate the precharging of the comparator 490.

After precharging the comparator 490, the row driver 60 may increment the count of the counting circuit (block 526). The row driver 60 may increment the counter circuit, e.g., in response to an increment of the timing signal timing. After incrementing the counter circuit, subpixel 72 automatically determines whether the count of the counter circuit equals or exceeds the value represented by stored DATA 412. This occurs because the respective bits of the count and the respective bits of the DATA412 are each transmitted to the comparator 490, where the comparator 490 outputs a logic high value if all the bits match or a logic low value if even one of the bits does not match. The output of comparator 490 is transmitted for storage or saving in inverter pair 498 of storage circuit 492 where the value is stored until row driver 60 enables transmission via the enabling of emit _ en signal 420.

After incrementing the count of the counting circuit, the row driver 60 causes transmission based on the determined output from the comparator 490 stored in the memory circuit 492 (block 528). The row driver 60 causes transmission by enabling the emit en signal 420. As previously described, when emit en 420 is enabled, this value is transmitted from inverter pair 498 to the LED driver and light emitting circuitry of the subpixel to cause light emission, for example, from LED 230 or any suitable light emitting circuitry. The value transmitted from memory circuit 492 may activate or deactivate the switching circuitry of the LED driver and the lighting circuitry responsible for causing light emission.

When the row driver 60 causes a transmission based on the output from the comparator 490, the row driver may determine whether the count of the counting circuit is a maximum count (block 530). The counting circuit may count from a minimum value to a maximum value, for example, from 0 to 255. Thus, when the counting circuit reaches a maximum value or maximum count, the row driver 60 may perform certain process steps to restart the counting.

In response to the maximum count not being reached, the row driver 60 restarts the process 520 by precharging the common output from the comparator 490 (block 524). From there, therefore, the process 520 continues as described to cause the row driver 60 to transmit another output from the comparator 490 that indicates whether the stored DATA412 equals or exceeds the count represented by the count circuit.

However, in response to reaching the maximum count, the row driver 60 prepares the next image (block 532). To this end, the row driver 60 is ready to receive a new DATA412 corresponding to the target gray level for the subpixel 72 transmitting the next image. Different implementations of the sub-pixel 72 may be prepared in various ways. For example, the subpixel 72 from fig. 21 may enable one or more write _ en signals 494 to facilitate loading of the new DATA412 into the memory circuit 491. In some embodiments, preparing the next image includes restarting counting by the counting circuit, such that at block 526, the counting circuit is incremented to zero and counting can be restarted. It should be understood that in embodiments where the counting circuit is a series of flip-flops coupled together to form a counter (such as counter 130), restarting the counting circuit to zero is not necessary because the counting circuit automatically restarts it to zero based on the digital logic characteristics of the circuit.

Several emission schemes, such as binary pulse width modulation and single pulse width modulation, have been described with respect to general theory of operation, specific exemplary memory circuits, and specific exemplary pixel circuits to enable the use of emission schemes to generate light of perceived gray levels emitted from the subpixels. An additional transmission scheme-a binary pulse width modulation reordering transmission scheme-can be performed by using in-pixel memory techniques.

To aid in illustration, a memory circuit 560 having one or more MWRs 406, one or more MSELs 410, an inverter pair 408, an inverter pair 498, and a switch/reset (SR) latch 562 is shown in fig. 23. The row driver 60 may cooperate with the column driver 62 to provide the DATA412 to the memory circuit 560 for storage prior to transmission as a csimage DATA signal 247 to the light emitting portion of the pixel, for example by enabling a control signal to allow the column driver 62 to store the DATA412 in the memory circuit 560.

In general, the row driver 60 may operate the memory circuit 560 to simultaneously transmit multiple bits of data from the memory to the same node (e.g., node BP _ pre). In this manner, the row driver 60 may modulate the emission time to rearrange the bit order represented by the DATA 412. For example, if DATA412 is equal to 0010, the row driver 60 may operate the memory circuit 560 to cause transmission to follow 1-0-0-0, such that a transmission time of "1" occurs first and no transmission occurs after a time period corresponding to "00". This rearrangement may improve the appearance of visual artifacts on the electronic display 18 while still causing the same gray level as "0010" to be emitted from the sub-pixels.

To further illustrate the reordering associated with the binary pulse width modulation reordering transmission scheme, fig. 24A shows a bit plane diagram 580, fig. 24B shows an error diagram 588, fig. 24C shows a bit plane diagram 582, fig. 24D shows an error diagram 590, fig. 24E shows a bit plane diagram 584, fig. 24F shows an error diagram 592, fig. 24G shows a bit plane diagram 586, and fig. 24H shows an error diagram 594, wherein fig. 24 shows the effect on the overall error reordering as a whole. Fig. 24A-24H show the simulated performance of the electronic display 18 implementing a binary pulse width modulation emission scheme with and without reordering of a six-bit binary number representing a sub-pixel and/or a target gray level for a pixel.

Bit-plane diagram 580 shows the original sequence of the binary pulse width modulation transmission scheme without any reordering of the gray levels represented by the six bits, where all of the bit-plane diagrams 580, 582, 584, and 586 have a light portion 595 corresponding to light emission and a dark portion 596 corresponding to no light emission. The bit-plane diagram 580 is caused by the row driver 60 operating the subpixels 72 to emit light via binary pulse width modulation (e.g., driving the LEDs 230 to emit light without reordering in response to a binary representation of least significant bit to most significant bit, such that 0101 emission follows 1-0-1-0). Each square of the bit-plane diagram shows the relative importance of a particular bit in a particular location shown in terms of the bit-plane that is used to generate a particular gray level ranging from a minimum gray level 598 (corresponding to the fully dark portion 596 of all bit-plane values) to a maximum gray level 599 (corresponding to the fully bright portion 595 of all bit-plane values). For example, the block 597 representing the most significant bit of the bit-plane diagram 580 is logic high for gray levels from 32 to 64 and logic low for gray levels from 0 to 32. This is consistent with the six-bit binary representation of these decimal values. Further, all bit planes are logic low at a gray level of 0 and logic high at a gray level of 64. These binary states correspond to binary value representations of gray levels, e.g., to make the gray level 0, it is desirable that all bit-planes be logic low or 000000. Thus, the bit-plane diagram may visually represent the relative importance of a bit to representing a gray level (e.g., in bit-plane diagram 580, the state of the sixth bit changes the gray level value in a more noticeable manner than the first bit or the least important bit).

When the subpixels 72 are operated to emit light following the binary pulse width modulation emission scheme without reordering, the total error count is high (e.g., 322), as shown in bit-plane diagram 580 and error diagram 588. It may be desirable to reduce the overall error count by reordering because errors appear on the electronic screen of the electronic display 18 as, for example, dynamic false contours, color splitting, and/or flickering of light emitted from one or more pixels.

Since the reordering occurs and the most significant bits are reordered to be transmitted first in order to make the gray level of the bit plane diagram, as shown in bit plane diagram 582 and bit plane diagram 584, the bit plane pattern tends to look like the ideal bit plane shown in bit plane diagram 586. Further, as shown by error map 588, error map 590, error map 592, and error map 594, errors are reduced when reordering occurs. Through reordering of the bit-planes, the perceived image quality can be improved by reducing the error count. An ideal case (e.g., bit-plane map 586) shows how bit-plane map 586 tends towards a gradual bit-plane change, as gray levels increase, and how the total error tends towards the multiple total states represented by the bit-plane by increasing the number of reordering times (e.g., 6 bits correspond to 64 total states, following the relationship that the number of states is 2ⁿWhere n is the number of bits).

Referring again to fig. 23 to illustrate in detail how the row driver 60 operates the memory circuit 560 to perform a binary pulse width modulation reordering transmission scheme, the row driver 60 enables and/or disables control signals to coordinate the transmission of the reordered DATA412 from the memory circuit 560. For example, the row driver 60 may selectively enable and/or disable the Sel signal 415 to transfer the corresponding bit from the inverter pair 408. In some embodiments, the row driver 60 may selectively enable and/or disable the Sel signal 415 in response to the bit plane clock 106 defining the transmission period for the bit position of the DATA 412.

At a high level and for the case of ideal reordering, the row driver 60 may operate the memory circuit 560 to transmit the DATA412 as a csimage DATA signal 247 in order of most significant bit to least significant bit to cause light emission from the subpixels 72 unless the bits of the DATA412 are logic low. If the DATA412 bit is a logic low, the row driver 60 effectively operates the memory circuit 560 to skip a logic low emission period and emit light according to the next logic high emission period. After transmitting all of the logic high bits represented in DATA412, the row driver 60 pauses for a duration equal to the total transmission period of logic low, or in some embodiments, proceeds to process the new DATA412 for transmission. For example, referring to the transmission reordering example 600, if DATA412 is equal to 1111, then a csimage DATA signal 247 is transmitted from the memory circuit 560 as "1111" with the same total transmission period as "1111"; and if DATA412 is equal to "0011", then the csimage.data signal 247 transmitted from the memory circuit 560 is equal to "1100", where the corresponding bit has the same transmission period as "0011"; and if DATA412 is equal to "0100", the DATA is recorded as "1000" for transmission as a csimage. Finally, a single pulse width light emission is generated according to the data corresponding to the binary pulse width modulation transmission scheme.

During reordering, if the bit stored in the memory is zero, the row driver 60 may operate the memory circuit 560 to either transmit the bit or ignore the bit. The row driver 60 may operate in several different operating modes based on the number of reordering to be performed by the row driver 60. For example, in the case of one reordering, the row driver 60 may have two modes of operation, while in the case of three reordering, the row driver 60 may have eight modes of operation.

The row driver 60 may determine which operating mode to operate based at least in part on a comparison of the current emission time to the quadrant time. The row driver 60 may compare the current time with a predefined time frame defining an operation mode (e.g. the first operation mode corresponds to a first transmission length). These different modes of operation may define how the row driver 60 prioritizes image data for transmission. For example, for one reordering example, if the first most significant bit is equal to the binary state "0," the row driver 60 in the first mode of operation may allow light emission according to a bit plane (e.g., a bit plane means how a pixel is normally operated to emit light in response to the binary state of the image data for operating the switch 104); however, if the first most significant bit is equal to the binary state "1", the row driver 60 may allow light emission regardless of the light emission defined by the bit plane such that reordering of the bit plane is performed.

For each mode of operation, the row driver 60 may perform similar control actions regardless of the number of reordering. In each mode of operation, the row driver 60 operates to cycle through each bit of DATA412, starting with the least significant bit (e.g., DATA [0]412A) and proceeding to the bit preceding the most significant bit corresponding to the reordering amount (e.g., DATA [ n-1]412 for one reordering, DATA [ n-2]412 for two reordering). For each iteration, starting with DATA [0], the row driver 60 resets the S node, precharging the memory circuit 560 so that the Sel signal 415B allows the DATA [ n ]412B bits to be transferred to the SR latch 562, and enables the Sel signal 415 corresponding to the current iteration of the least significant bits so that the current iteration of the most or least significant bits is transferred as the CSimage. DATA signal 247.

The row driver 60 may operate the memory circuit 560 differently based on the operating mode. For example, if the row driver 60 is operating in the first mode of operation, the row driver 60 additionally precharges the memory circuit 560 between enabling the Sel signal 415B and allowing the DATA [ n ]412B bit to be transferred to the SR latch 562, and enables the Sel signal 415 corresponding to the current iteration of the least significant bit. Additionally or alternatively, for operating modes other than the first operating mode, the row driver enables the Sel signal 415B, enables other Sel signals 415 corresponding to a number of most significant bits equal to the reordered number (e.g., signals 415 for two reordered DATA [ n ]412B and DATA [ n-1]412, and Sel signals 415 for three reordered DATA [ n ]412B, DATA [ n-1]412, and DATA [ n-2]412), and ends by enabling the Sel signal 415 corresponding to the current iteration of least significant bits (e.g., DATA [0]412A for the first iteration, DATA [1]412 for the second iteration, DATA [2]412 for the third iteration).

Thus, for the two reordering examples, the row driver 60 may operate in four different modes of operation for storing DATA412 having six bits. For a first mode of operation (e.g., corresponding to a first quarter of a gray level value between zero and gray level threshold 16), row driver 60 may reset the S node in addition to the SET signal for each bit of DATA412, Precharge (e.g., enable Precharge signal 416), enable Sel [6]415 and enable SET signal 602, Precharge, enable Sel [5]415 and enable SET signal 602, Precharge, and enable Sel [ n ]415 (e.g., for a first iteration, n is 0, Sel [0]415A is enabled), increment the value of n from zero until DATA [4]412 is reached for each iteration. For the second mode of operation (e.g., the second quarter of a gray level value corresponding to between gray level threshold 16 and twice 32 gray level threshold), in addition to the SET signal for each bit of DATA412, the row driver 60 may reset the S node, precharge, enable Sel [6]415B and enable the SET signal 602, precharge, enable Sel [5]415, and enable Sel [ n ]415, incrementing the value of n from zero until DATA [4]412 is reached for each iteration. For a third mode of operation (e.g., a third quarter of a gray level value between two times 32 and three times 48 of the gray level threshold), in addition to the SET signal for each bit of DATA412, the row driver 60 may reset the S node, precharge, enable Sel [6]415B, enable Sel [5]415 and SET signal 602, precharge, enable Sel [6]415B, and enable Sel [ n ]415, incrementing the value of n from zero until DATA [4]412 is reached for each iteration. For a fourth mode of operation (e.g., a fourth quarter of a gray level value between three times 48 the gray level threshold and four times 64 the gray level threshold), in addition to the SET signal for each bit of DATA412, the row driver 60 may reset the S node, precharge, enable Sel [6]415B, enable Sel [5]415, and enable Sel [ n ]415, incrementing the value of n from zero until DATA [4]412 is reached for each iteration.

To explain differently, fig. 25 includes a bit-plane diagram 604 representing a binary pulse width modulation transmission scheme with two reordering implemented with three color channels. As shown, two reordered bit-plane diagrams 582 are presented in the bit-plane diagram 604 over time and have three color channels of one pixel 70. The row driver 60 may time the emission according to quadrants, where one quadrant 606 may correspond approximately to one quarter of the emission time (e.g., 1/2) for two reordering casesⁿWhere n equals the number of reordering). These quadrants 606 may be in parallel with the previously described modes of operation. Over time, the electronic display 18 may change the emission priority-in other words, a higher emission priority may be given to the two most significant bits of the image data for a particular pixel 70 during emission than to other bits. In some embodiments, the electronic display 18 may manage the emission based on a comparison of the most significant bit to a value represented by a counter to increment the timing signal from binary state "00" to binary state "11" on an edge (e.g., a rising edge or a falling edge) (e.g., where one period of the timing signal corresponds to the duration of one quadrant). Thus, in these embodiments, with respect to the subpixel 72 of the pixel 70, for the first quadrant 606A, if the two Most Significant Bits (MSBs) are equal to the binary state "00", the subpixel 72 may emit according to the bit plane 608 (e.g., according to the binary data stored in the memory 78), but if the two most significant bits are equal to the binary states "11", "01", and/or "10", the subpixel emits light for the duration of the channel emission period (e.g., the first color channel corresponds to the first image channel)Duration 609 of limit 606A) as generally outlined in output logic profile 610.

To summarize the other three quadrants, the subpixel 72, when operating in the second quadrant 606B, emits light according to the bit plane 608 if the two most significant bits are equal to the binary state "01"; emitting light if the two most significant bits are equal to binary states "10" and/or "11"; and if the two most significant bits are equal to the binary state "00", no light is emitted. When operating in the third quadrant 606C, the sub-pixel 72 emits light according to the bit plane 608 if the most significant bit is equal to the binary state "10"; if the two most significant bits are equal to "11", light is emitted; and if the two most significant bits are equal to "00" and/or "01", no light is emitted. Additionally, when operating in the fourth quadrant 606D, the sub-pixel 72 emits light according to the bit plane 608 if the two most significant bits are equal to the binary state "11"; and if the two most significant bits are equal to "00", "01", and/or "10", no light is emitted. Thus, in this way, the sub-pixel 72 is operated to reorder the light emissions corresponding to the two most significant bits such that the light emissions of the two most significant bits occur before emission according to the bit plane 608.

To help provide content, fig. 26 depicts a timing diagram for a binary pulse width modulation transmission scheme with two reordering implemented with three color channels. The timing diagram illustrates the relationship between the substantially simultaneous loading of digital data into the memory 78 and other actions performed by the row driver 60. For example, data loading of the most significant bit of the green channel occurs at time 612 of the emission of the least significant bit of the red channel. Comparing fig. 26 with fig. 25, as depicted in the fourth quadrant 606D, the row driver 60 allows the subpixels 72 to emit light according to the bit plane represented by the data stored in and transferred from the memory 78. As shown in the timing diagram, the total emission period of all three color channels is approximately equal to three times the channel-specific emission period.

An exemplary embodiment of a pixel operated by the row driver 60 to follow a binary pulse width modulation reordering emission scheme is shown in fig. 27, the pixel comprising a memory circuit 560, MWR 406, MSEL 410, inverter pair 408, inverter pair 498, SR latch 562 coupled to an analog driver circuit 561. The figure is intended to be illustrative and not restrictive, for example, various pixel circuits and analog driver circuits may be used in conjunction with the memory circuit 560 and in-pixel memory technology. Fig. 27 shows an example of a memory circuit 560 applied to a Digital Mirror Display (DMD).

In general, the depicted memory circuit 560 is operative to receive DATA412 corresponding to a target gray level for a color channel of the pixel 70 corresponding to the memory circuit 560. As shown, the memory circuit 560 includes different color memory banks for each color channel's memory. In this embodiment, the pixel 70 has a memory circuit for each color channel, rather than a unique subpixel 72 for each color channel (e.g., R-G-B). The row driver 60 may operate the color channels by enabling the Color Group (CG) signal 564. Upon activation of the CG transistor (MCG)565, the stored DATA412 is transmitted to the analog driver circuit 561. The row driver 60 may allow one color channel to be transmitted at a time. Thus, the depicted memory circuit 560 facilitates color sequential output from the individual memory circuits to the shared output circuit coupled to the DMD electrodes.

The row driver 60 may operate the depicted memory circuit 560, similar to the memory circuit 560 of FIG. 23. Thus, for the two reordering examples, the row driver 60 may operate in four different modes of operation, with the mode of operation being selected based on the gray scale values of the DATA 412. After writing the DATA412 to the anti-phase 408, the row driver 60 operates the memory circuit 560 to transfer the stored DATA412 to the SR latch 562 one bit at a time to drive the DMD electrodes through the analog driver circuit 561. The row driver 60 may reorder the DATA412 to create a single pulse width modulated signal from binary pulse width modulated transmit DATA by: the CG signal 564 is selectively enabled and/or disabled (e.g., such that 564B is capable of transmitting red data corresponding to bit plane 7), driving the memory circuit 560 in different operating modes.

For example, and as described above, for the first mode of operation (e.g., corresponding to a gray level between zero and a gray level threshold), the row driver 60 may reset the S node, precharge, enable Sel [ n ]415B and enable the SET signal 602, precharge, enable Sel [ n-1]415 and enable the SET signal 602, precharge, and enable Sel [0] 415A. The row driver may repeat the first mode of operation for each bit of DATA412, incrementing from the first bit DATA [0]412A until DATA [ n-2] is reached (e.g., where 2 corresponds to the number of reordering times). The row driver 60 may operate in the second, third and fourth modes of operation as described in the discussion for fig. 23.

Similar to fig. 27, an exemplary embodiment of a pixel 650 operated by the row driver 60 to follow a single pulse width modulation reordering emission scheme is shown in fig. 28, which includes a memory circuit 654, a color channel select transistor 656, an inverter pair 498, an analog driver circuit 561, and a comparator 490 electrically coupled to a light emitting circuit (not shown). This figure is intended to be illustrative and not limiting, for example, any suitable pixel circuit may be used in conjunction with the memory circuit and in-pixel memory technology, e.g., any combination of additional and/or alternative embodiments of suitable switching elements (e.g., the depicted MOSFETs). Fig. 28 is included to illustrate an example of a pixel 650 applied to a Liquid Crystal Display (LCD), and the operation of the memory circuit 654 and the comparator 490 as a whole may follow the process depicted and described with respect to fig. 22.

In general, the pixels 650 receive the DATA412 during a DATA write process managed by the row driver 60 that enables the write _ en signal 414 to allow the DATA412 bits to be written into memory (e.g., inverter pair 408). During DATA writing, the pixel 650 receives the gray scale digital DATA (DATA)412R of the red channel, the gray scale digital DATA (DATA)412G of the green channel, and the gray scale digital DATA (DATA)412B of the blue channel, wherein the pixel 650 receives the DATA412 to each of the memory circuits 654 in serial DATA transmission and/or parallel DATA transmission. As DATA412 is written into the memory of pixel 650, comparator 490 performs an automatic comparison of DATA412 from the memory with a count transmitted from a counting circuit (such as counter 130) and/or any suitable counting method. Using the same approach as described with respect to comparator 490 in fig. 21, comparator 490 transmits a "1" if DATA412 is the same as count 658 from the counting circuitry (e.g., all bits are matched) or a "0" if not equal (e.g., one or more bits do not match). The row driver 60 transmits the CG signal 564 to respective ones of the color channel select transistors 656 to enable color channels (e.g., red, green, or blue color channels) for color sequential emission for emission via the shared output stage. The MTCH bits are transmitted to the memory circuit 492 for storage when the row driver 60 enables transmission from the color channels. The row driver 60 may enable the EMIT signal to be transmitted according to the stored MTCH bits, as previously described. Additionally or alternatively, the row driver 60 may enable a GHOST signal that causes, at least in part, no transmission to occur regardless of the MTCH bits stored in the memory circuit 492. To EMIT light, the row driver 60 activates an EMIT signal, causing the stored MTCH bits to be transmitted to the analog driver circuit 561, which is coupled to a high reference voltage and a low reference voltage. The stored MTCH bits are transmitted to analog driver circuit 561, which activates and/or deactivates an MS 566 (e.g., MS 566A, MS 566B) coupled to the LC electrode in response to a reference voltage. Although depicted as 5V and VSS, the reference voltage may be any suitable voltage for driving the LC electrodes when MS 566 is activated.

Following the above structure, the pixel 650 may be operated to emit according to a single pulse width modulation emission scheme. The row driver 60 may operate different embodiments to transmit according to different transmission schemes. For example, if the digital data transmitted to the pixel 650 changes and the comparator 490 is removed, the color channel of the pixel 650 may typically be operated according to a binary pulse width modulation emission scheme.

As discussed throughout this disclosure, it should be understood that in-pixel memory technology is effective for various embodiments and display technologies. It should also be understood that additional or alternative reference voltages may be used for each reference voltage discussed or disclosed in the figures. Additionally or alternatively, it should be noted that although described as reducing or eliminating reliance on the use of a frame buffer, in some embodiments, in-pixel memory techniques may be used in series with a frame buffer. Further, although the memory circuit has been described as storing six, twelve, eight, and/or sixteen bits, it should be understood that any suitable number of bits may be stored using any suitable memory structure.

As briefly discussed in fig. 21, a slight adjustment to the in-pixel memory technology may generally be applied to allow the memory 78 to be moved into the smart buffer, as opposed to or in addition to including the memory 78 in the pixel 72 itself. Fig. 29 illustrates this generally with an in-pixel memory architecture electronic display 700 and a smart buffer architecture electronic display 702. As shown, the in-pixel memory structure electronic display 700 includes a memory 78 located in each sub-pixel 72 in an active area 704 of the electronic display 18, where the active area 704 includes all of the light emitting components of the electronic display and a communication coupling for supporting data transmission to the light emitting components. In a memory-in-pixel architecture electronic display 700, digital data is transferred from memory 708 to each respective sub-pixel 72 for local buffering in memory 78. In some implementations, digital data is transferred from memory 708 to source region 710 for local buffering (e.g., buffering within subpixel 72) before being transferred to memory 78. However, memory substantially similar to memory 78 may be included in smart buffer 712 of smart buffer architecture electronic display 702 to still eliminate or at least reduce reliance on a frame buffer, but additionally remove memory 78 from active area 704. By moving the memory 78 into the smart buffer 712, the row driver 60 may operate the input latch 714 and the output latch 716 to arbitrate light emission from each subpixel 72 via analog output circuitry (e.g., driver 80). Here, smart buffer 712 may represent any suitable buffer memory disposed in the integrated circuit of electronic display 18, but outside the active area of electronic display 18.

Fig. 30 shows an example of a smart buffer implementation of memory 78 circuitry, including memory circuit 750, comparator 752, memory circuit 754, and output inverter 756. The circuit functions similarly to the memory circuit shown in fig. 21, where the smart buffer of fig. 30 receives digital data in response to a write enable (write _ en) control signal 757 that allows the digital data to be written to the memory circuit 750 (e.g., inverter pair). Accordingly, the operation of memory circuit 754 and comparator 752, in its entirety, may follow the process depicted and described with respect to fig. 22. The smart buffer of fig. 30 may have memory 78 circuitry for each sub-pixel 72 of the active area 704. The digital data values may be stored in memory circuit 750 until a new digital data value is written into the intelligent buffer for a particular subpixel 72.

When the digital data is transferred to the memory circuit 750, the comparator 752 determines whether all bits of the digital data match the output (CNT/CNT _ b) from the counting circuit. Similar to the previously described embodiments, the counting circuit counts to allow emission according to the gray scale represented by the digital data. The comparator may output a logic zero "0" as the MTCH bit until the digital data matches the count-at which time the comparator outputs a logic one "1" as the MTCH bit. The MTCH bits are typically transmitted to a memory circuit 754 for storage while the value of the inverted MTCH bits are transmitted onto an output inverter 756 and ultimately onto the corresponding subpixel to cause and/or stop emission.

Continuing with the transmission path of the MTCH bits, FIG. 31 depicts a pixel circuit 780 that may be used in conjunction with the smart buffer circuit of FIG. 30. Pixel circuit 780 includes an input latch 782 (e.g., an inverter pair) and an output latch 784 (e.g., an inverter pair), both of which are operative to latch digital data transferred from an intelligent buffer (e.g., intelligent buffer 712) in response to a write enable (write _ en) control signal 786. Upon latching, the digital data may be automatically transferred to the gate of the drive transistor 788. Similar to that discussed above, drive transistor 788 is activated in response to digital data, depending on the value of the digital data, and passes a drive current through the light emitting circuit (e.g., light emitting diode 790) of pixel circuit 780.

Accordingly, technical effects of the present disclosure include processing techniques for implementing memory in one or more pixels of an electronic display to improve image data for rendering. Technologies include systems and methods for receiving image data, storing the image data in a memory within a pixel, and transmitting the image to a drive circuit to operate a light emitting element of the pixel to emit light. Furthermore, the different emission schemes may be performed using any suitable pixel circuit implementing in-pixel memory technology, including binary pulse width modulation emission schemes, binary pulse width modulation reordering schemes, single pulse width modulation emission schemes, and pulse density modulation emission schemes, while still benefiting from reducing the bandwidth used to transmit the same image without using in-pixel memory technology. These pixel circuits implementing the emission scheme may be coupled to pixel circuits with hybrid drivers to increase the responsiveness of the LEDs to electrical signals.

The techniques described herein may be applied to and integrated with various display technologies and should not be limited to the particular embodiments depicted and/or described herein. For example, a pixel with memory is shown with a light emitting diode as the light modulation device, however, in-pixel memory technology can generally be applied to different pixel circuits to support various display technologies using various light modulation devices. In this way, suitable pixel circuits supporting light emission via light emitting diodes, digital mirror displays, organic light emitting diodes, or circuits supporting liquid crystal displays, plasma displays, or dot matrix displays may each have memory in the pixels to achieve improvements in at least data transmission bandwidth and ease of programming the pixels.

The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

The technology described and claimed herein is cited and applied to specific examples of physical and physical properties, which significantly improve the art and are, therefore, not abstract, intangible or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [ performing ] [ function ]. or" step for [ performing ] [ function ]. these elements will be construed in accordance with 35u.s.c.112 (f). However, for any claim containing elements specified in any other way, these elements will not be construed according to 35u.s.c.112 (f).

Exemplary embodiments may include：

Exemplary embodiment 1: an electronic display, comprising:

an active area including first pixels formed in the active area, wherein the first pixels are configured to emit light in response to image data; and

a controller configured to transmit the image data to the first pixel;

wherein the first pixel includes:

an organic light emitting diode configured to emit the light in response to the image data;

a memory configured to digitally store the image data received from the controller; and

a driver circuit configured to receive the image data from the memory, wherein the driver circuit is configured to cause the organic light emitting diode to emit the light in response to the image data.

Exemplary embodiment 2: the electronic display of exemplary embodiment 1, wherein the controller is configured to transmit the image data to the memory of the first pixel via a data line of the active area.

Exemplary embodiment 3: the electronic display of example embodiment 1, wherein the controller is configured to transmit the image data to a multiplexing circuit via data lines of the active area, wherein the controller is configured to control the multiplexing circuit to arbitrate transmission of the image data into the memory of the first pixel.

Exemplary embodiment 4: the electronic display of example embodiment 3, wherein the image data includes two or more color channels corresponding to an image to be displayed, and wherein the controller is configured to program the memory associated with a first color channel of the image data at a first time to cause the memory of the first pixel to be programmed via enabling a first multiplexing control signal, and wherein the controller is configured to program the memory associated with a second color channel of the image data at a second time to cause the memory of a second pixel to be programmed via enabling a second multiplexing control signal.

Exemplary embodiment 5: the electronic display of example embodiment 1, wherein the controller is configured to program the memory of the first pixel with the image data, wherein the image data is associated with a first color channel and programmed at a first time, wherein the controller is configured to program the memory of the first pixel with second image data, and the second image data is associated with a second color channel and programmed at a second time.

Exemplary embodiment 6: the electronic display of example embodiment 1, wherein the memory of the first pixel is configured to operate as an in-display frame buffer of the first pixel in the electronic display.

Exemplary embodiment 7: the electronic display of example embodiment 1, wherein the memory of the first pixel is configured to receive a counter signal and the image data, wherein the memory is configured to operate a switch by transmitting the image data based at least in part on the counter signal to cause the organic light emitting diode to emit the light according to a binary pulse width modulation emission scheme.

Exemplary embodiment 8: the electronic display of example embodiment 1, wherein the driver circuit of the first pixel comprises a comparator configured to receive a signal indicative of a number and the image data, and wherein the comparator is configured to operate a switch based at least in part on the image data and the signal indicative of a number to cause the organic light emitting diode to emit the light according to a single pulse width modulation emission scheme.

Exemplary embodiment 9: the electronic display of exemplary embodiment 1, wherein the driver circuit includes an adder configured to add the image data to a limit value of an accumulator during a summing process, wherein a carry from the summing process is configured to operate a switch to cause the organic light emitting diode to emit the light according to a pulse density modulated emission scheme.

Exemplary embodiment 10: a color specific sub-pixel in an electronic display, comprising:

a memory configured to receive a signal indicative of a value within a data range;

a first terminal configured to receive a first voltage signal;

a second terminal configured to receive a second voltage signal; and

a light emitting diode configured to emit light based at least in part on the signal indicative of the value within the data range, wherein the memory is configured to enable transmission of a current through the light emitting diode to cause light emission, and wherein the current is based at least in part on the first voltage signal and the second voltage signal.

Exemplary embodiment 11: the sub-pixel according to exemplary embodiment 10, wherein the memory comprises a register configured to receive a counter signal and the signal indicative of the value within the data range, wherein the memory is configured to operate a switch by transmitting the signal indicative of the value within the data range based at least in part on the counter signal so as to cause the organic light emitting diode to emit light according to a binary pulse width modulation emission scheme.

Exemplary embodiment 12: the sub-pixel according to exemplary embodiment 10, comprising a comparator configured to receive a signal indicative of a number and a signal indicative of a value within the data range, and wherein the comparator is configured to operate the light emitting diode to emit light according to a single pulse width modulation emission scheme based on the signal indicative of a value within the data range and the signal indicative of a number.

Exemplary embodiment 13: the sub-pixel according to exemplary embodiment 10, comprising an adder configured to add the signal indicative of the value within the data range to a limit value of an accumulator configured to be coupled to the adder during a summing process, and wherein a carry from the summing process is configured to operate the light emitting diode to emit light according to a pulse density modulated emission scheme.

Exemplary embodiment 14: the sub-pixel according to example embodiment 10, wherein the memory is configured to function as a frame buffer to store the signal indicative of the value within the data range for a period of time before allowing the signal indicative of the value within the data range to be used to cause light to be emitted from the light emitting diode.

Exemplary embodiment 15: a pixel, comprising:

a first sub-pixel of the pixel, wherein the first sub-pixel corresponds to a first color channel, wherein the first sub-pixel comprises:

a first memory configured to store a first signal indicative of a first value within a first data range for transferring image data of the first color channel of the pixel; and

a first driver circuit configured to receive the first signal indicative of the first value from the first memory, wherein the first driver circuit is configured to cause a first light emitting diode to emit light based at least in part on the first signal indicative of the first value; and

a second sub-pixel of the pixel, wherein the second sub-pixel corresponds to a second color channel, wherein the second sub-pixel comprises:

a second memory configured to store a second signal indicative of a second value within a second data range for transferring image data of the second color channel of the pixel; and

a second driver circuit configured to receive the second signal from the second memory indicative of the second value, wherein the second driver circuit is configured to cause a second light emitting diode to emit light based at least in part on the second signal indicative of the second value.

Exemplary embodiment 16: the pixel according to example embodiment 15, wherein the first subpixel is configured to be programmed with the first signal indicative of a first value at a first time, wherein the second subpixel is configured to be programmed with the second signal indicative of a second value at a second time, and wherein the first time occurs earlier than the second time.

Exemplary embodiment 17: the pixel of exemplary embodiment 16, wherein the first signal is configured to be transmitted to the first subpixel through a multiplexing circuit configured to operate in response to a first control signal transmitted at the first time, and wherein the first signal is configured to stop transmission to the first subpixel in response to the multiplexing circuit receiving a second control signal transmitted at the second time.

Exemplary embodiment 18: the pixel of exemplary embodiment 15, wherein the first memory is configured to operate as a frame buffer for the first sub-pixel.

Exemplary embodiment 19: the pixel of exemplary embodiment 15, wherein the first subpixel comprises a first counter, wherein the first memory is configured to receive an output from the first counter, wherein the output from the first memory is configured to activate a switch in response to the output from the counter, and wherein the output from the first memory is configured to operate the first light emitting diode to emit the light according to a binary pulse width modulation emission scheme.

Exemplary embodiment 20: the pixel of exemplary embodiment 15, wherein the first driver circuit includes a comparator configured to receive an output from the first memory and an output from a counter configured to correspond to a time difference between increments of gray scale levels associated with the first color channel, and wherein the first driver circuit is configured to operate the first light emitting diode based at least in part on the output from the comparator.

Exemplary embodiment 21: an electronic display, comprising:

a memory formed in an active area of the electronic display or in an integrated circuit of the electronic display located outside of the active area, wherein the memory is configured to store a digital data signal indicative of values within a data range;

a driver disposed in the active area, wherein the driver is configured to generate one or more analog electrical signals in response to the digital data signals; and a light modulation device disposed on the active area, wherein the light modulation device is configured to emit light based at least in part on the one or more analog electrical signals.

Exemplary embodiment 22: the electronic display of exemplary embodiment 21, wherein the light modulating device comprises a light emitting diode, a digital mirror display, an organic light emitting diode, or a device supporting a liquid crystal display, a plasma display, or a dot matrix display, or any combination thereof.

Exemplary embodiment 23: the electronic display of example embodiment 21, wherein the light modulation device comprises a light emitting diode, wherein the light emitting diode and the driver are configured to support a global cathode or global anode configuration configured to emit light using the one or more analog electrical signals.

Exemplary embodiment 24: the electronic display of example embodiment 21, wherein the light modulation device comprises a light emitting diode, wherein the light emitting diode and the driver are configured to support a global cathode or global anode configuration configured to emit light using the one or more analog electrical signals.

Exemplary embodiment 25: the electronic display of example embodiment 24, wherein the memory includes transistors configured to activate in response to a selection control signal, wherein the first subset of digital data signals is configured to be transmitted to the driver in response to activation of the transistors.

Exemplary embodiment 26: the electronic display of example embodiment 24, wherein the first pair of inverters is configured to output the first subset of the digital data signals to a sense amplifier before outputting it to the driver.

Exemplary embodiment 27: the electronic display according to example embodiment 24, comprising a switch/reset (SR) latch configured to be coupled to an output of the first inverter pair, and a second inverter pair configured to be coupled to an output of the switch/reset latch, wherein the switch/reset latch and the second inverter pair are configured to enable a binary pulse width modulation transmission scheme with reordering.

Exemplary embodiment 28: the electronic display of example embodiment 24, wherein the memory includes a second inverter pair configured to store a second subset of the digital data signals transmitted to the pixels.

Exemplary embodiment 29: the electronic display of example embodiment 28, wherein the first subset of the digital data signals and the second subset of the digital data signals are transmitted to the first inverter pair in response to a controller enabling a write enable control signal.

Exemplary embodiment 30: a pixel of an electronic display, comprising:

a memory configured to store a first digital data signal transmitted from a column driver to the pixel, wherein the first digital data signal is configured to correspond to an image to be displayed by having values within a data range to convey a portion of the image, the memory comprising:

one or more inverter pairs configured to receive the first digital data signal transmitted from a column driver to the memory in the pixel; and

a comparator configured to receive the first digital data signal and a second digital data signal from the one or more inverter pairs, wherein the comparator is configured to output a control signal in response to determining when the first digital data signal matches the second digital data signal; and

a driver configured to receive the control signal from the memory, wherein the driver is configured to cause light to be emitted from the pixel based at least in part on the control signal.

Exemplary embodiment 31: the pixel of example embodiment 30, comprising a counter configured to output an indication of a current number counted as the second digital data signal to the comparator.

Exemplary embodiment 32: the pixel according to example embodiment 30, comprising a transistor configured to enable precharging the memory.

Exemplary embodiment 33: the pixel of example embodiment 30, comprising an additional inverter pair separate from the one or more inverter pairs, the additional inverter pair configured to cause the output from the comparator to be stored as a control signal prior to transmission to the driver.

Exemplary embodiment 34: the pixel according to example embodiment 33, wherein the additional inverter pair is reset between a first storage of the first output and a second storage of the second output.

Exemplary embodiment 35: the pixel according to example embodiment 30, comprising a transistor configured to enable the control signal to be output from the comparator to be transmitted to the driver, wherein the transistor is configured to activate in response to an emission enable signal.

Exemplary embodiment 36: the pixel according to example embodiment 30, comprising additional memory corresponding to a color channel associated with displaying the image, wherein the additional memory is configured to be coupled to the driver.

Exemplary embodiment 37: an electronic display, comprising:

a controller configured to generate one or more digital data signals to cause an image to be displayed;

a buffer comprising a first memory configured to store a first digital data signal of the one or more data signals, wherein the first digital data signal is configured to cause a portion of the image to be displayed on the electronic display; and

a plurality of pixels configured to emit light in response to the one or more digital data signals, wherein a respective pixel of the plurality of pixels comprises:

a driver configured to receive the first digital data signal from the first memory, wherein the driver is configured to generate an analog data signal in response to the first digital data signal transmitted from the first memory; and

a light emitting circuit configured to be coupled to the driver, wherein the light emitting circuit is configured to emit light based at least in part on the analog data signal.

Exemplary embodiment 38: the electronic display of example embodiment 37, comprising a selection circuit configured to be coupled to an output of the first memory and an output of the second memory, wherein the buffer further comprises a second memory to store a second digital data signal, and wherein the selection circuit is configured to select the first memory to output the first digital data signal to the driver independently of selecting the second memory.

Exemplary embodiment 39: the electronic display of example embodiment 38, wherein the selection circuit is configured to be coupled to an output of a pair of inverters, wherein the pair of inverters is configured to store an output from the first memory when the selection circuit operates in a first state, and wherein the pair of inverters is configured to store an output from the second memory when the selection circuit operates in a second state.

Exemplary embodiment 40: the electronic display of example embodiment 37, wherein the respective pixel includes a counting circuit configured to be coupled to the first subpixel, wherein the first subpixel includes a comparator, and wherein the comparator is configured to compare an output from the counting circuit with an output from the first memory.

Exemplary embodiment 41: a pixel circuit for an electronic display, comprising:

a memory configured to store a digital data signal indicative of a value within a data range;

a light emitting diode configured to emit light based at least in part on the digital data signal;

an initialization transistor configured to initialize the pixel circuit before the light emitting diode emits light; and

a drive transistor configured to activate based at least in part on the digital data signal.

Exemplary embodiment 42: the pixel circuit of example embodiment 41, comprising a voltage drive circuit configured to be coupled to an anode of the light emitting diode, wherein the voltage drive circuit is configured to boost the anode of the light emitting diode at a beginning of a light emission period of the light emitting diode.

Exemplary embodiment 43: the pixel circuit according to example embodiment 41, wherein the drive transistor is configured as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and wherein the pixel circuit includes a plurality of p-type or n-type MOSFETs configured to cause the light emitting diode to emit light in response to a control signal.

Exemplary embodiment 44: the pixel circuit according to example embodiment 41, comprising a reset circuit configured to be coupled in parallel with the light emitting diode, wherein the reset circuit is configured to reset an anode voltage of the light emitting diode after a light emitting period.

Exemplary embodiment 45: the pixel circuit of example embodiment 41, comprising a hybrid driver, wherein the hybrid driver comprises voltage-driven and current-driven circuits, and wherein the hybrid driver is configured to operate the light emitting diode to emit light based at least in part on the digital data signal in response to a voltage data signal, a plurality of reference voltages, and an image data control signal.

Exemplary embodiment 46: the pixel circuit of example embodiment 41, comprising an auto-zero transistor configured to activate in response to an auto-zero control signal, wherein a voltage value of a source node of the auto-zero transistor is configured to increase until a voltage value of the source node of the auto-zero transistor equals a voltage value of a gate voltage of the drive transistor.

Exemplary embodiment 47: the pixel circuit of example embodiment 41, wherein the memory includes a register configured to store the digital data signal, and a comparator configured to compare the digital data signal with a number configured to be generated by a counter, and wherein the memory is configured to transmit an output from the comparator to activate the drive transistor.

Exemplary embodiment 48: the pixel circuit according to example embodiment 41, comprising additional circuitry configured to operate with the memory to activate the drive transistor to cause light emission according to a binary pulse width modulation emission scheme, a single pulse width modulation emission scheme, or a pulse density modulation emission scheme, or any combination thereof.

Exemplary embodiment 49: an electronic display, comprising:

a controller configured to generate one or more digital data signals to cause an image to be displayed; and

a plurality of pixels configured to emit light in response to the one or more digital data signals, wherein a first pixel of the plurality of pixels comprises:

a memory configured to receive a first digital data signal generated by the controller based at least in part on the image;

a light emitting circuit configured to emit light based at least in part on the first digital data signal;

an initialization transistor configured to initialize the first pixel before the light emitting circuit emits light; and

a drive transistor configured to activate based at least in part on the first digital data signal.

Exemplary embodiment 50: the electronic display of example embodiment 49, comprising a second pixel of the plurality of pixels, wherein the memory of the second pixel is configured to receive a second digital data signal at a different time than the time at which the memory of the first pixel is configured to receive the first digital data signal.

Exemplary embodiment 51: the electronic display of exemplary embodiment 50, wherein the controller is configured to arbitrate the transmission of the one or more digital data signals to the one or more pixels by controlling a multiplexing circuit.

Exemplary embodiment 52: the electronic display of example embodiment 49, wherein the light emitting circuit comprises a light emitting diode, and wherein the first pixel comprises a voltage drive circuit configured to boost an anode of the light emitting diode during an emission period of the light emitting diode.

Exemplary embodiment 53: the electronic display of example embodiment 49, wherein the first pixel includes a hybrid drive circuit configured to operate the light emitting diode to emit light based at least in part on the first digital data signal in response to a voltage data signal, a plurality of reference voltages, and an image data control signal.

Exemplary embodiment 54: the electronic display of exemplary embodiment 49, wherein the light emitting circuit comprises: a light emitting diode, an organic light emitting diode, or a circuit supporting a liquid crystal display, a plasma display panel, a dot matrix display, a digital mirror driven display, or any combination thereof.

Exemplary embodiment 55: a method, comprising:

transferring, via a controller, a first value into a first memory of a first pixel at a first time;

performing an initialization process via the controller to prepare the first pixel to emit light according to the first value;

performing, via the controller, a programming process to program a node of the first pixel with one or more voltage values; and

performing, via the controller, an emission process, wherein performance of the emission process is configured to cause light to be emitted from a light emitting circuit of the first pixel.

Exemplary embodiment 56: the method of example embodiment 55, wherein transmitting the first value to the first memory includes the controller arbitrating programming of the first memory and the second memory for the second pixel by:

enabling, via the controller, a first multiplexing control signal to allow the first value to be transferred into the first memory at the first time; and

disabling, via the controller, a second multiplexing control signal to stop transmitting the first value into the second memory at the first time.

Exemplary embodiment 57: the method of example embodiment 45, wherein the programming process includes:

enabling, via the controller, an auto-zero control signal; and

disabling, via the controller, the auto-zero control signal after a defined amount of time.

Exemplary embodiment 58: the method of exemplary embodiment 45, wherein the transmitting comprises:

enabling, via the controller, a voltage drive control signal configured to cause boosting of the light emitting circuit; and

transmitting, via the controller, an image data control signal configured to activate a drive transistor according to a binary pulse width modulation transmission scheme, a single pulse width modulation transmission scheme, a pulse density modulation transmission scheme, or any combination thereof.

Exemplary embodiment 59: the method according to example embodiment 45, comprising performing a reset procedure to reset the lighting circuit in preparation for future light emission.

Exemplary embodiment 60: the method of example embodiment 45, wherein the initialization process includes enabling, via the controller, a selection control signal to cause charging of a capacitor, wherein by charging the capacitor, the capacitor is configured to cause a drive current to be transmitted through the first pixel.

Claims

1. An electronic display, comprising:

an active area comprising a row of pixels, wherein the row of pixels comprises a first subpixel and a second subpixel, and wherein the first subpixel is configured to emit light in response to first image data; and

a controller configured to transfer the first image data to the first subpixel at a first time and configured to transfer second image data to the second subpixel at a second time;

wherein the first sub-pixel comprises:

a first current source configured to generate a first current;

a first organic light emitting diode configured to emit the light in response to the first current;

a first memory configured to digitally store the first image data received from the controller; and

a first driver circuit configured to receive a first control signal generated based at least in part on the first image data stored in the first memory, wherein the first driver circuit is configured to cause the first organic light emitting diode to emit the light at least in part by transmitting the first current to the first organic light emitting diode in response to the first control signal.

2. The electronic display of claim 1, wherein the first memory of the first subpixel is configured to receive a counter signal and the first image data, wherein the first memory of the first subpixel is configured to operate a switch by transmitting the first control signal, wherein the first control signal is generated based at least in part on the counter signal and the first image data, wherein the first control signal causes the first organic light emitting diode to emit the light according to a binary pulse width modulation emission scheme.

3. The electronic display of claim 1, wherein the first memory of the first subpixel comprises a comparator configured to receive a signal indicative of a number and the first image data, and wherein the comparator is configured to generate the first control signal to cause the first organic light emitting diode to emit the light according to a single pulse width modulation emission scheme based at least in part on the first image data and the signal indicative of a number.

4. The electronic display of claim 1, wherein the first memory comprises an adder configured to add the first image data to a limit value of an accumulator during a summing process, and wherein a carry from the summing process is configured to generate a first control signal for operating a switch to cause the first organic light emitting diode to emit the light according to a pulse density modulated emission scheme.

5. The electronic display of claim 1, wherein the first subpixel comprises:

a counter that receives a bit plane clock, wherein the bit plane clock has a timing period that increases over time to correspond to a level of influence of a particular bit in the first image data such that a least significant bit of the first image data is associated with a smaller timing period than a most significant bit of the first image data, wherein the counter counts edges of the bit plane clock; and

a switch that, when closed, connects a common voltage to a current source to drive the first organic light emitting diode to emit the light;

wherein the first memory includes a register that receives the first image data, an output of the counter, and a data clock;

wherein the register is configured to close the switch to cause the first organic light emitting diode to emit the light by an amount corresponding to the first image data in response to a comparison of the output of the counter and the first image data.

6. An electronic display, comprising:

a memory formed in an active area of the electronic display or formed in an integrated circuit of the electronic display located outside of the active area, wherein the memory is configured to store a plurality of bits indicating values within a data range;

an analog driver circuit disposed in the active area, wherein the analog driver circuit is configured to generate one or more analog electrical signals in response to a first control signal generated using the plurality of bits in response to a second control signal that causes one or more of the plurality of bits to be used to generate the first control signal; and

a light modulation device disposed on the active area, wherein the light modulation device is configured to emit light based at least in part on the one or more analog electrical signals.

7. The electronic display of claim 6, wherein the light modulating device comprises a light emitting diode, a digital mirror display, an organic light emitting diode, or a device supporting a liquid crystal display, a plasma display, or a dot matrix display, or any combination thereof.

8. The electronic display of claim 6, wherein the memory comprises three or more inverter pairs, each configured to store a respective bit of the plurality of bits.

9. The electronic display of claim 8, wherein each of the three or more inverter pairs is configured to output a respective bit to a sense amplifier at a different time before outputting the respective bit to the analog driver circuit.

10. The electronic display of claim 8, comprising a switch/reset latch configured to output a signal to a gate of a switch, the switch configured to couple an input of a second inverter pair to ground in response to a signal from the switch/reset latch.

11. The electronic display of claim 6, wherein the memory is configured to output one or more bits of the plurality of bits to a circuit configured to generate the first control signal based at least in part on the plurality of bits and a second control signal comprising a plurality of signals indicative of a count held by a counter circuit.

12. The electronic display of claim 11, wherein the circuit comprises a comparator, wherein the one or more bits are transmitted from the memory to the comparator, and wherein the comparator generates the first control signal in response to determining that the count matches a value within the data range.

13. The electronic display of claim 6, wherein:

the memory includes:

one or more inverter pairs configured to receive respective ones of the plurality of bits transmitted from a column driver to the memory in a pixel as a first digital data signal;

a comparator configured to receive a second digital data signal and the first digital data signal from the one or more inverter pairs, wherein the comparator is configured to output the one or more analog electrical signals as control signals to the analog driver circuit in response to determining when the first digital data signal matches the second digital data signal; and

an additional inverter pair separate from the one or more inverter pairs, the additional inverter pair configured to store the output from the comparator as a control signal prior to transmission to the analog driver circuit, wherein the additional inverter pair is configured to reset between a first storage of a first output and a second storage of a second output; and is

The analog driver circuit is configured to receive the control signal from the memory, wherein the analog driver circuit is configured to cause light to be emitted from the pixel based at least in part on the control signal.

14. A pixel circuit for an electronic display, comprising:

a drive transistor coupled between a current source and a light emitting diode configured to emit light in response to a signal from the current source through the drive transistor;

a comparator configured to compare the digital data signal to an indication of a number and to transmit an output to activate the drive transistor based on the comparison, wherein a counter is configured to generate the indication of the number; and

an initialization transistor configured to initialize the pixel circuit before the light emitting diode emits light.

15. The pixel circuit of claim 14, comprising a voltage drive circuit configured to be coupled to an anode of the light emitting diode, wherein the voltage drive circuit is configured to boost the anode of the light emitting diode at a beginning of a light emission period of the light emitting diode.

16. The pixel circuit according to claim 14, wherein the drive transistor is configured as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and wherein the pixel circuit comprises a plurality of p-type or n-type MOSFETs configured to cause the light emitting diode to emit light in response to a control signal.

17. The pixel circuit of claim 14, comprising a reset circuit configured to be coupled in parallel with the light emitting diode, wherein the reset circuit is configured to reset an anode voltage of the light emitting diode after an emission period.

18. The pixel circuit of claim 14, comprising a hybrid driver, wherein the hybrid driver comprises a voltage driver and a current driver circuit, and wherein the hybrid driver is configured to operate the light emitting diode to emit light based at least in part on the digital data signal in response to a voltage data signal, a plurality of reference voltages, and an image data control signal.

19. The pixel circuit of claim 14, comprising additional circuitry configured to operate with the memory to activate the drive transistor to cause light emission according to a binary pulse width modulated emission scheme, a single pulse width modulated emission scheme, or a pulse density modulated emission scheme, or any combination thereof.

20. The pixel circuit of claim 14, wherein

The memory includes a register configured to store the digital data signal; and is

The pixel circuit is configured to be controlled by a controller, wherein the controller is configured to:

initializing the memory;

precharging the comparator; and

incrementing the number provided by the counter to the comparator.