JP2011164425A - Image display device - Google Patents

Image display device Download PDF

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Publication number
JP2011164425A
JP2011164425A JP2010028186A JP2010028186A JP2011164425A JP 2011164425 A JP2011164425 A JP 2011164425A JP 2010028186 A JP2010028186 A JP 2010028186A JP 2010028186 A JP2010028186 A JP 2010028186A JP 2011164425 A JP2011164425 A JP 2011164425A
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Japan
Prior art keywords
circuit
display device
color
image display
pixel
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JP2010028186A
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Japanese (ja)
Inventor
Hajime Akimoto
Norihiro Nakamura
則裕 中村
秋元  肇
Original Assignee
Canon Inc
Hitachi Displays Ltd
キヤノン株式会社
株式会社 日立ディスプレイズ
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Priority to JP2010028186A priority Critical patent/JP2011164425A/en
Publication of JP2011164425A publication Critical patent/JP2011164425A/en
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
    • Y02B20/36Organic LEDs, i.e. OLEDs for general illumination

Abstract

To reduce the size of a color balance adjustment circuit of an organic EL display device.
A first gradation reference voltage corresponding to an upper limit value of a gradation voltage and a second gradation reference corresponding to a lower limit value for each of three types of organic EL elements of RGB arranged in a display unit. Voltage and generate. Each gradation reference voltage is adjusted using an electronic volume. After the assembly of the organic EL display device, the electronic volume is adjusted so that a suitable image quality can be obtained. The fuse memory element 300 is used to store electronic volume control data at that time. In the display operation of the organic EL display device 2, control data is read from the fuse memory element 300 to the adjustment value register group 304 and used for control of the electronic volume.
[Selection] Figure 10

Description

  The present invention relates to an image display device in which a plurality of types of light emitting elements having different emission colors, such as organic EL (Electro-Luminescence) elements of R (red), G (green), and B (blue), are arranged.

  Conventionally, an organic EL display that is a display device using an organic EL element has been proposed. Since the organic EL element is a self-luminous element, a backlight necessary for a liquid crystal display device is unnecessary, and it is suitable for thinning and has a feature that a viewing angle is close to 180 °. Therefore, the organic EL display is highly expected to be put to practical use as a next-generation display device.

  By using different light emitting materials for the light emitting layer of the organic EL element, a plurality of types of pixels each emitting light of a specific color can be formed. For example, the image display apparatus can be configured by arranging three types of pixels that emit RGB three primary colors separately from each other in the display unit. Such an element that directly emits light of a target color has high luminous efficiency and can obtain a bright image with low power consumption.

  On the other hand, since the organic EL material has different luminance characteristics for each RGB material, the luminance may vary for each RGB pixel. Therefore, there is a problem that the color balance of the image is shifted and accurate color reproduction cannot be performed on the video signal.

  There are two types of driving methods for organic EL display devices: a passive type using a simple matrix and an active type using a thin film transistor (TFT). A TFT used in an active mode uses a non-single crystal semiconductor for an active layer, and due to its characteristics, variation between elements is larger than a transistor using a single crystal for an active layer. Further, the correlation is not guaranteed even in the proximity. Specifically, the voltage-to-current conversion gain of the driving TFT varies between elements, or between glass substrates to be manufactured, and the start lot due to variations in TFT threshold, carrier mobility, manufacturing process (for example, W / L of the gate), etc. It can be different between. As a result, the current value supplied to the organic EL element by the driving TFT in accordance with the image signal varies between pixels. That is, the organic EL element cannot emit light with the brightness expected from the image signal, which may cause a problem that the display area and the panel appear as variations in brightness.

  In order to solve the above-described problems, an image display apparatus has been proposed that can be adjusted so that the display quality (display brightness, color balance, contrast) of an image becomes optimum after the organic EL panel is assembled. Patent Documents 1 and 2 below disclose techniques that enable such adjustment after assembly.

JP 2004-354684 A JP 2007-108248 A JP 2008-191348 A

  In recent years, image display devices have been required to be smaller and more integrated, and organic EL display panels are no exception. Here, unlike the liquid crystal display panel in which the color balance is determined by the color filter, the organic EL display panel essentially needs to adjust the color balance as described above. As a result, the number of adjustment parameters increases, so that the circuit / device configuration for adjustment needs to be simplified in order to achieve miniaturization and integration. Moreover, since the adjustment work is complicated and the adjustment time can be increased due to the large number of adjustment parameters, it is also required that the cost of the work be reduced.

  For example, there is a configuration in which a semi-fixed resistor is used for adjustment. However, the semi-fixed resistor is provided as an external component, and its mounting space is relatively large. In this regard, if an electronic volume is used instead of the semi-fixed resistor, the electronic volume is built in the drive circuit (driver) and can be integrated on the panel substrate, which contributes to miniaturization. In addition, by using an electronic volume, it is possible to reduce the cost compared to a configuration using a semi-fixed resistor.

  In the configuration using the electronic volume, it is necessary to store the adjustment value in the memory circuit of the drive circuit in which the electronic volume is built. If an EPROM (Erasable Programmable Read Only Memory) or an EEPROM (Electrically Erasable PROM) is used as this memory circuit, there is a problem that the test cost increases.

  The present invention has been made to solve the above-described problems, and includes a plurality of types of light emitting colors, such as organic EL elements, which emit different amounts of light according to gradation voltages. In addition, in the image display device, it is possible to adjust image quality such as color balance with a configuration that is more compact and easy to integrate and can reduce the cost for adjustment.

  An image display device according to the present invention includes a plurality of light emitting elements including a plurality of types having different emission colors, arranged in correspondence with pixels, and each emitting light with a light amount corresponding to a pixel signal voltage, and a pixel for each of the light emitting elements. A pixel signal voltage generation circuit that generates the pixel signal voltage based on data, and a memory circuit that uses a fuse memory to store a setting value set for each of the emission colors and to be used in the pixel signal voltage generation circuit The pixel signal voltage generation circuit controls generation of the pixel signal voltage for each light emission color based on the set value for each light emission color.

  According to a first preferred aspect of the present invention, the pixel signal voltage generation circuit sets the first gradation reference voltage corresponding to the upper limit value of the pixel data and the lower limit value of the pixel data for each of the emission colors. And a second gradation reference voltage corresponding to the light emission color, which is controlled based on the first set value for the light emission color and changes the first gradation reference voltage. A circuit having an electronic volume and an electronic volume that is controlled based on the second setting value for the emission color and changes the second gradation reference voltage, and a plurality of levels corresponding to possible values of the pixel data For each of the light emitting elements based on the first and second gradation reference voltages corresponding to the emission color of the light emitting element, and The gradation corresponding to the pixel data An image display device for outputting pressure as the pixel signal voltage. In this configuration, for example, the first set value for each light emission color is a white balance adjustment value set by color balance adjustment at the time of displaying image data corresponding to white, and the first set value for each light emission color. The set value of 2 is a black balance adjustment value set by color balance adjustment when displaying image data corresponding to black.

  The first preferred aspect includes a pixel circuit that is provided for each pixel and that causes the light emitting element to emit light with a light amount corresponding to a difference between the pixel signal voltage and a light emission reference voltage that determines a black level, and the light emission reference voltage. A light emission reference voltage generation circuit that is controlled based on a third set value and has an electronic volume for changing the light emission reference voltage, and the memory circuit uses a fuse memory Further, the third set value can be stored for use in the light emission reference voltage generation circuit.

  In the first preferred aspect, the memory circuit stores the set value and sets the electronic volume in a state corresponding to the set value, and the set value stored in the register is stored in the register. And a control circuit that controls an operation of writing to the fuse memory and an operation of reading the setting value stored in the fuse memory to the register.

  In a second preferred embodiment of the present invention, the pixel signal voltage generation circuit linearly converts input image data representing a target color in a predetermined reference color space, which is composed of a set of the pixel data of the respective emission colors. A color compensation circuit for generating compensation image data for reproducing the target color in a display color space displayed by the light emitting element of each of the emission colors, and based on pixel data constituting the compensation image data In the image display device, a pixel signal voltage is generated, and the memory circuit stores each element of a matrix representing the linear transformation as the set value.

  In each of the image display devices according to the present invention, the light emitting element may be an organic light emitting diode.

  In another preferred aspect of the present invention, the memory circuit classifies the plurality of set values into one or a plurality of write groups, and writes the set values to the fuse memory collectively for each write group. For each of the set values belonging to the write group, the fuse memory includes a number of memory cells corresponding to the number of bits of the set value, and the number corresponding to the number of times that the write can be performed for the write group is provided. An image display device comprising: a set value storage block; and a management information storage block including a number of memory cells corresponding to the number of writable times for each of the write groups.

  In this aspect, the memory circuit records management information indicating the number of times of writing for the write group in the management information storage block of each write group, and stores the set value in the fuse memory. When the setting value storage block that has not been written is specified based on the management information, the setting value is written to the setting value storage block, and the setting value is used for setting the state of the electronic volume. The setting value storage block storing the latest setting value is specified based on the management information, and the setting value is read from the setting value storage block.

  According to the present invention, in an image display device including a plurality of types of light emitting colors, such as organic EL elements, each of which emits light with a light amount corresponding to a gradation voltage, the image display apparatus is more compact and integrated. The image quality such as color balance can be adjusted while reducing the cost required for the adjustment.

1 is a schematic diagram showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention. It is a typical circuit diagram which shows the schematic structure of the part mainly formed in a display board | substrate of an organic electroluminescence display. FIG. 3 is a schematic circuit diagram of a pixel circuit arranged in a display unit of the organic EL display panel shown in FIG. 2. FIG. 5 is a schematic timing diagram illustrating the operation of a pixel circuit. It is a schematic circuit diagram which shows the state of the pixel circuit in the main timing of the writing period. It is a schematic circuit diagram which shows the state of the pixel circuit in the main timing of the light emission period. It is a block diagram which shows schematic structure of a drive circuit. It is a schematic circuit diagram of an example of a gradation voltage generation circuit. It is a typical circuit diagram which shows an example of the light emission reference signal generation circuit. It is a typical block diagram which shows an example of a structure of the memory circuit for adjustment. It is a circuit diagram which shows an example of a structure of one memory cell of a fuse memory element. It is a circuit diagram showing typically a memory cell in the state where a fuse element was cut. It is a circuit diagram showing typically a memory cell which maintained a fuse element in an uncut state. It is a schematic diagram which shows an example of bit allocation of a fuse memory element. FIG. 5 is a flowchart for explaining an operation of reading an adjustment value from a fuse memory element. FIG. 10 is a timing chart illustrating an example of an operation for reading an adjustment value from a fuse memory element. It is a flowchart for demonstrating the write operation of the adjustment value to a fuse memory element. FIG. 10 is a timing diagram illustrating an example of an operation of writing an adjustment value of data (* VD) to a fuse memory element. FIG. 10 is a timing chart showing an example of an operation of writing an adjustment value of data (* AMP0) to the fuse memory element. FIG. 10 is a timing diagram illustrating an example of an operation of writing an adjustment value of data (BLAV) to a fuse memory element. It is a schematic diagram which shows the structure of the outline of the color management block provided in the organic electroluminescence display which concerns on the 2nd Embodiment of this invention.

  Hereinafter, an image display apparatus according to an embodiment of the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings. Each embodiment is an active matrix type organic EL display device including an organic EL element as a light emitting element.

[First Embodiment]
FIG. 1 is a schematic diagram illustrating a schematic configuration of an organic EL display device 2 according to the first embodiment. The organic EL display device 2 includes a main circuit 4, a display substrate 6, and a connection substrate 8. The main body circuit 4 includes a signal processing circuit for processing an image signal, a frame memory, and the like, and is formed using a rigid substrate such as a glass epoxy substrate, for example.

  On the display substrate 6, a display unit 10 in which pixel circuits are arranged corresponding to dots (pixels) of a display image is formed. Each pixel circuit includes an organic EL element as a light emitting element, and the display unit 10 is regularly arranged in three types: an organic EL element having an emission color of R, an organic EL element having a G emission color, and an organic EL element having a B emission color. . Each dot is composed of pixel circuits (sub-pixels) corresponding to these different emission colors. For example, for one dot of the display image, three types of pixel circuits 20 corresponding to RGB are arranged adjacent to each other in the horizontal direction. In this case, the display unit 10 includes pixel circuits having the number of horizontal dots × 3 in the horizontal direction and a number of pixel circuits corresponding to the number of vertical dots in the vertical direction. The organic EL element is, for example, an organic light-emitting diode (OLED) in this embodiment. Note that if there is no problem in the following description, the sub-pixel may be simply referred to as a pixel.

  A drive circuit 12 that drives the display unit 10 is also provided on the display substrate 6. The drive circuit 12 is formed by integrating its main part on one or a plurality of semiconductor chips and mounting the chip on the display substrate 6. In addition, as the drive circuit 12, a circuit composed of a TFT using a semiconductor layer made of low-temperature polysilicon can be directly formed on the display substrate 6.

  The connection board 8 connects the main circuit 4 and the display board 6 and inputs display data and display control signals to the drive circuit 12 from, for example, a graphic controller provided on the main circuit 4 side. For example, in FIG. 1, DI means a display data interface (RGB interface) from the main body circuit 4 side to the drive circuit 12, and image data formed by the graphic controller and a data fetch clock are continuously input. System (external data). In this display data interface (DI), the drive circuit 12 sequentially captures image data in accordance with the capture clock in the same manner as a driver used in a conventional personal computer. The connection board 8 can be formed of a flexible wiring board. A part or all of the drive circuit 12 may be disposed on the connection substrate 8.

  FIG. 2 is a schematic circuit diagram showing a schematic configuration of a part of the organic EL display device 2 mainly formed on the display substrate 6 (organic EL display panel). In addition to the display unit 10 in which the pixel circuits 20 are arranged in a matrix, the display substrate 6 is provided with a gate drive circuit 30, a signal line drive circuit 32, and a light emission reference signal generation circuit 34 as the drive circuit 12.

  The gate drive circuit 30 outputs a control signal for each row (line) of the pixel circuit 20 of the display unit 10. Specifically, in the present embodiment, as described later, the pixel circuit 20 includes two switches (lighting switch and reset switch) each made of a TFT, and two lines are provided in each row of the pixel circuits 20. Control signal lines (lighting control line 40 and reset control line 42) are provided, and the gate drive circuit 30 supplies control signals to the control lines 40 and 42 in each row.

  The signal line driving circuit 32 receives data (pixel data) representing an image signal of each pixel (sub-pixel) in the selected row, converts the data into an analog voltage by a D / A converter, and responds to the image signal. It functions as a pixel signal voltage generation circuit that generates the pixel signal voltage. The signal line driver circuit 32 generates the pixel signal voltage for each column of the pixel circuits 20 of the display unit 10. Each column of the pixel circuit 20 is provided with a signal line 44, and the signal line driving circuit 32 outputs the pixel signal voltage of each pixel of the selected row in parallel to the signal line 44 of each column.

  The signal line 44 is provided with switches SWa and SWb. Using these switches SWa and SWb, it is possible to connect the light emission reference signal generation circuit 34 to the signal line 44 instead of the signal line drive circuit 32. Specifically, the signal line drive circuit 32 is connected to the signal line 44 when the switch SWa is in the on state. When the switch SWb is in the on state, the light emission reference signal generation circuit 34 is connected to the signal line 44. These switches SWa and SWb are switched by a control circuit (not shown).

The light emission reference signal generation circuit 34 generates the light emission reference signal V REF of the pixel circuit 20. The output voltage of the light emission reference signal generation circuit 34 is supplied to each pixel circuit 20 via the signal line 44.

Each pixel circuit 20 is supplied with a positive voltage V OLED from the OLED drive voltage source 46 via the power line 48. Each pixel circuit 20 is supplied with a ground potential (GND) through a common ground line.

  The gate driving circuit 30 includes a vertical scanning circuit using a shift register and a logic circuit for each row. The vertical scanning circuit sequentially selects the row of the pixel circuit to be operated in the display unit 10 in the column direction (for example, the direction from the upper side to the lower side of the screen), generates a timing signal for the selected row, Output to row logic. The logic circuit operates based on a timing signal for each row output from the vertical scanning circuit and a timing signal common to each row from the control circuit, and generates a lighting control signal and a reset control signal. Output to the reset control line 42.

  FIG. 3 is a schematic circuit diagram of the pixel circuit 20 arranged in the display unit 10 of the organic EL display panel shown in FIG. Each pixel circuit 20 includes an OLED 90 as a light emitting element. Specifically, the OLED 90 has a structure including at least an anode layer and a cathode layer, and a light emitting layer formed between the anode layer and the cathode layer by an organic material, and holes injected into the light emitting layer. And has the function of generating light by recombination of electrons. As described above, by using different materials for the light emitting layer, three types of OLEDs 90 having different emission colors are formed on the display unit 10. The cathode electrode of the OLED 90 is connected to a common ground line. The anode electrode of the OLED 90 is connected to the power supply line 48 via a lighting switch 92 made of an n-type TFT and a p-type TFT (hereinafter referred to as a drive TFT) 94.

  The gate electrode of the drive TFT 94 is connected to the signal line 44 via the storage capacitor 96, and a reset switch 98 made of an n-type TFT is provided between the drain electrode and the gate electrode of the drive TFT 94. The gate electrode of the reset switch 98 is connected to the reset control line 42. The gate electrode of the lighting switch 92 is connected to the lighting control line 40.

  As described above, each TFT of the pixel circuit 20 is, for example, a polycrystalline silicon thin film transistor that uses polysilicon as a semiconductor layer, and is formed on the display substrate 6.

Next, the pixel circuit operation will be described with reference to FIGS. FIG. 4 is a schematic timing chart for explaining the operation of the pixel circuit 20, and shows waveforms of various signals in one cycle (1 V) of the vertical scanning period. Specifically, FIG. 4 shows a vertical synchronization signal (VSYNC), a control signal Sa for the switch SWa, a control signal Sb for the switch SWb, a lighting control signal S ILM , a reset control signal S RST , and a voltage V D of the power line 48. The voltage V S of the signal line 44 and the gate voltage V G of the driving TFT 94 are shown. Here, the lighting control signal S ILM , the reset control signal S RST, and the gate voltage V G of the driving TFT 94 indicate waveforms relating to the nth row, which is an arbitrary line. A period between rising timings of the VSYNC vertical synchronizing pulse 100 corresponds to 1 V, and display processing for an image of one frame is performed in the period. In the display process for one frame, first, a process of writing the pixel signal voltage to the pixel circuit 20 line by line is performed in the writing period PW, and all lines are simultaneously emitted in the subsequent light emitting period PE.

  FIG. 5 is a schematic circuit diagram showing the state of the pixel circuit 20 at the main timing of the writing period PW, and FIG. 6 is a schematic diagram showing the state of the pixel circuit 20 at the main timing of the light emission period PE. FIG.

The leading period P1 of the writing period PW is a period of the writing operation up to the (n−1) th row. In the period P1, the switch SWa is turned on, and the pixel signal voltage is applied to the signal line 44 in order from the pixels in the first row. For the pixel circuit 20 in the n-th row that is not to be written in this period P1, the gate drive circuit 30 outputs the lighting control signal SILM and the reset control signal SRST to a low level (hereinafter referred to as L level) that is a predetermined low potential. Level). As a result, the lighting switch 92 and the reset switch 98 are kept off, and the gate electrode of the driving TFT 94 maintains the charge accumulation state set in the writing operation of the previous frame. Note that the gate voltage V G of the driving TFT 94 is coupled to the potential of the signal line 44 via the storage capacitor 96, and the influence of the pixel signal voltage V data (x) of another row applied to the signal line 44 is affected. However, the illustration is omitted in FIG.

Periods P2 and P3 are periods of a write operation to the n-th row, and the pixel signal voltage V data (n) of the n-th row is applied from the signal line driving circuit 32 to the signal line 44. In the period P2, the gate drive circuit 30 sets the lighting control signal SILM and the reset control signal SRST to a predetermined high potential High level (hereinafter, H level). As a result, the lighting switch 92 and the reset switch 98 are turned on, and charges accumulated in accordance with the pixel signal voltage of the previous frame on the gate side of the driving TFT 94 are discharged to the ground potential (GND) through the OLED 90. This operation is called a reset operation, and preparations for writing a signal corresponding to the pixel signal voltage V data (n) of the current frame to the storage capacitor 96 are made. At this time, a current flows through the OLED 90 due to the discharge from the gate of the driving TFT 94 and the gate potential V G being lowered to turn on the driving TFT 94. As a result, the OLED 90 emits light in a very small amount compared with the light emission period, and the light emission may cause blackening of the image. However, the pixel circuit 20 can be configured to avoid this.

In the period P3, the lighting control signal SILM is set to the L level, and the lighting switch 92 is turned off. The reset switch 98 is kept on and connects the gate and drain of the driving TFT 94. Driving TFT94 is in the ON state by the gate voltage V G is lower at the beginning of the period P3, it supplies the drain current to the gate. The gate voltage V G is the source voltage, a threshold voltage as high as a driving TFT94 drive TFT94 is turned off. When the gate voltage V G at this time is expressed as V th , a potential difference (V data (n) −V th ) is set between the terminals of the storage capacitor 96.

When the period P3 is completed, the reset control signal S RST is L level, the reset switch 98 is turned off, one terminal of the gate and the storage capacitance 96 of the drive TFT94 becomes a floating state, the storage capacity 96 in the n-th row The potential difference (V data (n) −V th ) corresponding to the pixel signal voltage is stored.

Subsequent to the write operation to the nth row in the periods P2 and P3, the write operation in the (n + 1) th row and thereafter is performed in the period P4. During the period, the lighting switch 92 and the reset switch 98 in the n-th row are maintained in the off state. Note that in this period, as in the period P 1, the gate voltage V G of the driving TFT 94 is coupled to the potential of the signal line 44 through the storage capacitor 96 and is applied to the signal line 44. Although it fluctuates under the influence of data (x), it is not shown in FIG.

When the light emission period PE is entered, the switch SWa is turned off. In the leading period P5 of the light emission period PE, the switch SWb is turned on, and the light emission reference signal V REF is supplied from the light emission reference signal generation circuit 34 to the signal line 44. The voltage V REF is applied in common to one terminal of the storage capacitor 96 of each pixel circuit 20 of the display unit 10. Since the reset switch 98 of each pixel circuit 20 is off and the other terminal of the storage capacitor 96 is in a floating state, the potential of the other terminal shifts according to V REF applied to one terminal. For example, the potential of the other terminal of the storage capacitor 96 in the n-th row storing the potential difference (V data (n) −V th ) is changed from the potential V th at the time when the potential difference is set to the potential (V REF −V data (n) + V th ). Thereafter, the switch SWb is turned off in the period P 6, whereby the potential of the other terminal of the storage capacitor 96 is maintained at (V REF −V data (n) + V th ), and this potential is applied to the gate electrode of the driving TFT 94. Is done.

In a state where the gate voltage V G of the thus drive TFT94 is set to the potential (V REF -V data (n) + V th), the lighting switch 92 is turned on (period P7), the drive TFT94, the gate - A drain current corresponding to the source-to-source voltage flows. The drain current is supplied to the OLED 90, and the OLED 90 emits light according to the amount of current.

Here, it is understood that V REF determines the threshold value of the pixel signal voltage V data emitted from the OLED 90. That is, if V data (n) ≧ V REF , the driving TFT 94 is turned on and the OLED 90 emits light, but if V data (n) <V REF , the driving TFT 94 is not turned on and the OLED 90 does not emit light.

  FIG. 7 is a block diagram showing a schematic configuration of the drive circuit 12. The drive circuit 12 includes the gate drive circuit 30 (not shown in FIG. 7), the light emission reference signal generation circuit 34, the image data interface circuit 200, the D / A conversion circuit 202, and the serial interface circuit 204 for the control register circuit. An adjustment memory circuit 206, a control register circuit 208, a gradation voltage generation circuit 210, and a pixel signal voltage output circuit 212. The signal line drive circuit 32 described above includes the gradation voltage generation circuit 210, the image data interface circuit 200, the D / A conversion circuit 202, and the pixel signal voltage output circuit 212 shown in FIG.

  In the present embodiment, display data (Data) input from the display data interface (DI) is composed of 6 bits for each color of R, G, and B, and the gradation voltage generation circuit 210 corresponds to this. A gradation voltage of 64 gradations is generated.

  The shift register circuit in the image data interface circuit 200 generates a capture pulse synchronized with the dot clock (DCLK) based on the dot clock (DCLK) input from the outside. The latch circuit of the image data interface circuit 200 captures display data input from the outside based on the capture pulse output from the shift register circuit.

  The D / A conversion circuit 202 selects a gradation voltage corresponding to display data stored in the latch circuit of the image data interface circuit 200 from among the gradation voltages of 64 gradations generated by the gradation voltage generation circuit 210. Select and output.

  The pixel signal voltage output circuit 212 outputs the gradation voltage output from the D / A conversion circuit 202 to the corresponding signal line 44 as a pixel signal voltage.

The light emission reference signal generation circuit 34 generates a light emission reference signal VREF .

  The operation of each part of the drive circuit 12 described above is executed under the instruction and control of the control register circuit 208. In the control, the control register circuit 208 writes the adjustment value to the adjustment memory circuit 206 or reads the adjustment value from the adjustment memory circuit 206 to obtain the gradation voltage generation circuit 210 and the light emission reference signal generation circuit 34. Including the operation of adjusting.

  FIG. 8 is a schematic circuit diagram of an example of the gradation voltage generation circuit 210. The gradation voltage generation circuit 210 generates gradation voltages of 64 gradations for each of R, G, and B. FIG. 8 shows a circuit for R of RGB. The grayscale voltage generation circuit 210 shown in FIG. 8 generates 64 levels of voltages V0 to V63 by dividing resistance between a reference voltage source (VDH) having a predetermined positive voltage and the ground potential (GND). The ladder resistor that performs resistance division has a three-stage configuration, and the voltage is divided stepwise in the order of the primary ladder resistor 220, the secondary ladder resistor 222, and the tertiary ladder resistor 224. The ladder resistor circuit is configured to include an electronic volume, and by changing the resistance value of the electronic volume in accordance with data (RVD, RAMP0 to RAMP14) set in the register, 64 levels are obtained so as to obtain a desired gradation characteristic. Can be adjusted. For example, the electronic volume 230 constituting the resistance of the primary ladder resistor 220 closest to the positive power supply (VDH) is controlled to have a resistance value corresponding to the data (RVD) stored in the register 232. In addition, the electronic volume 234 that constitutes the resistance of the secondary ladder resistor 222 closest to the ground potential (GND) is controlled to a resistance value corresponding to the data RAMP 0 stored in the register 236. The output voltage of the electronic volume 230 defines the upper limit of the voltage range in which the gradation voltage can be set, and the output voltage of the electronic volume 234 defines the lower limit of the range. That is, the data (RVD) is a parameter for adjusting the highest gradation voltage V0 of the emission color R, and the data (RAMP0) is a parameter for adjusting the lowest gradation voltage V63. The gradation voltage generation circuit 210 is configured similarly to the emission color R for the other emission colors G and B, and the maximum gradation voltage V0 for the emission colors G and B is adjusted by data (GVD and BVD), respectively. The gradation voltage V63 is adjusted by data (GAMP0, BAMP0), respectively.

  Here, color balance adjustment at the time of displaying image data corresponding to white, that is, white balance adjustment, is performed by operating the maximum gradation voltage V0 of each color. Further, the color balance adjustment when displaying the image data corresponding to black, that is, the black balance adjustment is performed by operating the maximum gradation voltage V63 of each color. Data (RVD, GVD, BVD) are adjustment parameters for white balance, and data (RAMP0, GAMP0, BAMP0) are adjustment parameters for black balance. Hereinafter, in order to simplify the notation, the symbol “* VD” is used when RVD, GVD, and BVD are comprehensively expressed, and the symbol “* AMP0” is used when RAMP0, GAMP0, and BAMP0 are comprehensively expressed. Is used.

FIG. 9 is a schematic circuit diagram illustrating an example of the light emission reference signal generation circuit 34. The light emission reference signal generation circuit 34 generates a light emission reference signal V REF by resistance-dividing the power source (VDH) and the ground potential (GND). The generated light emission reference signal V REF is output via the buffer circuit 254. The resistance dividing circuit 250 has an electronic volume 252. The electronic volume 252 is controlled to have a resistance value corresponding to data (BLAV) stored in the register 256. As described above, V REF determines the threshold value of the pixel signal voltage V data emitted from the OLED 90 and defines the black level. By operating this VREF , the contrast of the image displayed on the organic EL display device 2 can be adjusted.

  The organic EL display device 2 of the present embodiment can adjust the data (* VD, * AMP0, BLAV) after the assembly of the organic EL display device 2, and the adjustment result is stored in the adjustment memory circuit 206. For example, in a process after the assembly of the organic EL display device 2, a test image is displayed to measure white balance, black balance, and contrast, and data (* VD, * AMP0, BLAV) is used so that they are suitable. adjust. Then, the adjustment value is written and stored in the storage element in the adjustment memory circuit 206. When the organic EL display device 2 is activated, the control register circuit 208 reads out these adjustment values from the storage element and sets them in the registers 232, 236, and 256 for use by the gradation voltage generation circuit 210 and the light emission reference signal generation circuit 34. . Thereby, the organic EL display device 2 is set to a state in which a suitable image quality can be obtained.

  As a storage element for storing the data, the adjustment memory circuit 206 includes a fuse memory element that is an OTP (One-Time-Program) -ROM.

  FIG. 10 is a schematic block diagram illustrating an example of the configuration of the adjustment memory circuit 206. FIG. 10 shows a fuse memory element 300, a control circuit 302, an adjustment value register group 304, and a bank control register group 306.

  The fuse memory element 300 is an aggregate of memory cells capable of storing 1-bit information. In this embodiment, RVD, GVD, and BVD are 6-bit binary data, and a block (set value storage block) including 18 memory cells is provided to store one set of * VD. RAMP0, GAMP0, and BAMP0 are each 3-bit binary data, and a block of nine memory cells is provided to store one set of * AMP0. BLAV is 7-bit binary data, and a block composed of 7 memory cells is provided.

  Here, each cell of the fuse memory cannot be rewritten. Therefore, in order to allow each adjustment value to be rewritten and updated, the fuse memory element 300 is provided with a plurality of blocks for each adjustment value. The adjustment memory circuit 206 sets * VD, * AMP0, and BLAV as write groups, and writes the set values to the fuse memory in a lump for each write group. Here, the memory cell group corresponding to the write group is referred to as a bank. The fuse memory element 300 is also provided with a memory cell block (management information storage block) for storing management information indicating the number of times of writing. By referring to this management information, it is possible to grasp in which bank the latest value is written. In this embodiment, three banks are provided for each of * VD, * AMP0, and BLAV. Then, 3-bit management information is used to identify the three banks for * VD, and a block of three memory cells is prepared to store the management information. * Similarly, a block composed of three memory cells is prepared for AMP0 and BLAV.

  Since the adjustment value and management information described above are 111 bits in total, the capacity of the fuse memory element 300 may be 128 bits. In this case, each memory cell can be identified by a 7-bit address A [6: 0].

  The adjustment value register group 304 includes a white balance adjustment value register 320, a black balance adjustment value register 322, and a contrast adjustment value register 324. The white balance adjustment value register 320 is a register for storing one set of * VD. The black balance adjustment value register 322 is a register for storing one set of * AMP0. The contrast adjustment value register 324 is a register for storing BLAV. The adjustment value stored in the adjustment value register group 304 is used to control the electronic volume of the gradation voltage generation circuit 210 and the light emission reference signal generation circuit 34 described above.

  The bank control register group 306 includes a white balance bank control register 330, a black balance bank control register 332, and a contrast adjustment value bank control register 334. The white balance bank control register 330 is a register for storing the management information for * VD. The black balance bank control register 332 is a register for storing management information about * AMP0. The contrast adjustment value bank control register 334 is a register for storing management information about the BLAV. In the adjustment work after the assembly of the organic EL display device 2, image quality adjustment is performed by operating the adjustment values set in the adjustment value register group 304. A suitable adjustment value obtained by this adjustment operation is written from the adjustment value register group 304 to the fuse memory element 300. At that time, based on the management information stored in the bank control register group 306, an unused bank is selected, and an adjustment value is written to the bank.

  FIG. 11 is a circuit diagram showing an example of the configuration of one memory cell 350 of the fuse memory element 300. The memory cell 350 includes a level shift circuit (RES) for level-shifting a write signal (PROGRAM), a fuse element (FUSE) made of polysilicon, and an on (blown) / off (non-blown) fuse element (FUSE). ) For controlling the NMOS transistor (NMS), the level sense circuit (RSC) for detecting the state of the fuse element (FUSE), the inverter (INB) inserted into the output of the level sense circuit (RSC), and the read signal ( It is turned on by (READ) and is composed of a transfer gate circuit (TFG) for reading out the output of the level sense circuit (RSC) and a latch circuit (RCH).

  At the time of programming (writing), each memory cell 350 of the fuse memory element 300 is supplied with a power supply voltage (VFS) for fusing fuse elements, a power supply voltage (VPP) for controlling fuse element on / off, and a logic power supply voltage (VDD). ) Is applied. Then, each memory cell 350 of the fuse memory element 300 is sequentially selected one address at a time by the address signal (A [6: 0]) and programmed. For a memory cell that programs an H level representing a logical value “1”, the write signal (PROGRAM) is set to the H level, the NMOS transistor (NMS) is turned on, and a current flows through the fuse element (FUSE). Fusing (FUSE). FIG. 12 is a circuit diagram schematically showing the memory cell 350 in a state where the fuse element is cut. On the other hand, the fuse element (FUSE) is not blown by setting the write signal (PROGRAM) to the L level for the memory cell that programs the L level representing the logical value “0”. FIG. 13 is a circuit diagram schematically showing a memory cell 350 in which this fuse element is maintained in an uncut state.

  When reading a programmed value from the memory cell 350, an H level is applied to the read signal (READ) to turn on the transfer gate circuit (TFG). In the memory cell 350 in the state of FIG. 12, since the drain of the NMOS transistor (NMS) is in a floating state, the level sense circuit (RSC) detects the floating state and outputs an H level (= VDD). This H level potential is inverted by the inverter (INB) and further inverted by the latch circuit (RCH), so that the output (DOUT) becomes the H level (= VDD). That is, the logical value “1” is read from the memory cell 350 in FIG.

  On the other hand, the drain of the memory cell 350 and the NMOS transistor (NMS) in the state of FIG. 13 is pulled down to the ground potential (GND) via the fuse element (FUSE) and the resistance element (Pull-Down resistance), so that level sensing is performed. The circuit (RSC) detects the ground potential (GND) and outputs an L level (= GND). The L level potential is inverted by the inverter (INB) and further inverted by the latch circuit (RCH), so that the output (DOUT) becomes the L level (= GND). That is, a logical value “0” is read from the memory cell 350 in FIG.

  In this manner, digital data represented by binary values “1” and “0” is programmed in the fuse memory element 300, and the program state can be output as a digital signal (DOUT [127: 0]). .

  FIG. 14 is a schematic diagram illustrating an example of bit allocation of the fuse memory element 300. For example, the area from the 0th bit to the 110th bit among 128 bits is allocated to the adjustment value and the management information. As a management information storage block for storing management information, a memory cell of [8: 0] bits (representing addresses from the 0th bit to the 8th bit, the same notation is used hereinafter) is used. The remaining [110: 9] bit memory cells are used as adjustment value storage blocks (setting value storage blocks) for storing the adjustment values of the electronic volume.

  The adjustment memory circuit 206 sets * VD, * AMP0, and BLAV as write groups, and writes the set values to the fuse memory in a lump for each write group. Correspondingly, one management information storage block is provided for each of the three write groups. Bank1 consisting of [2: 0] bits shown in FIG. 14 is a management information storage block for storing management information (BLFB [2: 0]) for BLAV, and Bank2 consisting of [5: 3] bits is * This is a management information storage block for storing management information (WFB [2: 0]) for the VD. Bank3 consisting of [8: 6] bits stores management information (BFB [2: 0]) for * AMP0. This is a management information storage block.

  As a bank for BLAV, [15: 9] bits are assigned for initial value setting, [22:16] bits for first rewriting, and [29:23] bits for second rewriting. * As a bank for VD, [47:30] bits for initial value setting, [65:48] bits for first rewriting, and [83:66] bits for second rewriting are allocated. * As a bank for AMP0, [92:84] bits are assigned for initial value setting, [101: 93] bits for first rewriting, and [110: 102] bits for second rewriting.

  Next, the adjustment value reading operation from the fuse memory element 300 will be described. FIG. 15 is a flowchart for explaining the read operation of the adjustment value from the fuse memory element 300. First, when the power is turned on (step 400) and the sequence bit is turned on (step 402), the control circuit 302 generates a read signal (READ) (step 404). Then, the data (DOUT [127: 0]) stored in each memory cell of the fuse memory element 300 is read from the fuse memory element 300 (step 406).

  Based on the management information of [8: 0] bits in the read data (DOUT [127: 0]), the control circuit 302 selects an adjustment value storage block in which the latest adjustment value is stored (step 408). ). The adjustment value is read from the adjustment value storage block selected in the previous step and stored in the corresponding registers 320, 322, and 324 in the adjustment value register group 304 (step 410).

After that, the gradation voltage generation circuit 210 adjusts the electronic volumes 230 and 234 based on the adjustment values * VD and * AMP0 stored in the white balance adjustment value register 320 and the black balance adjustment value register 322 to obtain the 64 gradation levels. Generate a regulated voltage. The light emission reference signal generation circuit 34 adjusts the electronic volume 252 based on the adjustment value BLAV stored in the contrast adjustment value register 324 to generate V REF . A display operation is performed using the adjusted gradation voltage and V REF (step 412).

  FIG. 16 is a timing chart showing an example of the adjustment value read operation from the fuse memory element 300. In FIG. 16, VSYNC is a vertical synchronization signal, and HSYNC is a horizontal synchronization signal. Based on the signal (HSYNC1_P) synchronized with the horizontal synchronization signal (HSYNC), the control circuit 302 enables the enable signal (ENB_N) for the period T1. Next, the control circuit 302 outputs a read signal (READ_P) to the fuse memory element 300 and reads data (DOUT [127: 0]) from the fuse memory element 300.

  Next, the control circuit 302 outputs a register clock (FADCK_P) to the bank control register group 306. The white balance bank control register 330, the black balance bank control register 332, and the contrast adjustment value bank control register 334 operate in synchronization with the register clock (FADCK_P) and read data (DOUT [127: 0]). [8: 0] bits of management information (WFB [2: 0], BFB [2: 0], BLFB [2: 0]) are stored. In FIG. 10, the management information (WFB [2: 0], BFB [2: 0], BLFB [2: 0]) is collectively expressed as “D_BANK”. The management information is passed to the control circuit 302.

  Based on the management information, the control circuit 302 selects the adjustment value storage block in which the latest adjustment value is stored, and receives the address information (IN_ADJ_P) of the selected adjustment value storage block and the register clock (IN_SREG2_P). Output to the adjustment value register group 304.

  The white balance adjustment value register 320, the black balance adjustment value register 322, and the contrast adjustment value register 324 operate in synchronization with the register clock (IN_SREG2_P), and read and store the designated adjustment value storage block. Each of the registers 320, 322, and 324 outputs the stored adjustment values (R / G / BVD [5: 0], R / G / BAMP0 [2: 0], BLAV [6: 0]) to the electronic volume. In FIG. 10, these adjustment values are collectively represented as “D_ADJ”.

  Next, the adjustment value writing operation to the fuse memory element 300 will be described. FIG. 17 is a flowchart for explaining the adjustment value writing operation to the fuse memory element 300.

  First, an image is displayed on the organic EL display device 2 (step 500), and the electronic volume 230, 232, 252 is adjusted by increasing or decreasing the adjustment value set in the register while visually recognizing the displayed image. Adjust contrast, white balance, and black balance. As a result of adjustment, the adjustment value register group 304 stores adjustment values in a state where desired image quality is obtained (step 502).

  The control circuit 302 generates a read signal (READ) (step 504), and reads data (DOUT [127: 0]) from the fuse memory element 300 (step 506).

  Based on the management information of [8: 0] bits in the read data (DOUT [127: 0]), the control circuit 302 selects an adjustment value storage block for writing a new adjustment value, and An initial address value is set (step 508). The address of the selected adjustment value storage block is sequentially designated, and the adjustment value stored in the adjustment value register group 304 is written to the fuse memory element 300 (step 510), and the adjustment value is written to the fuse memory element 300. The operation is terminated (step 512).

  Note that, as a procedure for reflecting the new adjustment value in the light emission reference signal generation circuit 34 and the gradation voltage generation circuit 210, one is already in the adjustment value register group 304 as shown in step 514 in FIG. A method of performing immediately using the stored adjustment value is possible. In another method, the latest adjustment value written in the fuse memory element 300 is loaded in a re-on sequence, and then reflected in the light emission reference signal generation circuit 34 and the gradation voltage generation circuit 210 to display with a new image quality. It is also possible to perform an operation (step 516).

  18 to 20 are timing charts showing an example of the adjustment value write operation to the fuse memory element 300. FIG. 18 is a * VD write operation, FIG. 19 is a * AMP0 write operation, and FIG. A write operation is shown.

  The control circuit 302 outputs a register clock (FADCK_P) to the bank control register group 306. The white balance bank control register 330, the black balance bank control register 332, and the contrast adjustment value bank control register 334 operate in synchronization with the register clock (FADCK_P), and store management information (WFB [2: 0], BFB [2: 0], BLFB [2: 0]) are output to the control circuit 302.

  Based on the management information obtained from the bank control register group 306, the control circuit 302 sets an initial address (A [6: 0]) of an adjustment value storage block for storing a new adjustment value.

  The control circuit 302 enables the enable signal (ENB_N) in the period T2 in synchronization with the vertical synchronization signal (VSYNC). Further, a memory cell to be programmed one address at a time is designated by an address signal (A [6: 0]) within one vertical scanning period, and a new value set in the adjustment value register group 304 is set based on a write signal (PROGRAM). A correct adjustment value is written in the fuse memory element 300.

  Specifically, in the * VD writing shown in FIG. 18, the adjustment value stored in the white balance bank control register 330 is an adjustment value for which an address is specified based on the management information (WFB [2: 0]). Written to storage block. In this write operation, the control circuit 302 counts down the count value (FFCNT) by one from the initial value 20 in synchronization with the signal (HSYNC1_P). Based on the management information (WFB [2: 0]) obtained at FFCNT = 20, the start address (n) of the adjustment value storage block to be written at FFCNT = 19 is designated. Thereafter, in conjunction with the countdown of FFCNT. The address is also counted down. The memory cells at the addresses specified in this way are sequentially set as write targets. The memory cell at address (n to n-5) has RVD, the memory cell at address (n-6 to n-11) has GVD, and the memory cell at address (n-12 to n-17) has BVD. Written. When FFCNT = 1, the fuse element (FUSE) of the memory cell (address α) corresponding to the bit indicating the bank written this time in the 3-bit management information (WFB [2: 0]) is blown.

  The write signal (PROGRAM) generates an H level pulse for the bit that blows the fuse element (FUSE), while maintaining the L level for the bit that does not blow. In FIG. 18, a broken line portion of the write signal (PROGRAM) corresponds to a bit that does not blow, and represents that the write signal (PROGRAM) is maintained at the L level in the portion.

  Similarly, in the writing of * AMP0 shown in FIG. 19, the adjustment value stored in the black balance bank control register 332 is used to store the adjustment value whose address is specified based on the management information (BFB [2: 0]). Written to the block. In this case, FFCNT is counted down from 11, the start address (n) of the adjustment value storage block to be written at FFCNT = 10 is designated, and the memory cell at address (n to n-2) has RAMP0, address ( GAMP0 is written into the memory cells n-3 to n-5), and BAMP0 is written into the memory cells with addresses (n-6 to n-8). When FFCNT = 1, the fuse element (FUSE) of the memory cell (address α) corresponding to the bit indicating the bank written this time in the management information (BFB [2: 0]) is blown.

  In the BLAV writing shown in FIG. 20, the adjustment value stored in the contrast adjustment value bank control register 334 is written into the adjustment value storage block whose address is specified based on the management information (BLFB [2: 0]). It is. In this case, FFCNT is counted down from 9, the start address (n) of the adjustment value storage block to be written at FFCNT = 8 is designated, and BLAV is written into the memory cell at address (n to n-6). When FFCNT = 1, the fuse element (FUSE) of the memory cell (address α) corresponding to the bit indicating the bank written this time in the management information (BLFB [2: 0]) is blown.

The adjustment using the fuse memory element described above for white balance, contrast, etc. can also be applied to adjustment of other parameters in the organic EL display device 2. For example, the regulation of the light emission period, the EL element driving voltage (V OLED ), and the like can be adjusted after the assembly of the organic EL display device 2, and the adjusted value can be stored in the fuse memory element.

  Further, the number of times that writing can be performed is not limited to three. For example, a larger number of times of writing may be possible. In addition, a situation that may affect the image quality of the organic EL display device 2 such as a use environment (for example, temperature) of the organic EL display device 2 is assumed in advance, and adjustment for each of the assumed plurality of situations is performed. 2 may be performed after assembly and stored in the fuse memory element. Since a plurality of parameters are related to the color balance adjustment, the adjustment is not easy. However, if a suitable adjustment value corresponding to the situation is stored in advance in the fuse memory element for each product, the user can easily reproduce the adjustment state corresponding to the situation simply by switching the bank value.

  A fuse memory element which is an OTP memory can operate at a lower voltage than an MTP (Muli-Time-Programming) memory. Since a large voltage is not used, a circuit structure with a low breakdown voltage can be obtained, so that a merit of reducing the layout area of the drive circuit can be expected. Regarding the inspection cost, the MTP memory requires steps such as baking and UV irradiation for inspection of rewrite accuracy, but the OTP memory does not require these steps.

[Second Embodiment]
Hereinafter, components having the same functions as those in the first embodiment are indicated by the same reference numerals as those in the first embodiment, and the components are basically the same as those in the first embodiment. Use the explanation.

  The organic EL display 2 according to the second embodiment is basically a color management function mounted on the organic EL display 2 of the first embodiment. For example, in a digital still camera display, a display for DTP (Desktop Publishing), and the like, there is an increasing demand for high color purity such as compatibility with the Adobe RGB standard in terms of color reproducibility. In this respect, since the organic EL display has a wide color gamut compared to the liquid crystal display, it is possible to achieve high color purity. On the other hand, as described above, the color of the organic EL display may cause a difference in luminance between RGB pixels due to the characteristic difference of the organic EL material. In addition, individual differences between displays due to manufacturing variations or the like may occur. Also, the same display can change over time. Therefore, the organic EL display 2 of the present embodiment has a color management function in order to fully utilize the characteristics of high color purity, and makes it possible to match the color reproduction range with the Adobe RGB standard or the sRGB standard.

  FIG. 21 is a schematic diagram showing a schematic configuration of a color management block 600 provided in the organic EL display 2 according to the present embodiment. The color management block 600 is provided in the drive circuit 12 and can constitute a part of the pixel signal voltage generation circuit. The color management block 600 may be provided in a portion other than the drive circuit 12, for example, in the main body circuit 4.

  For example, the color management block 600 performs conversion from a color space (reference color space) such as the Adobe RGB standard or the sRGB standard into a display color space displayed by the OLED 90 for each color of RGB. At this time, the color management block 600 performs color compensation. Specifically, the color management block 600 performs linear conversion on display data (input image data) input to the image data interface circuit 200 to generate new display data (compensation image data). At that time, the color management block 600 basically keeps the colors represented by the image data before and after the conversion.

The input image data corresponding to each pixel is composed of a set of pixel data (R in , G in , B in ) corresponding to sub-pixels of each color of R, G, B. Similarly, the compensation image data is composed of a set of pixel data (R out , G out , B out ) corresponding to the sub-pixels of R, G, and B colors. The color management block 600 includes a multiplication circuit 602 and an addition circuit 604, and in principle performs linear conversion represented by the following equation.
R out = A 11 · R in + A 12 · G in + A 13 · B in
G out = A 21 · R in + A 22 · G in + A 23 · B in ··· (1)
B out = A 31 · R in + A 32 · G in + A 33 · B in

A ij on the right side of Equation (1) is a coefficient of linear transformation. The coefficient A ij is a correction coefficient that realizes a color compensation function. The correction coefficient A ij is obtained by converting the compensation image data obtained by the conversion into a color (target color) in the reference color space represented by the input image data. The same color is determined to be reproduced in the display color space.

Each correction coefficient A ij is written in the fuse memory element in the same manner as the various adjustment values in the first embodiment. In this embodiment, the capacity of the fuse memory element 300 of the adjustment memory circuit 206 is increased from that of the first embodiment, and each correction coefficient is stored in the fuse memory element 300.

The fuse memory element 300 stores correction coefficients A 11 , A 12 , A 13 as set values for R, stores correction coefficients A 21 , A 22 , A 23 as set values for G, and corrects as set values for B Coefficients A 31 , A 32 and A 33 are stored. The adjustment memory circuit 206 supplies these correction coefficients to the linear conversion process in the color management block 600. The configuration and procedure for writing these correction coefficients to the fuse memory element and reading from the fuse memory element are the same as those in the first embodiment. For example, the adjustment memory circuit 206 is provided with a correction coefficient register group 608 including registers 606 for each correction coefficient. The correction coefficient used for use in the color management block 600 is read from the fuse memory element 300 and stored in the register 606. The color management block 600 reads the correction coefficient stored in the register 606 and performs the above-described color space conversion processing. Use.

  In addition, a plurality of banks can be provided in the fuse memory element 300 in the same manner as in the first embodiment, assuming rewriting / updating due to a change in correction coefficient over time. In this case, similarly to the first embodiment, a memory cell for storing management information for storing management information indicating the number of times of writing has been provided, and a bank register is provided.

The expression (1) is linearly converted when the input image data (R in , G in , B in ) is the column vector P in , and the compensation image data (R out , G out , B out ) is the column vector P out. Can be expressed as follows using a matrix [A] having the coefficients A ij of i as elements of the i-th row and j-th column.
P out = [A] · P in (2)

  The matrix [A] is determined for each reference color space. Therefore, in the configuration in which the color management block 600 corresponds to the Adobe RGB standard and the sRGB standard, the fuse memory element 300 stores the matrix [A] corresponding to the Adobe RGB standard and the matrix [A] corresponding to the sRGB standard, respectively. An area is provided.

In general, the correction coefficient A ij is a real number having a decimal part, and the correction coefficient that is a diagonal element of the matrix [A] is basically positive and has an absolute value larger than that of a non-diagonal element. For example, the correction factor of the diagonal element is a value relatively close to 1. On the other hand, the absolute value of the correction coefficient of the non-diagonal element is relatively close to 0, and may be positive or negative.

In order to simplify the configuration of the multiplication circuit 602, the addition circuit 604, and the adjustment memory circuit 206 of the color management block 600, the adjustment memory circuit 206 is preferably configured to store the correction coefficient A ij converted to an integer. For example, the original correction coefficient expressed in decimal is multiplied by κ, and the integer part is stored in the adjustment memory circuit 206. In this case, the color management block 600 is configured to divide the output value of the adder circuit 604 by κ.

Here, as an example, a configuration in which κ is set to 64 (= 2 6 ) will be specifically described. Since the original value of the diagonal element is a positive number of about 1, each diagonal element converted to an integer can basically be represented by unsigned 7-bit binary data, considering the width of the adjustment range. But 7 bits would be sufficient. An integerized off-diagonal element basically needs to prepare a sign bit, but since the absolute value is small, it can be expressed with a smaller number of bits than the diagonal element. In this way, the number of bits necessary to store nine correction coefficients is estimated taking into account the range in which these correction coefficients can be adjusted, and the memory cell having the number of bits is used as the fuse memory element of the adjustment memory circuit 206. prepare.

  The division by 64 in the subsequent stage of the addition circuit 604 can be realized by a 6-bit right shift operation.

Compensated image data (R out , G out , B out ) obtained by color space conversion processing in the color management block 600 is input to the D / A conversion circuit 202. The subsequent steps are the same as in the first embodiment, and the D / A conversion circuit 202 selects the gradation voltage corresponding to the input compensation image data, and the selected gradation voltage is used as the pixel signal voltage. The signal is supplied from the output circuit 212 to the corresponding pixel circuit 20 through the signal line 44.

  As mentioned above, although this invention was concretely demonstrated based on embodiment, this invention is not limited to the said embodiment. That is, even in an image display device other than the above-described embodiment, a plurality of light emitting elements including a plurality of types having different emission colors, arranged in correspondence with pixels, and each emitting light with a light amount corresponding to a pixel signal voltage; The present invention can be applied to a device having a pixel signal voltage generation circuit that generates the pixel signal voltage based on pixel data for each light emitting element. The gist of the present invention is that an image display device is provided with a memory circuit that stores a set value set for each of the emission colors using a fuse memory and is used for the pixel signal voltage generation circuit. A generation circuit is present in that the generation of the pixel signal voltage is controlled for each light emission color based on the set value for each light emission color. The present invention can be variously modified without departing from the gist of the invention.

  The image display device and the driving method thereof according to the present invention can be used for, for example, an active matrix type organic EL display, and as a result, for a TV, a car navigation system, a PC monitor, a notebook PC, a mobile phone, a DSC, a PDA, and the like. Can be used.

  2 organic EL display device, 4 body circuit, 6 display substrate, 8 connection substrate, 10 display unit, 12 drive circuit, 20 pixel circuit, 30 gate drive circuit, 32 signal line drive circuit, 34 light emission reference signal generation circuit, 40 lighting Control line, 42 reset control line, 44 signal line, 46 OLED drive voltage source, 48 power supply line, 60 vertical scanning circuit, 62 logic circuit, 70, 72, 74, 76 timing signal line, 90 OLED, 92 lighting switch, 94 Drive TFT, 96 memory capacity, 98 reset switch, 200 image data interface circuit, 202 D / A conversion circuit, 204 serial interface circuit, 206 adjustment memory circuit, 208 control register circuit, 210 gradation voltage generation circuit, 212 pixel signal Voltage output circuit, 220 Primary ladder resistor , 222 Secondary ladder resistance, 224 Tertiary ladder resistance, 230, 234, 252 Electronic volume, 232, 236 register, 250 Resistance dividing circuit, 300 Fuse memory element, 302 Control circuit, 304 Adjustment value register group, 306 Bank control register Group, 320 white balance adjustment value register, 322 black balance adjustment value register, 324 contrast adjustment value register, 330 white balance bank control register, 332 black balance bank control register, 334 contrast adjustment value bank control register, 350 memory cells , 600 color management block, 602 multiplication circuit, 604 addition circuit, 606 register, 608 correction coefficient register group.

Claims (9)

  1. A plurality of light emitting elements that include a plurality of types having different emission colors, are arranged corresponding to the pixels, and each emits light with a light amount corresponding to the pixel signal voltage;
    A pixel signal voltage generation circuit that generates the pixel signal voltage based on pixel data for each of the light emitting elements;
    A memory circuit that stores a set value set for each of the emission colors using a fuse memory and is used for the pixel signal voltage generation circuit;
    Have
    The pixel signal voltage generation circuit controls generation of the pixel signal voltage for each emission color based on the set value for each emission color;
    An image display device characterized by the above.
  2. The image display device according to claim 1,
    The pixel signal voltage generation circuit includes:
    A circuit for generating a first gradation reference voltage corresponding to an upper limit value of the pixel data and a second gradation reference voltage corresponding to a lower limit value of the pixel data for each of the emission colors, For each color, the electronic volume is controlled based on the first setting value for the emission color and changes the first gradation reference voltage, and is controlled based on the second setting value for the emission color. A circuit having an electronic volume for changing the second gradation reference voltage;
    A circuit that generates a plurality of levels of gradation voltages corresponding to possible values of the pixel data for each emission color based on the first and second gradation reference voltages corresponding to the emission color of the light emitting element. When,
    And outputting the gradation voltage corresponding to the pixel data for each of the light emitting elements as the pixel signal voltage.
  3. The image display device according to claim 2,
    The first setting value for each light emission color is a white balance adjustment value set by color balance adjustment when displaying image data corresponding to white,
    The second setting value for each of the emission colors is a black balance adjustment value set by color balance adjustment when displaying image data corresponding to black;
    An image display device characterized by the above.
  4. The image display device according to claim 2,
    A pixel circuit that is provided for each pixel and emits the light emitting element with a light amount corresponding to a difference between the pixel signal voltage and a light emission reference voltage that defines a black level;
    A circuit for generating the light emission reference voltage, the light emission reference voltage generation circuit having an electronic volume controlled based on a third set value and changing the light emission reference voltage;
    Have
    The memory circuit uses a fuse memory to further store the third set value for use in the light emission reference voltage generation circuit;
    An image display device characterized by the above.
  5. The image display device according to claim 2,
    The memory circuit includes:
    A register for storing the set value and setting the electronic volume in a state corresponding to the set value;
    A control circuit that controls an operation of writing the setting value stored in the register to the fuse memory, and an operation of reading the setting value stored in the fuse memory to the register;
    An image display device comprising:
  6. The image display device according to claim 1,
    The pixel signal voltage generation circuit includes:
    The input image data comprising a set of the pixel data of each light emission color and representing the target color in a predetermined reference color space is linearly converted, and the display color space displayed by the light emitting element of each light emission color A color compensation circuit for generating compensated image data for reproducing a target color, and generating the pixel signal voltage based on pixel data constituting the compensated image data;
    The memory circuit stores each element of a matrix representing the linear transformation as the set value;
    An image display device characterized by the above.
  7. The image display device according to any one of claims 1 to 6,
    The image display device, wherein the light emitting element is an organic light emitting diode.
  8. The image display device according to any one of claims 1 to 6,
    The memory circuit classifies the plurality of set values into one or a plurality of write groups, and writes the set values to the fuse memory collectively for each write group,
    The fuse memory is
    For each of the set values belonging to the write group, the set value storage unit includes a number of memory cells corresponding to the number of bits of the set value, and is provided in a number corresponding to a predetermined number of writable times for the write group. Block,
    For each of the write groups, a management information storage block including a number of memory cells corresponding to the number of writable times,
    An image display device comprising:
  9. The image display device according to claim 8,
    The memory circuit includes:
    In the management information storage block of each write group, record management information indicating the number of times the write group has already been written,
    When storing the setting value in the fuse memory, the setting value storage block that has not been written is specified based on the management information, and the setting value is written to the setting value storage block,
    When the setting value is used for setting the status of the electronic volume, the setting value storage block storing the latest setting value is specified based on the management information, and the setting value storage block is used to identify the setting value storage block. Reading set values,
    An image display device characterized by the above.
JP2010028186A 2010-02-10 2010-02-10 Image display device Pending JP2011164425A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103377616A (en) * 2012-04-25 2013-10-30 精工爱普生株式会社 Electro-optic device, method of driving electro-optic device, and electronic apparatus
JP2016032241A (en) * 2014-07-30 2016-03-07 ローム株式会社 Storage circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103377616A (en) * 2012-04-25 2013-10-30 精工爱普生株式会社 Electro-optic device, method of driving electro-optic device, and electronic apparatus
US9107247B2 (en) 2012-04-25 2015-08-11 Seiko Epson Corporation Electro-optic device, method of driving electro-optic device, and electronic apparatus
US9478165B2 (en) 2012-04-25 2016-10-25 Seiko Epson Corporation Electro-optic device, method of driving electro-optic device, and electronic apparatus
JP2016032241A (en) * 2014-07-30 2016-03-07 ローム株式会社 Storage circuit

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