KR102321174B1 - Memory-in-pixel display - Google Patents

Abstract

The electronic display 18 may include an active area having a first pixel 70 , wherein the first pixel 70 is formed in the active area, wherein the first pixel 70 is responsive to image data 86 . to emit light. Electronic display 18 may also include controllers 60 , 62 , 54 for transmitting image data 86 to first pixel 70 . The first pixel 70 has a memory 78 for digitally storing the image data 86 received from the controllers 60 , 62 , 54 and a driver for receiving the image data 86 from the memory 78 . A circuit part 80 may be included. The driver circuitry 80 may cause light to be emitted in response to the image data 86 .

Description

Memory-in-pixel display

An overview of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief overview of some of these embodiments, and that these aspects are not intended to limit the scope of the disclosure. Indeed, the present disclosure may include various aspects that may not be described below.

Methods and systems for reducing concurrently transmitted amounts of image data, or bandwidths of image data transmitted and processed to prepare an image for presentation on an electronic display by implementing memory within pixels of an electronic display, are enormous. can provide value. Such memory implementation within the pixels may allow for the elimination of a frame buffer associated with an electronic display. Having memory within the pixels may also alleviate the design complexity of electronic displays, since the fewer images simultaneously transmitted to the pixel array of the electronic display, the simpler the electronic display can be designed. For example, pixels may be programmed into smaller groups, since the memory within the pixel stores values until presentation of the image.

This disclosure describes an electronic display having one or more pixels including a driver and memory that can help reduce bandwidth associated with transmitting and processing image data for presentation on the electronic display. The inclusion of a memory within a pixel may enable storage of image data prior to output to the light emitting portion of the pixel. Thus, memory within a pixel can reduce, or in some cases eliminate, reliance on a frame buffer within an electronic display by acting as a separate frame buffer for the pixel. The memory within the pixel may be used in conjunction with a driver to cause the light emitting portion of the pixel to emit light.

Various aspects of the present disclosure may be better understood upon reading the following detailed description and with reference to the drawings.
1 is a schematic block diagram of an electronic device according to an embodiment.
Fig. 2 is a perspective view of a watch representing an embodiment of the electronic device of Fig. 1 according to an embodiment;
3 is a front view of a tablet device representing an embodiment of the electronic device of FIG. 1 according to an embodiment;
4 is a front view of a computer representing an embodiment of the electronic device of FIG. 1 according to an embodiment;
5 is a block diagram of a display system of the electronic device of FIG. 1 according to an embodiment.
6 is a block diagram of a pixel array of the display system of FIG. 5 according to an embodiment.
7 is a block diagram of one embodiment of the pixel array of FIG. 6 according to one embodiment.
8 is a block diagram of the pixels of the pixel array of FIG. 6 emitting light according to a binary pulse width modulated emission scheme, according to one embodiment.
9 is a block diagram of one embodiment of a pixel of the pixel array of FIG. 6 emitting light according to a single pulse width modulated emission scheme, according to one embodiment.
10 is a block diagram of another embodiment of a pixel of the pixel array of FIG. 6 emitting light according to a pulse density modulated emission scheme, according to one embodiment.
11 is a timing diagram of programming sequences performed by a column driver of the display system of FIG. 5 , according to one embodiment.
12 is a circuit diagram of a first embodiment of a subpixel of the pixel array of FIG. 6 with a current drive, according to one embodiment.
13 is a circuit diagram of a second embodiment of a subpixel of the pixel array of FIG. 6 with a memory and a hybrid drive, according to one embodiment.
14 is a timing diagram of control signals used to operate the subpixel of FIG. 13 to display an image, according to one embodiment.
FIG. 15 is a graph showing currents and voltages generated by simulating transmission of image data corresponding to the binary pulse width modulated emission scheme for the subpixel of FIG. 12 , according to one embodiment;
16 is a graph showing currents and voltages generated by simulating transmission of image data corresponding to the binary pulse width modulated emission scheme for the subpixel of FIG. 13, according to one embodiment;
FIG. 17 is a circuit diagram of memory circuitry coupled to the subpixel of FIG. 12 , according to an embodiment.
FIG. 18 is a circuit diagram of one embodiment of the memory circuitry of FIG. 17 coupled to one embodiment of the subpixel of FIG. 12 implementing a global anode, according to one embodiment;
19 is a process for operating the subpixel of FIG. 18 , according to one embodiment.
FIG. 20 is a circuit diagram of a subpixel of FIG. 18 that implements a global cathode according to an embodiment;
21 is a circuit diagram of an embodiment of the memory circuit unit of FIG. 13 according to an embodiment.
22 is a process for operating the memory circuitry of FIG. 21 , according to one embodiment.
23 is a circuit diagram of an embodiment of the memory circuit unit of FIG. 13 according to an embodiment.
FIG. 24A is a bit-plane graph corresponding to no reordering implemented in the memory circuitry of FIG. 23 , according to an embodiment.
FIG. 24B is an error graph corresponding to no rearrangement implemented in the memory circuit unit of FIG. 23 , according to an exemplary embodiment.
FIG. 24C is a bit-plane graph corresponding to two reorderings implemented in the memory circuitry of FIG. 23 , according to an embodiment.
FIG. 24D is an error graph corresponding to two reorderings implemented in the memory circuit unit of FIG. 23 , according to an embodiment.
FIG. 24E is a bit-plane graph corresponding to three reorderings implemented in the memory circuitry of FIG. 23 , according to an embodiment.
FIG. 24F is an error graph corresponding to three reorderings implemented in the memory circuit unit of FIG. 23 , according to an embodiment.
FIG. 24G is a bit-plane graph corresponding to the ideal case of reordering implemented in the memory circuitry of FIG. 23 , according to an embodiment.
FIG. 24H is an error graph corresponding to an ideal case of reordering implemented in the memory circuit unit of FIG. 23 , according to an embodiment.
25 is a bit-plane graph illustrating the bit-plane graph of FIG. 24C over time and with inclusion of additional color channels, according to one embodiment.
FIG. 26 is a timing diagram illustrating a loading and ejection process associated with a third quadrant of the bit-plane graph of FIG. 25, according to one embodiment.
27 is a circuit diagram of one embodiment of the memory circuitry of FIG. 23 implemented for use in a digital mirror display, according to one embodiment.
28 is a circuit diagram of one embodiment of the pixel of FIG. 25 for use in a liquid crystal display, according to one embodiment.
FIG. 29 is a block diagram comparing the display system of FIG. 5 with a display system having a smart buffer outside an active area of an electronic display, according to one embodiment.
30 is a circuit diagram of one embodiment of the memory circuitry of FIG. 13 for use in the smart buffer of FIG. 29, according to one embodiment.
FIG. 31 is a circuit diagram of a third embodiment of a subpixel of the pixel array of FIG. 6 for use in the display system with the smart buffer of FIG. 29, according to one embodiment;

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, the specification does not describe all features of an actual implementation. In the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from implementation to implementation. you have to understand that Further, it is recognized that such development efforts can be complex and time consuming, but will nevertheless be a routine task of design, manufacture, and fabrication for those of ordinary skill in the art having the benefit of this disclosure. have to understand

When introducing elements of various embodiments of the present disclosure, the singular forms “a”, “an”, and “the” are intended to mean that one or more of the elements is present. The terms “comprising, including,” and “having” are inclusive and are intended to mean that additional elements other than those listed may be present. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be construed as excluding the existence of additional embodiments that also include the listed features.

BACKGROUND Electronic displays are found in many electronic devices, from cell phones to computers, televisions, car dashboards, and more. Electronic displays have achieved increasingly higher resolutions by reducing individual pixel size. However, increasing resolutions may result in increased power consumption associated with increased resolutions being processed by processing circuitry prior to displaying the image, for example, by causing increased power consumption from processing increased amounts of image data. It can increase the difficulties associated with managing the amount of image data. Moreover, increasing resolutions can increase the bandwidth used to pass image data from processing circuitry to a pixel array for presentation of the image, because it takes more images to convey the same image at higher electronic display resolutions. Because data is used.

Embodiments of the present disclosure relate to systems and methods for implementing memory-in-pixel circuitry that can be used as a separate frame buffer for each pixel, including a pixel array of an electronic display and a frame external to driving circuitry. Reliance on buffers can be reduced. The memory may be implemented in a pixel circuit unit including a light-emitting diode (LED). Although organic light-emitting diodes (OLEDs) represent one type of LED that may be found in a pixel, other types of LEDs may also be used, or liquid crystal displays (LCDs), plasma Light emitting components such as display panels and/or components for supporting dot-matrix displays may be used in the pixel circuitry.

Systems and methods of the present disclosure for implementing memory-in-pixel circuitry can reduce transmission bandwidths of image data to pixel arrays for display, because a pixel cannot store image data in memory. because there is In this way, the dependence on frame buffers for temporarily storing image data outside the pixel is reduced, since a pixel has its own memory for storing its own image data prior to display of the image data. Because.

A general description of suitable electronic devices that may include a self-emissive display and corresponding circuitry, such as the LED (eg, OLED) display of the present disclosure, is provided. OLED represents one type of LED that can be found in a self-emissive pixel, but other types of LEDs can also be used.

For illustrative purposes, an electronic device 10 including an electronic display 18 is shown in FIG. 1 . As described in more detail below, electronic device 10 may be any suitable electronic device, such as a computer, mobile phone, portable media device, tablet, television, virtual reality headset, vehicle dashboard, and the like. Accordingly, it should be noted that FIG. 1 is only one example of a specific implementation and is intended to illustrate the types of components that may be present in the electronic device 10 . Electronic device 10 includes, inter alia, processing core complex 12 such as system on a chip (SoC) and/or processing circuit(s), storage device(s) 14, communication interface(s) ) 16 , an electronic display 18 , input structures 20 , and a power source 22 . The various components described in FIG. 1 may include hardware elements (eg, circuitry), software elements (eg, a tangible non-transitory computer-readable medium storing instructions), or a combination of both hardware and software elements. may include. It should be noted that the various illustrated components may be combined into fewer components or may be separated into additional components.

As shown, the processing core complex 12 is operatively coupled with the storage device(s) 14 . Accordingly, processing core complex 12 may execute instructions stored in storage device(s) 14 to perform operations such as generating and/or transmitting image data. As such, processing core complex 12 may include one or more general purpose microprocessors, one or more application specific integrated circuits (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof. Using pixels that include light emitting components (eg, LEDs, OLEDs), electronic display 18 can show images generated by processing core complex 12 .

In addition to instructions, storage device(s) 14 may store data to be processed by processing core complex 12 . Accordingly, in some embodiments, storage device(s) 14 may include one or more tangible, non-transitory computer-readable media. The storage device(s) 14 may be volatile and/or non-volatile. For example, the storage device(s) 14 may be non-rewritable, such as random access memory (RAM) and/or read only memory (ROM), flash memory, hard drives, optical disks, and the like. volatile memory, or any combination thereof.

As shown, the processing core complex 12 is also operatively coupled with the communication interface(s) 16 . In some embodiments, communication interface(s) 16 may facilitate communicating data with other electronic devices and/or networks. For example, the communication interface(s) 16 (eg, a radio frequency system) may enable the electronic device 10 to connect to a personal area network (PAN), such as a Bluetooth network, or a local area network (LAN), such as a 1622.11x Wi-Fi network. ), and/or to a wide area network (WAN), such as a 4G or Long-Term Evolution (LTE) cellular network.

Additionally, as shown, the processing core complex 12 is also operatively coupled to a power supply 22 . In some embodiments, power source 22 may provide power to one or more components within electronic device 10 , such as processing core complex 12 and/or electronic display 18 . Accordingly, the power source 22 may include any suitable energy source, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter.

As shown, the electronic device 10 is also operatively coupled with one or more input structures 20 . In some embodiments, input structures 20 may facilitate user interaction with electronic device 10 , for example by receiving user inputs. Accordingly, input structures 20 may include buttons, keyboards, mice, trackpads, and the like. Additionally, in some embodiments, input structures 20 may include touch sensitive components within electronic display 18 . In such embodiments, the touch sensitive components may receive user inputs by detecting the occurrence and/or location of an object touching the surface of the electronic display 18 .

In addition to enabling user inputs, electronic display 18 may include a display panel having one or more display pixels. As described above, the electronic display 18 displays frames based, at least in part, on the corresponding image data, thereby providing information such as a graphical user interface (GUI), an application interface, a still image, or video content of an operating system. Light emission from display pixels can be controlled to present visual representations. As shown, the electronic display 18 is operatively coupled to the processing core complex 12 . In this manner, the electronic display 18 may display frames based at least in part on the image data generated by the processing core complex 12 . Additionally or alternatively, electronic display 18 may display frames based at least in part on image data received via communication interface(s) 16 and/or input structures 20 .

As can be appreciated, the electronic device 10 may take many different forms. As shown in FIG. 2 , the electronic device 10 may take the form of a watch 30 . For illustrative purposes, watch 30 may be any Apple Watch® model available from Apple Inc. As shown, the watch 30 includes an enclosure 32 (eg, a housing). In some embodiments, enclosure 32 may protect internal components from physical damage and/or shield them from electromagnetic interference (eg, may house components). Strap 34 may allow watch 30 to be worn on an arm or wrist. The electronic display 18 may display information related to the operation of the watch 30 . Input structures 20 allow a user to activate or deactivate watch 30 , navigate a user interface to a home screen, navigate a user interface to a user-configurable application screen, and/or , enable voice-recognition features, provide volume controls, and/or enable toggling between vibrate and ring modes. As shown, input structures 20 can be accessed through openings in enclosure 32 . In some embodiments, input structures 20 may include, for example, an audio jack for connecting to external devices.

The electronic device 10 may also take the form of a tablet device 40 , as shown in FIG. 3 . For illustrative purposes, tablet device 40 may be any iPad® model available from Apple Inc. Depending on the size of the tablet device 40 , the tablet device 40 may serve as a handheld device, such as a mobile phone. The tablet device 40 includes an enclosure 42 from which input structures 20 may protrude. In certain examples, input structures 20 may include a hardware keypad (not shown). Enclosure 42 also holds electronic display 18 . The input structures 20 may enable a user to interact with the GUI of the tablet device 40 . For example, input structures 20 may enable a user to type a Rich Communication Service (RCS) text message, a Short Message Service (SMS) text message, or make a phone call. The speaker 44 may output the received audio signal, and the microphone 46 may capture the user's voice. Tablet device 40 may also include a communication interface 16 that allows tablet device 40 to connect to other electronic devices via a wired connection.

4 illustrates a computer 48 representing another form that the electronic device 10 may take. For illustrative purposes, computer 48 may be any Macbook® or iMac® model available from Apple Inc. It should be understood that the electronic device 10 may also take the form of any other computer, including a desktop computer. The computer 48 shown in FIG. 4 includes an electronic display 18 and input structures 20 including a keyboard and a track pad. The communication interfaces 16 of the computer 48 may include, for example, a universal service bus (USB) connection.

In any case, as described above, operating the electronic device 10 to convey information by displaying images on the electronic display 18 of the electronic device 10 generally consumes power. Additionally, as noted above, electronic devices 10 often store a finite amount of electrical energy. Thus, to facilitate improving power consumption efficiency, electronic device 10 is, in some embodiments, memory-in as a way to reduce or eliminate the use of an external frame buffer in displaying images. - an electronic display 18 that implements pixels and thus reduces the power consumed by the use of the frame buffer in displaying images and/or reducing the bandwidth of image data received within the electronic display 18 can In some cases, an internal frame buffer (eg, located within the electronic display 18 , eg, within the display driver integrated circuit of the electronic display 18 ) may be used instead of or in addition to memory-in-pixel techniques. can By implementing memory-in-pixel or related techniques, the electronic display 18 may be programmed with smaller bandwidths of image data, further enabling power consumption savings. In addition, an electronic display 18 that uses memory in pixels or in an onboard frame buffer may have a less complex design than the electronic display 18 with no memory in pixels or no onboard frame buffer. These gains can be realized because the pixel retains the transmitted data into its memory until new image data is written to the memory.

Similarly, portions of image data can program a subset of pixels associated with electronic display 18 at a time. The image to be displayed is typically converted to numerical data or image data, such that the image becomes interpretable by the components of the electronic display 18 . In this way, the image data itself can be divided into small “pixel” portions, each of which may correspond to a pixel portion of the electronic display 18 , or a pixel portion of a display panel corresponding to the electronic display 18 . can In some embodiments, the image data is represented through combinations of red-green-blue light, so that one pixel that appears to have a single color actually emits a proportion of red, green, and blue light, respectively. 3 sub-pixels to produce that single color. In this way, the numerical values or image data that quantify combinations of red-green-blue light are to a digital luminance level or gray level that correlates the luminance intensity (eg, brightness) of the color of the image data for those specific subpixels. can respond. As will be appreciated, the number of gray levels in an image usually depends on the number of bits used to represent the gray levels in a particular electronic display 18 , which may be represented as ^{2 N gray levels, where N} corresponds to the number of bits used to represent the gray levels. As an example, in one embodiment where the electronic display 18 uses 8-bits to represent gray levels, the gray level is: for a total of 256 potential gray levels, 0 to maximum illumination for black or no illumination and / or reach a range of 255 for sufficient lighting. Similarly, an electronic display 18 using 6-bits can represent the luminance intensity for each subpixel using 64 gray levels.

Having a memory within the pixels of the electronic display 18 allows image data to be transmitted in subpixels associated with one color, without the image data having to be transmitted simultaneously to additional subpixels associated with a second color. . For the purposes of this disclosure, subpixels are discussed with respect to red-green-blue color channels, where a color channel, when combined with additional color channels, for a single color produces an image of the true or desired color. A layer of image data comprising gray levels, wherein image data for a color channel corresponds to image data transmitted in subpixels for that color channel. However, it should be understood that any combination of color channels and/or subpixels such as blue-green-red, cyan-magenta-yellow, and/or cyan-magenta-yellow-black may be used.

For illustrative purposes, a display system 50 associated with an electronic display 18 that does not implement memory-in-pixel and a display system 52 associated with an electronic display 18 that implements memory-in-pixel are illustrated in FIG. 5 . , each of which may be implemented in the electronic device 10, respectively. The display system 50 includes a timing controller 54 for receiving image data 56 , a frame buffer 58 communicatively coupled to the timing controller 54 via a communication link 64 , and a row driver 60 . ) and a column driver 62 , and a pixel array 66 that receives control signals from the column driver 62 and the row driver 60 to produce an image on the electronic display 18 . Moreover, the display system 52 includes a timing controller 54 for receiving image data 56 , a row driver 60 and a column driver communicatively coupled to the timing controller 54 via a communication link 68 . 62 , and a pixel array 69 implementing memory-in-pixel techniques for receiving control signals from a column driver 62 and a row driver 60 to produce an image on the electronic display 18 . .

In preparing to display the image, display system 50 may receive image data 56 from timing controller 54 . The timing controller 54 receives and uses the image data 56 and clock signals to control the presentation of the image data 56 to the pixel array 66 via the column driver 62 and the row driver 60 . and/or control signals. Additionally or alternatively, in some embodiments, image data 56 is received by frame buffer 58 .

In either case, frame buffer 58 may serve as external storage for timing controller 54 to store image data 56 prior to output to column driver 62 and/or row driver 60 . . Timing controller 54 may transmit image data 56 from frame buffer 58 to column driver 62 and/or row driver 60 via communication link 64 .

Communication link 64 transfers image data 56 associated with all channels, eg, image data 56 associated with red, green, and blue channels, to row driver 60 and/or column driver 62 . ) large enough to transmit simultaneously (eg, determined via the transmission bandwidth of the image data). In this manner, the communication link 64 simultaneously carries image data 56 associated with each pixel of the pixel array 66 for the red channel, the green channel, and the blue channel. The column driver 62 and the row driver 60 may send control signals based on the image data 56 to the pixel array 66 . In response to the control signals, the pixel array 66 transmits an image by emitting light at various luminosity or brightness, represented, for example, through gray levels ranging from 0 to 255.

However, the display system 52 receives the image data 56 from the timing controller 54 . Timing controller 54 may use image data 56 to determine clock signals used to supply image data 56 to memory-in-pixel pixel array 69 . Timing controller 54 sends image data 56 to row driver 60 and/or column driver 62 to program memory of pixel array 69 with digital data signals associated with image data 56 . where the digital data signals represent the emission brightness/gray level for the pixels of the pixel array 69 .

By implementing the memory-in-pixel systems and methods, the display system 52 can reduce the bandwidth of the signals conveyed over the communication link 68, for example, as compared to the bandwidth of the signals conveyed over the communication link 64. Bandwidth can be reduced. In some cases, a single channel of image data 56 can be used over communication link 64 as opposed to all channels being simultaneously transmitted to pixel array 66 (eg, red-green-blue channels). may be transmitted via (eg, a red channel). In this manner, the communication link 68 carries image data 56 associated with each pixel of the pixel array 66 for the red channel, the green channel, and the blue channel at different times, thereby transferring the image data 56 . This results in a reduction in the overall bandwidth of the signals used to carry them. Reducing the overall bandwidth of the communication link 68 may lead to a reduction in power consumption of the electronic device 10 because processing less data (eg, image data of a single channel) at a given time This is because it can consume less processing resources than processing more data (eg, image data of three channels).

Timing linked to row driver 60 and/or column driver 62 via communication link 68 to further elaborate on operating pixel array 69 with memory-in-pixel to display images. An example of a display system 52A implementing memory-in-pixel with a controller 54 is shown in FIG. 6 . Display system 52A includes subpixels 72 corresponding to the color channels of electronic display 18 , such as red subpixel 72R, green subpixel 72G, and blue subpixel 72B. a pixel array 69 of L rows by M columns having one or more pixels 70 each having and a driver (DRV) 80 that operates the subpixel 72 to emit light, and is shown in FIG. It should be understood that the illustrated display system 52A is exemplary only and is not intended to be limiting. For example, in some embodiments, pixel array 69 may contain varying amounts of cyan, yellow, cyan corresponding to cyan-yellow-magenta color channels instead of or in addition to red-green-blue color channels; and subpixels 72 emitting magenta light.

To describe the operation of display system 52A, timing controller 54 receives image data 56 corresponding to the next image to be displayed on an electronic display having pixel array 69 . The timing controller 54 generates control signals and/or clocking signals in response to the image data 56 and sends signals related to operating the rows of pixels 70 to the row driver 60; Signals related to operating the columns of pixels 70 are sent to the column driver 62 . Row driver 60 is responsive to signals associated with image data 56 transmitted from timing controller 54 , emission control signals 82 and write control for each red-green-blue (RGB) channel. Generate signals 84 . Column driver 62 , also responsive to signals associated with image data 56 transmitted from timing controller 54 , generates image data 86 to be transmitted to memory 78 of each of pixels 70 . Column driver 62 may generate image data 86 in response to image data 56 and/or signals associated with image data 56 , although in some embodiments, image data 56 may Data 86 is transmitted to each of the pixels 70 . Column driver 62 generates data of size N bits for each subpixel 72 , which also matches the size of memory 78 which is size N bits.

Generally, through transmission of emission control signals 82 , write control signals 84 , and image data 86 , pixels 70 emit light to produce an image on electronic display 18 . operated to emit. Each of the pixels 70 has a respective emission control signal 88 of the emission control signals 82 transmitted from the row driver 60 , a respective three write control signals 90 of the write control signals 84 . ), and respective image data 92 for channels of pixel 70 , eg, N bits of image data (image data - R) 92R for the red channel, N bits for the green channel. Receive bits of image data (image data - G) 92G, and N bits of image data (image data - B) 92B for the blue channel. The write control signals 84 may enable the memory 78 of the pixel 70 to be programmed by the image data 86 transmitted by the column driver 62 . Also, a respective emission control signal 88 of the emission control signals 82 may control whether the pixel 70 is capable of emitting light. Emission control signal 88 is transmitted to respective pixels 70 in a column. The enabled emission control signal 88 activates the driver 80 such that digital image data 92 from the memory 78 causes light to be emitted from the pixel 70 using analog data signals. 70 , for example a light emitting diode (LED) associated with subpixel 72 . In the illustrated embodiment, columns of pixels 70 , eg pixels 70 ( R1C1 , R2C1 , R3C1 , through RLC1 ) in the first column receive the same emission control signal 88 . The image data 92 sent to the pixel 70 causes the pixel 70 to emit light of full color and/or brightness.

The perceived color emitted from the pixel 70 changes based on the light emitted from each of the three channels of the pixel 70 , ie the light emitted from each of the respective subpixels. For example, operating each subpixel to output a brightness of 0 causes the pixel 70 to appear off, while making the red subpixel 72R to output a brightness of 100% and a brightness of 50%. Operating the green subpixel 72G to output and the blue subpixel 72B to output 0% brightness may cause the pixel 70 to emit an overall color perceived as an orange color. Thus, data is rendered and transmitted to each subpixel 72 to correspond to the respective color channels of pixel 70 .

Implementing memory 78 in pixel 70 allows image data 92 to be programmed into pixel 70 prior to the desired presentation time of the image. In some embodiments, enabled write control signal 90 causes memory 78 to erase (or overwrite) stored image data 92 , where not enabling write control signal 90 means Allow memory 78 to hold programmed image data 92 . For example, to write new image data, the write control signal - R (90R) causes the memory 78 of the red subpixel 72R to erase, the new image data, i.e. the image data - R (92R). Writes may be loaded into memory 78 . In this example, the write control signal - B ( 90B) was not enabled, and thus the memory 78 of the blue subpixel 72B erases its programmed image data, i.e., the image data - B ( 92B). without continuing to hold it. Having the memory 78 within the pixels 70, as previously described with reference to FIG. 5, allows the memory 78 to allow portions of the image data 86 to be written at a time instead of the entire frame of data. power used to process the image data as well as an improvement to display technologies and processing techniques as the improved use of the available bandwidth allows the transfer of image data for display on the electronic display 18 . improvements to consumption.

In the pixel array 69 , image data 86 is transferred from the column driver 62 to the subpixels 72 via a direct communication coupling, for example via a communication coupling 94 . In some embodiments, the multiplexing circuit may be configured such that, for example, in such arbitration, red subpixel 72R may not receive image data 98 concurrently with blue subpixel 72B or green subpixel 72G. In this case, a multiplexing control signal is used to control the transmission of image data 86 to subpixels 72 such that the multiplexing control signal is used by column driver 62 to mediate transmission of image data 98 to subpixels 72 . can be used to

For the purposes of the above, a display system associated with an electronic display 18 implementing a memory-in-pixel including a timing controller 54 that is linked to a row driver 60 and a column driver 62 via a communication link 68 . An exemplary embodiment of 52B is shown in FIG. 7 . Display system 52B, similar to display system 52A shown in FIG. 6 , includes a pixel array 69 of L rows by M columns having one or more pixels 70 , and includes one or more pixels 70 . ) each has subpixels 72 , eg, a red subpixel 72R, a green subpixel 72G, and a blue subpixel 72B, where each of the subpixels 72 has at most N bits. and a memory 78 for storing them and a driver (DRV) 80 for operating the subpixels 72 to emit light, as shown in FIG. 6 . It should be understood that the illustrated display system 52B is exemplary only and is not intended to be limiting. Note that functions and/or descriptions of the display system 52 that are common to both FIGS. 6 and 7 are dependent on this disclosure.

In the exemplary embodiment of display system 52B of FIG. 7 , pixel array 69 includes multiplexing circuitry 96 that receives image data 98 of size N bits from column driver 62 . The multiplexing circuit 96 is responsive to a respective multiplexing control signal (MUX control signal) 100 of the multiplexing control signals 101 . The MUX control signal 100 may cause the multiplexing circuit 96 to output data to the subpixel 72 of the pixel 70 . In this way, the column driver 62, via emission of the MUX control signal 100 , connects the subpixel 72 (eg, one color channel) of the pixel 70 to, for example, the communication coupling 94 . ), it can operate to program at once. For pixel array 69, various embodiments of subpixel 72 circuits may be used.

An example of one embodiment of a subpixel 72 implementing memory-in-pixel techniques is a memory 78 , a driver 80 , a current source 102 , an LED 103 , a switch 104 , and a counter 105 . wherein subpixel 72 includes image data 98 , bit-plane clock 106 , reset signal 108 , common voltage 110 , first reference voltage 112 , second reference voltage ( 114 , and various signals including data clock 116 , shown in FIG. 8 . It should be understood that the illustrated subpixels 72 are exemplary only and are not intended to be limiting. For example, memory 78 is shown as a 12-bit register, but may be any suitable memory circuit for storing any suitable number of bits.

The illustrated subpixel 72 may emit according to a binary pulse width modulated emission scheme. To illustrate the operation of subpixel 72 , image data 98 is sent to memory 78 , for example from column driver 62 . Additionally or alternatively, image data 92 , image data 56 , or any suitable image data may be sent to memory 78 for storage. Upon receiving image data 98 , memory 78 stores image data 98 clocked in by data clock 116 . Image data 98 may be represented by binary data such that any given bit may be equal to zero (“0”) or one (“1”), where 0 is a logical low for the system. ) voltage value, and 1 corresponds to a logical high voltage value for the system. Memory 78 stores image data 98, for example, bit by bit, in order from least significant bit to most significant bit, according to a clocking signal generated by the combination of counter 105 and bit-plane clock 106 . ) can be output to the switch 104 .

As shown, the bit-plane clock 106 has clocking periods that increase over time to correspond to the level of influence of a particular bit in the image data 98 . In this way, the least significant bit of image data 98 may be associated with a smaller clocking period than the most significant bit of image data 98 .

When memory 78 outputs image data 98 , for example on the rising edge of bit-plane clock 106 , image data 98 operates switch 104 to open or close. Bit 0 causes switch 104 to open, causing LED 103 to not emit light, while bit 1 causes switch 104 to close, causing LED 103 to emit light. The operation of the switch 104 occurs at various emission periods as a way to modulate the emission of light from the LED 103 , causing the perceived brightness of the subpixel 72 to change as the modulation changes. Thus, through the relationship between the memory 78 and the image data 98 output from the switch 104, the image data 98 equal to “000000000000” may cause the LED 103 not to emit light, while Image data 98 equal to “101011000111” may cause LED 103 to be perceived as brighter. Image data 98 equal to “101011000111” can be perceived as brighter because subpixel 72 has a value that causes switch 104 to be activated to emit light, each logical high value. This is because it operates to emit light in response to a “1”. The more the switch 104 is activated during the emission period, the brighter the pixel is perceived because more light is emitted over time (eg, light is emitted in response to a "1" and a "0" "Not released in response to"). In this way, the image data 98 is not an exact binary representation of the gray level, but can be derived from the desired gray level for the subpixel 72 . It should be noted, however, that there may be scenarios where the desired gray level for subpixel 72 is actually the same as the binary representation transmitted via image data 98 .

When the switch 104 is closed, an electrical connection is created between the common voltage 110 and the first reference voltage 112 . This allows the current from the current source 102 to be transmitted through the LED 103 so that light can be emitted from the subpixel 72 . Accordingly, the emission periods of the subpixel 72 can be varied to control the perceived light emitted from the subpixel 72 , where the emission periods are the bit arrangement of the image data 98 stored in the memory 78 ( For example, the most significant bit, the least significant bit), and thus, the closer the bit of the image data 98 is to the most significant bit position, the longer the emission period corresponding to that bit of the image data 98 is. Once the counter 105 has counted up to 11, the counter 105 is restarted and, for example, the bit-plane clock 106 clocks its clock to correspond to the next least significant bit since the last most significant bit emission period. Restart intervals. Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to vary the overall current value used to control the light emitted from the LED 103 . For example, the second reference voltage 114 causes the LED 103 to emit light from the LED 103 or a lower current value can be used to enable the LED 103 to respond to current changes. can increase the sensitivity of

This emission scheme is generally referred to as a binary pulse width modulated emission scheme for a subpixel 72 because the image data 98 changes the perceived brightness of the subpixel 72 in such a way that the subpixel 72 72) because it is binary data selected to modulate the light emission from Graph 118 shows emission periods for subpixel 72 caused by a binary pulse width modulated emission scheme. With a binary pulse width modulated emission scheme, the subpixel 72 is operated to vary the perceived brightness of the light emitted through various emission periods of the light. As shown in graph 118, image data 98 received by subpixel 72 is represented via five bits of binary data. Thus, when the image data 98 is equal to 01111, the subpixel 72 is a first having emission periods 124A for the least significant bit and emission periods 124B, 124C, 124D for subsequent bits. It emits light corresponding to the range 120 . In this embodiment, the least significant bit of the image data 98 from the memory 78 first actuates the switch 104, for this reason the least significant bit corresponds to the first emission period 124A in time. As such, between the transmission of the bits to actuate the switch 104, the emission is temporarily stopped, as there appears to be no emission period between the first emission period 124A and the emission period 124B. Further, when the image data 98 is equal to 11111 , the emission period of the subpixel 72 corresponds to the second range 122 , which corresponds to the first range 120 and the last emission period corresponding to the most significant bit ( 124E) (eg, because the most significant bit is currently enabled as a 1).

When following the binary pulse width modulated emission scheme, image data 98 with data of 01111 is, due to how light is perceived by the viewer of electronic display 18, image data 98 with data of 11111 perceived as less bright. This is because the more emission periods that occur during the total emission cycle (eg, as represented by all 1s in image data 98 , ie, 11111 ), the brighter the light emitted from subpixel 72 is perceived. am. As such, when the subpixel 72 emits during the last emission period 124E in addition to the first range 120 (eg, when the most significant bit of the image data 98 is 1), the subpixel 72 is It may be perceived that the subpixel 72 is brighter on the electronic display 18 than it emits only for the first range 120 .

Another example of one embodiment of a subpixel 72 including a memory 78 , a driver 80 , a current source 102 , an LED 103 , a switch 104 , a counter 130 , and a comparator 132 is shown in FIG. 9 , where subpixel 72 includes image data 98 , gray level clock 134 , common voltage 110 , first reference voltage 112 , second reference voltage 114 , and data It receives various signals including a clock 116 . It should be understood that the illustrated subpixels 72 are exemplary only and are not intended to be limiting. For example, memory 78 is shown as an 8-bit register, but may be any suitable memory circuit for storing any suitable number of bits.

The illustrated subpixel 72 with memory-in-pixel can emit according to a single pulse width emission scheme. To account for the operation of subpixel 72 , image data 98 is sent to memory 78 for storage, eg, from column driver 62 . Additionally or alternatively, image data 92 , image data 56 , or any suitable image data may be sent to memory 78 for storage. In some embodiments, image data 98 may be clocked into memory 78 by data clock 116 , for example, on a rising edge of data clock 116 . The image data 98 passed to the subpixel 72 may correspond to the desired gray level at which the subpixel 72 is emitting light. Using the image data 98 stored in memory 78 , comparator 132 determines whether the current number represented by counter 130 is less than or equal to image data 98 in memory 78 . In other words, the counter 130 counts up to the number represented by the image data 98 , and the number represented by the counter 130 satisfies a condition, for example the number represented by the image data 98 . In response to being less than or equal to, comparator 132 outputs a control signal to close switch 104 when the condition is met. When the condition is not met, the comparator 132 opens the switch 104 without outputting a control signal. Additionally or alternatively, comparator 132 may enable a deactivation control signal to cause switch 104 to open. For example, if memory 78 stores the binary sequence of 10110101 corresponding to number 181, comparator 132 will check whether counter 130 has counted to number 181, and When 130 exceeds number 181 , comparator 132 sends a signal to open switch 104 , thus stopping emission.

When the switch 104 is closed, an electrical connection is created between the common voltage 110 and the first reference voltage 112 . This causes the current from the current source 102 to be transmitted through the LED 103 , causing light to be emitted from the subpixel 72 . Accordingly, the emission periods of the subpixel 72 can be varied to control the perceived light emitted from the subpixel 72 through changing the number represented by the image data 98 . Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to vary the overall current value used to control the light emitted from the LED 103 . For example, the second reference voltage 114 causes the LED 103 to emit light from the LED 103 or a lower current value can be used to enable the LED 103 to respond to current changes. can increase the sensitivity of

The counter 130 counts from 0 to 255 and increments based on the rising edge of the gray level clock 134 , for example the gray level clock 134 . The periods of the gray level clock 134 are the time difference between the increments of the gray level for the electronic display 18 , eg, the time difference between emitting a gray level of 100 and emitting a gray level of 101 . express the difference In this way, the counter 130 counts up to the number represented by the image data 98 stored in the memory 78, which subsequently causes emission to occur for a period corresponding to the desired gray level. Counter 130 may continue to count beyond the number represented by image data 98 stored in memory 78 up to a maximum value, e.g., 255, and restart counting at a minimum value, e.g., 0. can Accordingly, in some embodiments, the counting range of the counter 130 may be defined through the design of the counter 130 , for example, through a number of registers and/or logic components included within the counter 130 . . Additional image data 98 may be stored in memory 78 to begin comparison to the next emission period of the gray level associated with additional image data 98 until counter 130 restarts counting at zero. have.

By following this emission scheme, the subpixel 72 can follow a single pulse width modulated emission scheme. A representation of the emission of light from subpixel 72 following a single pulse width modulated emission scheme is shown in graph 136 . The graph 136 includes an actual release period 138 and a total release period 140 . The total emission period 140 may correspond to the total length of emission represented by the maximum number transmitted as image data 98 , for example 255 , and may correspond to the maximum perceived brightness of light emitted from the subpixel 72 . have. The actual emission period 138 corresponds to the period in which the subpixel 72 emits light according to a number less than a maximum transmitted as image data 98 , for example from the counter 130 . The counter 130 increments from 0 to 255 which takes the time represented by the total emission period 140 , while the comparator 132 allows light to be emitted during the time represented by the actual emission period 138 . . In this way, subpixel 72 can emit light of various perceived brightnesses.

Another example of one embodiment of a subpixel 72 including a memory 78 , a driver 80 , a current source 102 , an LED 103 , a switch 104 , an accumulator 150 , and an adder 152 is shown in FIG. 10 , where subpixel 72 has an emission clock 154 , image data 98 , a common voltage 110 , a first reference voltage 112 , a second reference voltage 114 , and a data clock Receive various signals including 116 . It should be understood that the illustrated subpixels 72 are exemplary only and are not intended to be limiting. For example, while memory 78 is shown as capable of storing 8-bits of image data 98, it may be any suitable memory circuitry for storing any suitable number of bits.

The illustrated subpixel 72 with memory-in-pixel can emit according to a pulse density modulated emission scheme. In a pulse density modulated emission scheme, each pulse has a constant emission duration and light emitted, but variable separation intervals between pulses - where the brighter light emitted from sub-pixel 72 is more numerous during the same duration. corresponding to the pulses of To illustrate the operation of subpixel 72 for a pulse density modulated emission scheme, image data 98 is transmitted to memory 78 for storage, eg, from column driver 62 . Additionally or alternatively, image data 92 , image data 56 , or any suitable image data may be sent to memory 78 for storage. The image data 98 transmitted to the subpixel 72 is generated based on at least the desired gray level at which the subpixel 72 is emitting light.

Upon receiving the image data 98 , the memory 78 stores the image data 98 according to the data clock 116 , for example, on each rising edge of the data clock 116 , the image data ( 98) is loaded bit by bit. Memory 78 outputs image data 98 to be added to the binary data stored in accumulator 150 . Although accumulator 150 is shown as an 8-bit accumulator, it should be understood that any suitable accumulator or register may be used to temporarily store data. Adder 152 may perform binary addition of image data 98 and binary data of accumulator 150 in response to a rising edge of emission clock 154 , eg, emission clock 154 . The sum from adder 152 is sent for storage in accumulator 150 for use with the next image data 98, while a carry bit is required to open and/or close switch 104. used

When the switch 104 is closed, an electrical connection is created between the common voltage 110 and the first reference voltage 112 . This allows the current from the current source 102 to be transmitted through the LEDs 103 and, in general, light to be emitted from the subpixels 72 . In this way, the variable separation intervals between the pulse generated by the emission clock 154 and the pulse generated by the adder 152 that transmits the carry bit from the addition can vary the emission of light from the subpixel 72 . can contribute to Thus, the intervals separating the emission pulses of the subpixel 72 can be varied to control the light emitted from the subpixel 72 , where brighter light is emitted in response to the smaller intervals separating the pulses. (eg, higher density pulses correspond to brighter perceived light emitted from LED 103 ). Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to vary the overall current value used to control the light emitted from the LED 103 . For example, the second reference voltage 114 causes the LED 103 to emit light from the LED 103 or a lower current value can be used to enable the LED 103 to respond to current changes. can increase the sensitivity of

Graph 156 shows emission pulses and variable separation intervals between pulses caused by a pulse density modulated emission scheme. With a pulse density modulated emission scheme, subpixel 72 emits pulses separated by non-emission intervals of different lengths, thereby changing the overall light emitted from subpixel 72 . As shown in graph 156 , image data 98 may cause a subpixel to emit an emission pulse 158 and not to emit during a period of non-emission interval 160 . For example, the emission pulses 162 have a non-emission interval that separates the respective emission pulses, which is smaller than the emission interval 160 , so that the LED 103 of the subpixel 72 emits an emission pulse 158 . ) may emit light for emission pulses 162 , which is perceived to be brighter than the light emitted from LED 103 .

Thus, in summary, through using memory-in-pixel techniques, the timing controller 54 allows a smaller amount of the image data 98 as opposed to simultaneously programming the image data for all subpixels 72 . In portions, image data 98 may be programmed into display system 52 . For illustrative purposes, a timing diagram of a signal transmitted within display system 52 in preparation for transmitting image data for storage in one or more memories 78 is a red image data transmission period 174R, green image data A transmission period 174G, a blue image data transmission period 174B, one or more copy periods 176 , and one or more enable periods 178 are illustrated, and are shown in FIG. 11 .

As shown, column driver 62 may receive a signal to initiate a copy of red data into one or more memories 78 of one or more red subpixels 72R. Upon receiving the signal, the column driver 62 may enter a copy period 176 and prepare to transmit red data to the red subpixels 72R. During the copy period 176 , the column driver 62 enables the multiplexing circuits 96 associated with the pixels 70 of the display system 52 , for example via internal circuitry such as a row decoder. You can prepare a booklet. Column driver 62 or other suitable circuitry facilitates programming of memories 78 of red subpixels 72R, for example via enabling and/or disabling multiplexing control signals 101 . to operate the multiplexing circuits 96 to allow, and to operate the multiplexing circuits 96 to disallow programming of the memories 78 of the blue subpixels 72B and green subpixels 72G. can In this way, red image data may be transmitted to and stored in memories 78 corresponding to red subpixels 72R. At the end of the copy period 176 , the column driver 62 may transmit the red image data to the red subpixels 72R during the red image data transmission period 174R. The transmitted red image data is transmitted to respective memories 78 of the red subpixels 72R to be programmed with new red image data. In transmitting the red image data to the red subpixels 72R, the column driver 62 and the row decoder repeat the process described for the green image data and the blue image data, so that the various It is possible to enable selective programming of color channels.

In general, subpixel 72 is operated to emit light through receiving one or more control signals, such as from column driver 62 and/or row driver 60 . Row driver 60 and column driver 62 may control the operation of subpixel 72 by using control signals to control components of subpixel 72 , such as the current drive of subpixel 72 . . As described above, the column driver 62 may be responsible for the transmission of image data to at least the subpixel 72 , while the row driver 60 may include one or more devices for controlling the emission transmitted to the subpixel 72 . It may be responsible for control signals. Subpixel 72 may include any suitable controllable element responsive to such control signals and image data, such as a transistor, one example of which is a metal-oxide-semiconductor field-effect transistor. transistor, MOSFET). However, any other suitable type of controllable elements may also be used, including thin film transistors (TFTs), p-type and/or n-type MOSFETs, and other transistor types.

In some embodiments, the row driver 60 and/or the column driver 62 performs an initialization process, a charging process, a programming process, and an ejection process for the subpixel 72 on the electronic display 18 . An image can be prepared for display. Through performing these processes, the row driver 60 and/or column driver 62 of the electronic display 18 may initialize the subpixel 72 to be programmed, charge a capacitor for programming, and , can program the subpixel 72 with signals corresponding to a driving current designed to cause the subpixel 72 to emit light, allowing image data to control the emission of light from the subpixel 72 . can In some embodiments, the current drive may be responsible for generating a driving current in subpixel 72 .

To assist in detailing the subpixel circuit with current drive, an initialization transistor (MINI) 220 , a driving transistor (MDR) 222 , a selection transistor (MSEL) 224 , a switching transistor (MS) 226 . , a reset transistor (MRST) 228 , a light emitting portion such as an LED 230 , a capacitor 232 , and an auto-zero transistor (MAZ) 234 , one embodiment of a subpixel 72 is shown in FIG. 12 . is shown. It should be understood that the illustrated subpixel 72 is exemplary and not intended to be limiting. For example, while row driver 60 and column driver 62 are described herein as outputting image data and control signals related to displaying the next image on electronic display 18, any suitable component It should be understood that can be used to perform the processes described for display of a subsequent image by emitting control signals. In addition, the circuitry shown in FIG. 12 is merely an example of a circuitry implemented in the subpixel 72 and/or the pixel 70, and should not be construed as limiting. For example, instead of a current drive circuit (eg, a current drive), a voltage drive circuit (eg, a voltage drive) may be used with the subpixel 72 .

During the initialization process, row driver 60 may enable a reset control (CSreset) signal 235 and may disable an auto-zero control (CSauto.zero) signal 237 . The CSreset signal 235 may be transmitted to the MRST 228 . In response to receiving the CSreset signal 235 , the MRST 228 may be activated to allow residual signals from the display of the first image to exit from the subpixel 72 . These residual signals may be drained to a node coupled to a voltage reset (Vreset) signal 239 designed to facilitate the draining of residual signals (eg, zero volts), such as system ground or a system reference voltage. Also, the row driver 60 may enable the selection control (CSselect) signal 241 . The CSselect signal 241 may be transmitted to the MSEL 224 . In response to receiving the CSselect signal 241 , the MSEL 224 may be activated to allow transmission of the voltage data (Vdata) signal 242 to the node of the capacitor 232 . To complete the initialization process, the row driver 60 may also enable an initialization control (CSinitialization) signal 243 . The CSinitialization signal 243 may be transmitted to the MINI 220 . In response to receiving the CSinitialization signal 243 , the MINI 220 may be activated to allow initialization of the capacitor 232 to occur. In this state, the capacitor 232 may be charged with a voltage corresponding to a voltage difference between the Vdata signal 242 and the initialization voltage signal 244 . As such, the voltage difference may interfere with initialization or interfere with initialization while selecting different values for the Vdata signal 242 and the Vinitialization signal 244 based on the desired voltage level to initialize the capacitor 232 . It can be programmed through protecting subpixel 72 from receiving additional signals that could cause unintended light emissions from it. The row driver 60 may continue the initialization process until the row driver 60 disables the CSinitialization signal 243 which causes the MINI 220 to be deactivated.

After the initialization process, row driver 60 may perform a charging process while MINI 220 and MRST 228 are inactive. During the charging process, MAZ 234 and MINI 220 remain deactivated, while MSEL 224 remains activated. While the MSEL 224 is active, the capacitor 232 is charged based on the Vdata signal 242 and the reference voltage (Vreference) signal 246 . Charging capacitor 232 may allow driving current to be transmitted through MDR 222 even while MSEL 224 is inactive. In some embodiments, capacitor 232 stores the voltage value of Vdata signal 242, allowing MDR 222 to remain active throughout the emission process - subpixel 72 LED for emission. Allows to generate a constant driving current through 230. In this way, the subpixel 72 has a current drive - since the driving current allows the emission of light from the LED 230 while the MS 226 is active.

During the programming process, the row driver 60 may enable the CSauto.zero signal 237 which causes activation of the MAZ 234 . When MAZ 234 is activated, electrical coupling is formed between the node of capacitor 232 and the source node of MS 226 so that the voltage value at the source node of MS 226 is the gate voltage of MDR 222 . (Vg) to increase equal to the voltage value of (245). After a period sufficient for the voltage at the source node of MS 226 to increase equal to the voltage value at Vg 245 , row driver 60 displays CSauto.zero signal 237 causing MAZ 234 to be deactivated. can be enabled In this state, subpixel 72 is programmed with electrical signals ready to transmit to LED 230 upon activation of MS 226 . That is, in this state, subpixel 72 is ready to transmit the driving current generated through its programmed signals in response to CSimage.data signal 247 enabling MS 226 .

Upon completion of the programming process, row driver 60 may operate subpixel 72 to perform an emission process. During the emission process, the subpixel 72 emits light according to an image data control (CSimage.data) signal 247 that is transmitted, for example, from the column driver 62 to the MS 226 . The subpixel 72 may receive a CSimage.data signal 247 from any suitable component of the electronic device 10 capable of causing and/or generating image data for display via the subpixel 72 . have. MS 226 provides an enabled CSimage.data signal 247 , eg, sufficient to switch MS 226 (eg, a programmed voltage at the source node of MS 226 and a threshold of MS 226 ). It is activated in response to a voltage of a logic high bit having a value large enough to overcome the voltage. Upon activation of MS 226 , the voltage stored at the source node of MS 226 is transmitted as a driving current via LED 230 . If the driving current exceeds the threshold voltage of the LED 230, where the threshold voltage of the LED represents a constant voltage value, above which light is emitted from the LED, the LED 230 is accordingly driven by the driving current. may emit light based at least in part on the value of .

As will be understood, the CSimage.data signal 247 is binary and/or representing image data used to operate the subpixel 72 to emit at a particular gray level to convey an image (eg, a second image). or digital data. As previously discussed, the subpixel 72 may operate according to various emission schemes, and as such, the CSimage.data signal 247 sent to the MS 226 may vary between embodiments. However, throughout the embodiments, the CSimage.data signal 247 is derived from the image to be displayed on the display. Moreover, enabling and/or disabling the CSimage.data signal 247 at least in part causes the LED 230 to emit light or not to emit light, and thus, the CSimage.data signal 247 . may allow to modulate the emission of light from subpixel 72 .

Upon completion of the emission process, row driver 60 may disable CSselect signal 241 and enable CSSET signal 235, causing deactivation of MSE 224 and activation of MRST 228. . When the MSEL 224 is deactivated, the subpixel 72 may no longer operate to emit light because the capacitor 232 is no longer receiving charge, and the This is because residual signals from the emission process, which are allowed by the enabling, are emitted.

The subpixel 72 described is considered a current drive pixel because the subpixel 72 has a primary current that drives the LED 230 to either emit light or not to emit light. A primary or driving current is transmitted through MS 226 in response to various control signals that control the timing of light emission from subpixel 72 . The described subpixel 72 circuit may have certain advantages, including how the digital output may control emission from the LED 230 without further conversion to an analog output. Also, the inclusion of capacitor 232 may enable compensation for changes in threshold voltage associated with subpixel 72 from substrate bias effects, ie, a side effect associated with applying a voltage to the gate of some transistors.

Further improvements to the subpixel 72 may occur if a voltage drive is included in addition to the current drive structure of the subpixel 72 of FIG. 12 . At the beginning of the emission process, the voltage drive is enabled for a period of time to provide a boost to the anode of the LED 230 to make the initial emission of light easier, where the anode of the LED 230 is not boosted. Rather, a lower driving current may be used to enable light emission. A smaller driving current value can be used to drive the LED 230 to emit light, because the boost provided by the voltage drive causes the LED 230 to react in the forward bias region, or small current changes. This is because it can operate in the operating region of the more sensitive LED 230 .

For illustrative purposes, a second embodiment of a subpixel 72 having a memory 78 and a hybrid drive comprising a current drive 270 and a voltage drive 272 is shown in FIG. 13 . It should be understood that the illustrated subpixel 72 is exemplary and not intended to be limiting. For example, although current drive 270 and voltage drive 272 are shown as separate elements within subpixel 72 , one or both of the drives may be included in driver 80 described above.

Row driver 60 and/or column driver 62 may operate subpixel 72 to emit light by enabling and/or disabling control signals. The row driver 60 and/or the column driver 62 may be configured to enable the subpixel 72 to display image data corresponding to the image to be displayed in various ways, including an initialization process, a charging process, a programming process, and an emitting process. Control signals can be used to perform processes to cause subpixel 72 to emit light.

To help account for the interaction of the control signals emitted by the row driver 60 and/or column driver 62 and the subpixel 72 of FIG. 13, a Vdata signal 242, a CSinitialization signal 243, Timing diagrams corresponding to signals used for display, including CSselect signal 241 , CSauto.zero signal 237 , CSimage.data signal 247 , CSselect signal 280 , and CSreset signal 235 ( 279) is shown in FIG. 14 . It should be understood that the timing diagrams are exemplary and not intended to be limiting, for example, the control signals shown in FIG. 14 may represent more or fewer control signals than implemented in subpixel 72 .

The initialization process described above corresponds to period 282 . During period 282 , row driver 60 may provide a high voltage for Vdata signal 242 , enable CSinitialization signal 243 for the duration of the initialization process, and generate CSselect signal 241 . During period 284 , the CSauto.zero signal 237 may be disabled, the CSreset signal 235 may be disabled, and the CSselect signal 280 may be disabled.

Referring back to FIG. 13 , the control signals output by the row driver 60 to execute the initialization process cause activation and/or deactivation of various switching elements, as described above. Implementing the control signals of FIG. 14 in subpixel 72 causes MINI 220 to be activated in response to an enabled CSinitialization signal 243 , and MSEL 224 in response to an enabled CSselect signal 241 . ) is activated, MAZ 234 is deactivated in response to a disabled CSauto.zero signal 237 , MRST 228 is deactivated in response to a disabled CSreset signal 235 , and disabled A voltage drive switching element (MVD) 285 is deactivated in response to the CSselect signal 280 . This arrangement allows the difference in voltage values between the Vdata signal 242 and the Vinitialization signal 244 to charge the capacitor 232 . The row driver 60 may continue the initialization process until the row driver 60 disables the CSinitialization signal 243 which causes the MINI 220 to be deactivated, thus ending initialization.

Referring back to FIG. 14 , timing diagram 279 shows, after an initialization process, row driver 60 disabling CSinitialization signal 243 to perform a charging process for subpixel 72 . During the charging process, the Vdata signal 242 , the CSauto.zero signal 237 , the CSimage.data signal 247 , the CSselect signal 280 , and the CSreset signal 235 remain in their previous states. The timing diagram 279 shows, for example, at a high voltage level for the subpixel 72 circuit DVDD, corresponding to a logic high value in the binary data for the subpixel 72 and/or the electronic device 10 . shows the Vdata signal 242 of In some embodiments, DVDD is equal to the voltage value of Vreference signal 246 .

Referring again to FIG. 13 , the control signals output by the row driver 60 activate and/or deactivate various switching elements to perform the charging process. Upon disabling CSinitialization signal 243 and deactivation of MINI 220 , capacitor 232 is charged based on Vdata signal 242 and Vreference signal 246 . Charging the capacitor 232 may allow the current drive 270 to remain in use during the discharging process, even while the MSEL 224 is deactivated. In some embodiments, capacitor 232 holds the voltage value of Vdata signal 242 after the charging process, allowing MDR 222 to remain active throughout the emission process - current drive ( 270) to generate a constant driving current through LED 230 for emission.

After a set period suitable for charging capacitor 232 , row driver 60 may perform a programming process. 14, to perform the programming process, row driver 60 enables CSauto.zero signal 237 for period 286, CSinitialization signal 243, Vdata signal 242, Keep the CSimage.data signal 247, CSselect signal 280, and CSreset signal 235 in their previous state. As shown, the row driver 60 also sends a ground voltage GND as the Vdata signal 242 for a period 288 during the programming process. GND may be equal to zero volts or any suitable ground reference voltage associated with electronic display 18 , electronic device 0 , and/or subpixel 72 .

Returning to FIG. 13 , in response to the CSauto.zero signal 237 being enabled, the MAZ 234 is activated. When MAZ 234 is activated, electrical coupling is formed between the node of capacitor 232 and the source node of MS 226 so that the voltage value at the source node of MS 226 is the voltage value of Vg 245 . to increase in the same way as After period 286 , row driver 60 disables CSSauto.zero signal 237 , and MAZ 234 is inactive. In this state, subpixel 72 is programmed with electrical signals ready to transmit to LED 230 upon activation of MS 226 . That is, in this state, subpixel 72 is ready to transmit the driving current generated through its programmed signals in response to CSimage.data signal 247 enabling MS 226 . Once the source node of MS 226 is programmed to a voltage of Vg 245 , row driver 60 transmits a Vdata signal 242 equal to GND, and at the end of period 284 , MSEL 224 is deactivated. disable the CSselect signal 241, which causes Upon completion of the programming process, row driver 60 may enable and/or disable control signals to perform the emission process.

Referring to FIG. 14 , during the emission process, the row driver 60 may return the Vdata signal 242 to DVDD, may continue to disable the CSinitialization signal 243 , and continue the CSselect signal 241 . to disable, enable CSimage.data signal 247 for period 290, enable CSselect signal 280 for period 292, and continue CSreset signal 235 so you can disable it. As illustrated, the CSselect signal 280 is enabled concurrently with the CSimage.data signal 247 , but is disabled faster than the CSimage.data signal 247 . This is because the CSselect signal 280 acts to activate the switching element to provide a boost to the anode of the LED 230 of the subpixel 72 .

Turning to FIG. 13 , the voltage drive switching element (MVD) 285 of the subpixel 72 is activated in response to the enabling of the CSselect signal 280 causing the voltage drive 272 to be activated. In response to the MVD 285 being activated, the CSimage.data signal 247 enables the switching transistor (MS) 302 and MS 226 for the first transmitted CSimage.data signal 247 . , a reference voltage (Vreference) signal 300 is transmitted to the anode of the LED 230 . This causes the Vreference signal 300 to be transmitted at the anode of the LED 230 to enable or “boost” a smaller programmed value from the source of the MS 226 to cause light emission from the LED 230 . do. Boosting may continue for period 292 , where at the end of period 292 , row driver 60 disables CSselect signal 280 causing deactivation of MVD 285 and MS 302 . do.

Alternatively, the release process may continue for a period 290 , where the boost lasts for a shorter period, eg, period 292 . During the emission process, subpixel 72 is programmed to transmit a driving current through LED 230 in response to activation of MS 226 . As described above, the memory 78 of the subpixel 72 stores digital data and outputs digital data. With the hybrid drive described, the stored digital data is transmitted as digital data that is converted from memory 78 into control signals for controlling the emission of light from subpixel 72 with little overhead and no increase in power consumption. do. At the end of boosting, in some embodiments, subpixel 72 may be reset via enabling of CSreset signal 235 for a duration such as period 294 . Accordingly, the light emitted from the LED 230 may follow various emission schemes to convey the gray levels associated with the image, as described above in conjunction with FIGS. This is because the output binary data acts to modulate the light emitted through the LED 230 .

To help account for the effects of “boost” on the anode voltage of subpixel 72 , an exemplary CSimage.data signal 350 , a voltage signal 352 corresponding to the voltage at the anode of LED 230 , and a graph 348 illustrating a current signal 354 corresponding to the current through the LED 230 for a subpixel 72 that does not implement a hybrid drive is shown in FIG. 15 . It should be understood that the timing diagrams are exemplary and are not intended to be limiting.

In this simulation, the binary pulse width modulated emission scheme was tested by providing increasingly wider binary pulses as the CSimage.data signal 350 . The simulation results shown in graph 348 generally have two parts. The first portion 356 may correspond to a slower emission response time, and the second portion 358 may correspond to a normal emission response time, where the emission response time generally depends on the voltages applied to the LED 230 . refers to his relative responsiveness to It is also noteworthy that an LED, such as LED 230, operates to conduct based on the difference in voltages between the LED's anode and cathode. When the difference in voltage between the anode and cathode is greater than the threshold voltage, the LED operates to emit light according to the value of the current being transmitted through the LED. In graph 348 , current signal 354 may generally correspond to the emission of LED 230 , where the values of current signal 354 more closely match the state of CSimage.data signal 350 , the LED The emission response time of 230 is better. In graph 348, the effects of the effect of slow charging on the anode voltage of LED 230 are evident. During the first portion 356 , the current signal 354 appears to be less responsive to state changes of the CSimage.data signal 350 than the second portion 358 , which is the current signal during the second portion 358 . 354 and by the general matching of the amplitudes of the CSimage.data signal 350 and the lack of matching during the first portion 356 . Boosting the anode at the beginning of the emission period may reduce or eliminate the effect of slow charging of the anode voltage.

Proceeding to FIG. 16 , for comparison, an exemplary CSimage.data signal 350 , a voltage signal 374 corresponding to the voltage at the anode of the LED 230 , and a subpixel 72 with hybrid drive A graph 370 illustrating the current signal 376 corresponding to the current through the LED 230 is shown in FIG. 16 . It should be understood that the timing diagrams are exemplary and are not intended to be limiting. For example, although the CSimage.data signal 350 is shown as conforming to a binary pulse width modulated emission scheme, any suitable emission scheme may result in the same improvement in response as described below.

In this simulation similar to graph 348 , the binary pulse width modulated emission scheme was tested by providing increasingly wider binary pulses as the CSimage.data signal 350 . However, unlike graph 348 , graph 370 shows that current signal 376 responds to changes in CSimage.data signal 350 . This improved responsiveness is due, at least in part, to the addition of a voltage drive 272 to the subpixel 72 . Because the voltage drive 272 of the hybrid drive “boosting” the anode of the LED 230 , the smaller changes in voltages at the anode of the LED 230 are equal and /or can elicit a similar responsiveness. Accordingly, graph 370 shows the benefits and improvements to display technologies provided by implementing a hybrid drive at least within subpixel 72 .

As noted above, a display implementing memory-in-pixel techniques may implement various pixel circuitry embodiments and various memory circuitry embodiments to achieve the advantages previously described in this disclosure. An exemplary embodiment is a memory circuit that supports a binary pulse width emission scheme, wherein digital data stored in the memory circuit is output to a driver circuit to control the emission of light from the pixel. As a reminder, a binary pulse width emission scheme works in conjunction with a clocking signal, eg a bit-plane clock, to assign contribution weights to different portions of digital data transmitted from a memory circuit. In some embodiments, the clocking signal is used to clock the register to output the stored digital data from the memory circuit. However, in some embodiments, the system clock and/or row driver 60 may control the emission duration through the length of time that the emission-enabling signal is enabled.

To help explain the memory circuitry that facilitates controlling emission via an emission-enable signal, a subpixel 72 comprising memory circuitry 400A, analog driver circuitry 402, and light emitting circuitry 404 . ) is shown in FIG. 17 . It should be understood that subpixel 72 is exemplary and not intended to be limiting. For example, although memory circuitry 400A is shown as storing 12 bits of digital data, any suitable memory circuitry may be used, such as circuitry for storing more than or less than 12 bits of digital data. .

The memory circuitry 400A may include write enabling transistors (MWR) 406 , one or more inverter pairs 408 , and transmit select transistors (MSEL) 410 . The memory circuit unit 400A receives and stores digital data (DATA) 412 , for example, from the column driver 62 . Before the memory circuitry 400A stores the DATA 412 , the row driver 60 MWR to allow writing the image data to a memory (eg, inverter pairs 406 ) so that the memory can store the image data. A write enabled control signal (write_en) 414 may be enabled to activate the s 408 . Upon receiving DATA 412 , inverter pair 408 stores the value of DATA 412 . Using the memory circuitry 400A, in addition to bit-by-bit transmission in which each bit of DATA 412 is stored one bit at a time, all bits of DATA 412 simultaneously, or (e.g., write_en signal ( It should be emphasized that this allows parallel transmission of DATA 412 to be stored in respective inverter pairs 408 in the same write cycle (when 414 is enabled). The MSEL 410 is an enabled select control that is transmitted, for example, by the row driver 60 , which operates to activate the MSEL 410 of bits of memory targeted to be transmitted to the analog driver circuitry 402 . It is activated in response to a signal (Sel) 415 . In this way, MSEL 410A can be activated at the same time MSEL 410B is deactivated. Accordingly, the memory circuitry 400A is loaded with one or more bits of DATA 412 before the emission process begins, and the DATA 412 is easily read bit by bit by activation of the respective MSEL 410 .

At the beginning of an emission process, eg, an emission process as described in FIG. 14 , row driver 60 initially enables light emission based at least in part on activation of emission transistor (MEM) 419 . As a method, a precharge control signal (Precharge) 416 may be enabled. The MEM 419 may be activated in response to the row driver 60 enabling the emission control signal (emit_en) 420 . In some embodiments, row driver 60 emit_en to allow Vreference signal 246 to be transmitted to MS 226 to precharge or boost the anode of LED 230 prior to activation of MSEL 410 . The precharge signal 416 may be enabled simultaneously with the signal 420 . After precharging is complete, and during the emission process, the emit_en signal 420 may continue to be enabled by the row driver 60 . On the other hand, the row driver 60 disables the Precharge signal 416 after precharge, so that the stored DATA 412 at least partially controls the activation of the MEM 419 . In this manner, the stored DATA 412 transmitted from the inverter pair 408 may cause the MEM 419 to be activated in response to a logical value of the stored value (eg, “1” or “0”). Note that in some embodiments, the logic high value is equal to the Vreference signal 246 and the logic low value is equal to the Vreference signal 248 .

When the stored DATA 412 is transmitted from the memory circuitry 400A, the light emitting circuitry 404 receives the stored DATA 412 at the gate of the MS 226 . MS 226 is activated in response to the stored value of DATA 412 so that the current generated by analog driver circuitry 402 is transmitted to LED 230 to cause light emission. As long as the stored DATA 412 is applied as the CSimage.data signal 247 , the emission may continue. In this manner, light is emitted from the subpixel 72 following the initialization process, charging process, programming process, and emission process generally described in FIGS. 12-14 .

A further embodiment of a subpixel 72 having memory circuitry 400B and analog driver circuitry 442 including light emitting circuitry 404 is shown in FIG. 18 . It should be understood that subpixel 72 is exemplary and not intended to be limiting. For example, although memory circuitry 400B is shown as storing 16 bits of digital data, any suitable memory may be used, such as circuitry for storing more than or less than 16 bits of digital data. Also, although subpixel 72 is shown with LEDs 230 included in light emitting circuitry 404, any suitable light emitting circuitry 404 may be combined with the described memory-in-pixel techniques. .

Memory circuitry 400B is shown including one or more write enabling transistors (MWR) 406 , one or more inverter pairs 408 , and one or more select transistors (MSEL) 410 . DATA 412 is received, for example, from column driver 62 into memory circuitry 400B. To transmit the DATA 412 into the memory circuitry 400B, the row driver 60 generates a write_en signal 406 and an inverse signal of write_en (inverse write_en) 444 to enable bit-by-bit memory storage of the DATA 412 . ) can be enabled. For example, row driver 60 may enable storage of the last bit of DATA 412 in inverter pair 408B by activating MWR 406D and/or MWR 406C. Accordingly, the row driver 60 and the column driver 62 may operate to enable bit-by-bit transmission and storage of the DATA 412 to the memory circuitry 400B.

Upon storage of DATA 412 in inverter pairs 408 , memory circuitry 400B stores the value of DATA 412 until row driver 60 selects a respective bit for transmission. Prior to selecting the respective bit for transmission, row driver 60 precharges sense amplifier 440 via enabling of a precharge signal 416 . By precharging the sense amplifier 440 and subsequent analog driver circuitry 442 , the responsiveness of the subpixel 72 to transmitted electrical signals can be improved when compared to a subpixel 72 that is not precharged. As previously described, precharging subpixel 72 may make switching states easier and less demanding for circuitry (eg, by increasing circuitry responsiveness).

Upon completion of the precharge, the row driver 60 selects a bit for transmission to the analog driver circuitry 442 to cause an emission according to the stored DATA 412 . To send a bit to the analog driver circuitry 442 , the row driver may enable the Sel signal 415 to activate the MSEL 410 corresponding to the inverter pair 408 . For example, row driver 60 may use a Sel signal to activate MSEL 410A and MSEL 410B to cause transmission of DATA 412 stored in inverter pair 408A to be sent to analog driver circuitry 442 . (415A) can be enabled.

In some embodiments, DATA 412 is transmitted through sense amplifier 440 before being transmitted to analog driver circuitry 442 . Sense amplifier 440 may act to sense the logic state of DATA 412 and amplify the sensed logic state (eg, by increasing signal amplitude) to an interpretable logic state for adjacent circuitry. The interpretable logic state may be based, at least in part, on the threshold voltage of the MS 226 of the analog driver circuitry 442 . For example, a bit transmitted to node 446 is output at node 448 as having a larger voltage value, which is caused by transmission through sense amplifier 440 and the display system ( It is based, at least in part, on a voltage difference between Vreference signal 248 and Vreference signal 246 , representing, for example, any suitable voltage value common to display system 52 .

After the DATA 412 is amplified, the amplified DATA 412 is transmitted as a CSimage.data signal 247 to the analog driver circuitry 442 to activate or deactivate the MS 226 . For example, in some embodiments, MS 226 is deactivated in response to transmitted logic high DATA 412 (eg, transmitted as CSimage.data signal 247 ), and transmitted logic low DATA 412 . ) is activated in response to In this manner, the voltage value of the digital data transmitted as CSimage.data signal 247 corresponds to the bias voltage of MS 226, or a voltage value that operates MS 226 to change state. Upon activation of MS 226 , a driving current generated by analog driver circuitry 442 based at least in part on a voltage difference between Vreference signal 450 and Vreference signal 451 is transmitted via LED 230 . This allows the subpixel 72 to emit light. Thus, in the manner described, the DATA 412 stored in the memory circuitry 400B can drive light emission from the pixel circuitry (eg, subpixels, pixels).

To summarize the operation of the embodiment of the subpixel 72 of FIGS. 18 and 17 , an example of a process 461 for controlling the operation of the subpixel 72 coupled to the memory circuitry 400 is shown in FIG. 19 . described. Broadly, process 461 includes loading the current bit into memory (block 462), determining whether the current bit is the last bit to be loaded into memory (block 464), in response to not being a bit, loading the next current bit into memory (block 462), and in response to the current bit being the last bit, enabling a select signal to allow reading a bit from the memory (block 462). block 466), waiting for the bit to cause an emission in the pixel circuitry (block 468), and determining whether the bit is the last bit to be read from memory (block 471) . responsive to the bit being the last bit, completing the display cycle (block 472), and responsive to the bit being not the last bit, enabling a next select signal to allow reading of the next bit from memory. (Block 466). In some embodiments, process 461 uses processing circuitry, such as processing core complex 12 , to execute instructions stored in a tangible, non-transitory computer-readable medium, such as one or more storage devices 14 , at least It may be partially implemented. Additionally or alternatively, process 461 may be implemented at least in part based on circuit connections formed in display control circuitry, such as row driver 60 , column driver 62 , and/or timing controller 54 . have.

Accordingly, in some embodiments, the row driver 60 may load the current bit into the memory circuitry 400 (block 462). As described above, row driver 60 configures a respective switching element, such as MWR 406B or MWR 406D, to allow bit-by-bit loading of the current bit of DATA 412 into memory circuit 400. Optionally enable. Upon enabling of the MWR 406 , a bit corresponding to the current bit of DATA 412 is transmitted for storage, eg, in inverter pair 408 , where the value of the current bit indicates that the bit causes transmission. It is continuously inverted until it is selected for.

After loading the current bit into memory, row driver 60 may determine whether the current bit is the last bit (block 464). The last bit represents the last bit of the DATA 412 (eg, the last bit to be stored in the memory circuitry 400 ). Thus, checking whether the current bit is the last bit checks whether all of the DATA 412 has been sent from the column driver 62 for storage. Various techniques may be implemented to determine whether the current bit is the last bit, including, for example, maintaining a separate count to keep track of the current bit position relative to the last bit position.

In response to the current bit being not the last bit, the row driver 60 may load the next current bit into the memory circuitry 400 (block 462). As described above, the row driver 60 may then enable the respective switching element to enable the next bit of the DATA 412 to be transmitted bit by bit as the next current bit into the memory circuitry 400 . . Accordingly, process 461 is repeated until the last bit of DATA 412 is stored in memory circuitry 400 .

However, in response to the current bit being the last bit, row driver 60 may enable a select signal to transmit a bit from memory (block 466). When the current bit is the last bit, the row driver 60 determines that the loading of the target data to be stored in the memory circuitry 400 into the memory is complete - thus, at this time, the row driver 60 writes to the DATA 412 . The stored DATA 412 is transmitted bit-by-bit or bitwise to the analog driver circuitry 442 to cause light emission from the subpixel 72 at a corresponding level or luminosity. In some embodiments, row driver 60 transmits the stored bits in the order of least significant bit to most significant bit, although any suitable order for memory circuitry 400 and display system 52 may be used. To cause a transmission, the row driver 60 enables the Sel signal 415 corresponding to the target bit from the memory circuitry 400 for reading. Upon enabling of the Sel signal 415 , the target bit is transmitted to the sense amplifier 440 and/or analog driver circuitry 442 to cause light emission.

Row driver 60 may then wait a programmed period for the transmitted bit from memory to cause light to be emitted from subpixel 72 (block 468). While the row driver 60 waits, the bits stored in the inverter pair 408 are sent to the MS 226 . Upon activation of MS 226 , analog driver circuitry 442 allows driving current to be transmitted through LED 230 , causing light emission from subpixel 72 . As described above with respect to FIG. 8 , the bit-plane clock 106 may act to modulate the widths of the light emission to correspond to the significance of the bit from memory to the overall perceived gray level. The row driver 60 uses the bit-plane clock 106 , for example, via modulating the overall emission of the subpixel 72 (eg, via enabling the emit_en signal 420 ), and /or via modulating a period during which a bit is selected to be transmitted from memory circuitry 400 (eg, enabling MSEL 410 for a period corresponding to the significance of the bit in Sel signal 415 to activate it) ) to modulate the light emission from the subpixel 72 . Note that in some embodiments, the row driver 60 does not wait and continues to determine whether the bit read from the memory circuitry 400 was the last bit of the stored DATA 412 .

After reading the bit, the row driver 60 may determine whether that bit was the last bit of the stored DATA 412 (block 471). Row driver 60 determines whether the last bit has been read and/or sent to analog driver circuitry 442 . Row driver 60 may, in various ways, increment a counter that increments in conjunction with enabling of Sel signal 415 to indicate when row driver 60 has read an expected number of bits from memory circuitry 400 . You can manage these decisions by maintaining

If the bit is the last bit, the row driver 60 may complete the display cycle (block 427). The display cycle may include the entire process 461 , upon reaching block 427 , the row driver 60 emitting light at a gray level corresponding to the DATA 412 . Upon completion of the display cycle, the row driver 60 may be ready to accept new DATA 412 corresponding to the same or a different gray level for emission.

However, in response to the bit being not the last bit, row driver 60 may enable a next select signal to allow reading of the next current bit from memory (block 466). The row driver 60 may manage the enabling of the next select signal in various ways - eg, maintaining a separate count to keep track of the currently transmitted bit position relative to the last transmitted bit position. In any case, the row driver 60 determines the Sel signal 415 to enable (eg, the Sel signal 415 corresponding to the next bit to be transmitted from the memory circuitry 400 ). When the row driver 60 determines which Sel signal 415 to enable, the row driver 60 applies the Sel signal 415 which causes activation of the MSEL 410 corresponding to the target bit for transmission. enable Row driver 60 may repeat transmitting bits of stored DATA 412 until the last bit is reached. Upon reaching the last bit, row driver 60 may complete the emission cycle and prepare for the next emission cycle (block 427).

18 and 19, the described embodiments of subpixel 72 have analog driver circuitry 442 with a global anode. A further embodiment of subpixel 72 may have analog driver circuitry 442 with a global cathode.

A subpixel having a global cathode including a memory circuit portion 400C, and an analog driver circuit portion 442 having a light emitting circuit portion 404 is shown in FIG. It should be understood that subpixel 72 is exemplary and not intended to be limiting. For example, although memory circuitry 400C is shown as storing 16 bits of digital data via bit-by-bit transmission of data, circuitry for allowing parallel transmission of data and/or more or less than 16 bits Any suitable memory circuitry may be used, such as circuitry for storing the digital data.

In the illustrated embodiment, the cathode of LED 230 is coupled to a reference voltage (Vreference) signal 470, and the anode of LED 230 is MS 226A, MS 226B, MS 276, and It is coupled via MS 278 to a reference voltage (Vreference) signal 473 . As described above, after DATA 412 is stored in memory circuitry 400C, and in some embodiments, after precharging circuitry via Precharge signals 416, row driver 60 emits light. may enable the emit_en signal 420 to cause Upon activation of MEM 480 and MEM 482 , bits of stored DATA 412 are transmitted through sense amplifier 440 , and the amplified bits are transmitted to MEM 480 , while stored DATA 412 . An inverted version of the bits of is sent to MEM 482 without amplification. The inverted bit and the amplified bit are used as control signals to activate the MS 226A, 226B, effectively acting like the CSimage.data signal 247 from previous discussions. Upon activation of MS 226A and MS 226B, analog driver circuitry 442 responds to the voltage difference between Vreference signal 473 and Vreference signal 470 to cause light emission transmitted via LED 230. generate a driving current based, at least in part, on the driving current.

In a manner similar to the global anode embodiment, the global cathode subpixel 72 may generate different gray levels through following a binary pulse width modulation scheme. The binary pulse width modulation scheme may partially use a bit-plane clock to control the control signals output from the row driver 60 . In this way, the emit_en signal 420 may be enabled for a shorter period of time for bits of less significance to the perceived gray level (eg, the least significant bit of DATA 412 ), and to the perceived gray level. may be enabled for a longer period of time for bits of greater significance (eg, the most significant bit of DATA 412 ). In some embodiments, Sel signal 415 may be modulated to cause light to be emitted from subpixel 72 according to different gray levels.

As illustrated in FIG. 9 , using memory-in-pixel techniques and a comparator may enable a row driver to generate a single pulse width modulated emission scheme. Accordingly, one embodiment of a subpixel 72 including a comparator 490 , a memory circuitry 491 , and a memory circuitry 492 is shown in FIG. 21 . It should be understood that subpixel 72 is exemplary and not intended to be limiting. For example, while memory circuitry 492 is shown coupled to LED driver circuitry and light emitting circuitry of subpixel 72, memory circuitry 492 is coupled to any suitable light emitting circuitry and/or driving circuitry. can be

In the illustrated subpixel 72 , DATA 412 of size n bits is received in memory circuitry 491 following a process similar to that described above, i.e. row driver 60 sends DATA to inverter pairs 496 . act to enable the write_en signal 494 to cause the transmission of 412 . In some embodiments, row driver 60 simultaneously enables write_en signals 494 , thereby causing parallel transmission of all bits associated with DATA 412 into inverter pairs 496 into column driver 62 . ) works in conjunction with Additionally or alternatively, row driver 60 may cause bit-by-bit transmission of bits associated with DATA 412 through selectively enabling write_en signals 494 - for example, DATA 412 ) loading bits into inverter pair 496A by selectively enabling write_en signal 494A to cause transmission of the first bit of the .

Once the DATA 412 is stored in the inverter pairs 496, the comparator 490 uses the bits of the stored DATA 412 and the bits transmitted from the counting circuitry (eg, the counter 130) to generate two of the bits. Comparison is performed between sets of . As a reminder, in a single pulse width modulated emission scheme, a counting circuitry, such as a counter 130, increments up to a maximum gray level on the rising edge of a clocking signal, such as a gray level clock 134, where the light emission is from subpixel 72, until it counts to a number equal to and/or exceeding the number represented by stored DATA 412 . In this manner, comparator 490 performs compression of all bits of DATA 412 into a single bit indicating whether DATA 412 is equal to the count transmitted from the counting circuitry. Thus, comparator 490 performs bitwise XNOR compression to a single bit with one embodiment of memory circuitry 491 and memory circuitry 492, where the output from comparator 490 is not all bits matched. One logical low (eg, “0”) value. If all bits match, comparator 490 outputs a logic high value. The output from comparator 490 is stored in memory circuitry 492, where its value causes emission of the stored output of comparator 490 to the LED driver and light emitting circuitry to drive light emission, as previously described. is held in inverter pair 498 until row driver 60 enables emit_en signal 420 to do so. CNT_b[n:0] corresponds to the inverse of CNT[n:0] and is used to compare the inverted output from inverter pairs 496 to the inverted bit of CNT[n:0].

It should be understood that, in some embodiments, the counting circuitry may decrement, the comparator 490 may output a logic low value if all bits match, or any combination thereof. In other words, various effective embodiments may apply the described memory-in-pixel techniques. Furthermore, an optional transistor 500 is included in subpixel 72 to provide power saving benefits from precharging the common output (eg, MTCH) node of comparator 490 , whereby circuitry is included in comparator 490 . ) can be made more responsive to changes in the output from

To detail the operation of the subpixel 72 shown in FIG. 21 , a process 520 for operating the subpixel 72 having a comparator 490 and memory circuitry 491 is described in FIG. 22 . Broadly, process 520 includes initializing the memory circuitry (block 522), precharging the common output from the comparator (block 524), and incrementing the count of the counting circuitry (block 526). )), causing the emission based on the automatic comparator determination stored in the memory circuitry (block 528), and determining whether the counting circuitry has reached the maximum count (block 530). In response to the counting circuitry reaching the maximum count, preparing the next image (block 532), and in response to the counting circuitry not reaching the maximum count, precharging the common output from the comparator (block 532). block 524). In some embodiments, process 520 uses processing circuitry, such as processing core complex 12 , to execute at least instructions stored on a tangible, non-transitory computer-readable medium, such as one or more storage devices 14 , at least. It can be done partially. Additionally or alternatively, process 461 may be implemented at least in part based on circuit connections formed in display control circuitry, such as row driver 60 , column driver 62 , and/or timing controller 54 . have.

Accordingly, in some embodiments, row driver 60 may initialize memory circuitry 492 (block 522). To initialize the memory circuitry 492 , the row driver 60 may enable a control signal to force the node of the memory circuitry 492 to a low voltage value. For example, referring to FIG. 21 , in order to initialize the memory circuit unit 492 , the row driver applies an S reset (S_rst) signal to reset a voltage value of a node (eg, S node) of the memory circuit unit 492 . can be enabled Initializing the node of memory circuitry 492 causes the comparator to output a logic high to stop emitting light from subpixel 72 (eg, in response to reaching the gray level stored in memory by the counting circuitry). until the light emitting circuit portion is emitted. In other words, for one or more subpixels 72 implementing comparator 490 , subpixels 72 may start emitting light together simultaneously, but may stop emitting light at different times - where Each duration of light emission corresponds to a target gray level for a respective subpixel 72 .

Row driver 60 may precharge comparator 490 after initializing memory circuitry 492 (block 524). To precharge the comparator 490 , the row driver 60 enables the precharge signal to cause the voltage to boost the circuitry so that the subpixel 72 responds to changes in the output from the comparator 490 . You can be more responsive. To precharge comparator 490 , row driver 60 generates an inverse emit_en signal such that a voltage (eg, DVDD) is sent to comparator 490 (eg, the MTCH node of comparator 490 ) to boost circuitry. A “Precharge” signal that works in conjunction with 420 may be enabled. Although specific circuitry is shown that operates to precharge the comparator 490 in response to the precharge signal, it should be understood that a variety of effective circuitry arrangements may be used to facilitate precharging the comparator 490 .

After precharging comparator 490, row driver 60 may increment the count of the counting circuitry (block 526). Row driver 60 may increment the counting circuitry in response to, for example, a clocking signal timing the increment. After incrementing the counting circuitry, the subpixel 72 automatically determines whether the count of the counting circuitry equals or exceeds the value represented by the stored DATA 412 . This occurs because the individual bits of the count and the individual bits of DATA 412 are each sent to a comparator 490 where the comparator 490 returns a logic high value, or even one, if all of the bits match. If the bits of do not match, a logic low value is output. The output of comparator 490 is sent for storage or storage in inverter pair 498 of memory circuitry 492 , where the value is determined by row driver 60 to emit through enabling of emit_en signal 420 . stored until enabled.

After incrementing the count of the counting circuitry, the row driver 60 causes an emission based on the output from the determination of the comparator 490 stored in the memory circuitry 492 (block 528). Row driver 60 causes emission through enabling emit_en signal 420 . As described above, upon enabling of the emit_en signal 420 , its value is transmitted from the inverter pair 498 to the LED driver and light emitting circuitry of the subpixel, for example the LED 230 or any suitable It causes light emission from the light emitting circuit part. The value transmitted from the memory circuitry 492 may activate or deactivate the light emitting circuitry responsible for causing light emission and the switching circuitry of the LED driver.

When row driver 60 causes an emission based on the output from comparator 490, the row driver may determine whether the count of the counting circuitry is the maximum count (block 530). The counting circuitry may count from a minimum value to a maximum value, for example from 0 to 255. Accordingly, when the maximum value or maximum count is reached by the counting circuitry, the row driver 60 may perform certain processing steps to restart the count.

In response to the maximum count not being reached, row driver 60 restarts process 520 by precharging the common output from comparator 490 (block 524). Thus, therefrom, process 520, as described, comparator 490, where row driver 60 indicates whether stored DATA 412 equals or exceeds the count represented by the counting circuitry. Continue to send another output from

However, in response to reaching the maximum count, row driver 60 prepares the next image (block 532). To this end, the row driver 60 prepares to receive new DATA 412 corresponding to the target gray level of the subpixel 72 used to convey the next image. Different embodiments of subpixels 72 may prepare in various ways. For example, subpixel 72 from FIG. 21 may enable one or more write_en signals 494 to facilitate loading of new DATA 412 into memory circuitry 491 . In some embodiments, preparing the next image includes, at block 526, incrementing to zero and restarting the counting of the counting circuitry so that the counting can restart. In embodiments where the counting circuitry is a series of flip-flops coupled together to form a counter, such as counter 130, the counting circuitry automatically self-zeros based on digital logic properties of the circuitry. It should be understood that restarting the counting circuitry to zero is unnecessary because it restarts with .

Several emission schemes, such as binary pulse width modulation and single pulse width modulation, provide general theory of operation, specific exemplary memory circuitry, and specific exemplary pixel circuitry. A further emission scheme can be performed by using memory-in-pixel techniques - a binary pulse width modulation reordering emission scheme.

For illustrative purposes, memory circuitry 560 having one or more MWRs 406 , one or more MSELs 410 , inverter pairs 408 , inverter pair 498 , and a switch/reset (SR) latch 562 . ) is shown in FIG. 23 . Row driver 60 illuminates the pixel as CSimage.data signal 247, for example, by enabling control signals to allow column driver 62 to store DATA 412 in memory circuitry 560 . It may operate in concert with the column driver 62 to provide the DATA 412 to the memory circuitry 560 for storage prior to transmission to the part.

Alternatively, the row driver 60 may operate the memory circuitry 560 to simultaneously release multiple bits of data from the memory to the same node, for example, the node BP_pre. In this way, the row driver 60 can modulate the emission time to rearrange the bit order represented by the DATA 412 . For example, if DATA 412 is equal to 0010, row driver 60 causes emission to follow 1-0-0-0 so that the emission time for “1” occurs first, and the emission time for “00” The memory circuitry 560 may be operated so that it is not released after a period of time. This rearrangement may improve the appearance of visual artifacts on the electronic display 18 while still allowing a gray level equal to “0010” to be emitted from the subpixel.

To further elaborate on the reordering associated with the binary pulse width modulation reordering emission scheme, FIG. 24A shows a bit-plane graph 580, FIG. 24B shows an error graph 588, and FIG. 24C shows a bit-plane graph ( 582 , FIG. 24D shows an error graph 590 , FIG. 24E shows a bit-plane graph 584 , FIG. 24F shows an error graph 592 , and FIG. 24G shows a bit-plane graph A graph 586 is shown, and FIG. 24H shows an error graph 594 , where FIG. 24 as a whole illustrates the reordering effects on total error. 24A-24H show simulated electronic display 18 implementing a binary pulse width modulated emission scheme with and without reordering to a 6-bit binary number representing a target gray level for subpixels and/or pixels. express performance.

Bit-plane graph 580 shows the original sequence of a binary pulse width modulated emission scheme without any rearrangement to the gray levels represented by 6 bits, where all bit-plane graphs 580, 582 , 584 and 586 have a bright portion 595 corresponding to light emission and a dark portion 596 corresponding to no light emission. The bit-plane graph 580 is caused by the row driver 60 operating the subpixel 72 to emit light via binary pulse width modulation (e.g., the LED 230 is driven to emit light in response to the binary representations of the most significant bits, causing 0101 to emit light according to 1-0-1-0). Each square of the bit-plane graph has a minimum gray level 598 (corresponding to all dark portions 596 for all bit-plane values) to a maximum gray level 599 (all bright portions for all bit-plane values). It shows the relative significance of a particular bit at a particular location shown relative to the bit-plane used to cause a particular gray level spanning a range of portions 595). For example, block 597 representing the most significant bit of bit-plane graph 580 is logic high for gray levels of 32-64 and logic low for gray levels of 0-32. This is consistent with the 6-bit binary representations of these decimal values. Also, all bit planes are logic low and a gray level of 0, and all are logic high at a gray level of 64. These binary states correspond to numerical representations of a gray level in binary, eg to make a gray level of zero, all bit-planes are expected to be logical low or 000000. Thus, bit-plane graphs can visually represent the relative importance of a bit to representing gray levels (eg, in bit-plane graph 580 , the state of the sixth bit converts the gray level value to the first bit or change in a more dramatic way than the least significant bit).

When subpixels 72 are operated to emit light according to a binary pulse width modulated emission scheme without realignment, the total error counts are high as shown in bit-plane graph 580 and error graph 588 (e.g., , 322). It may be desirable to lower the total error counts through reordering, since errors occur on the electronic screen of the electronic display 18 , for example dynamic false contouring, color breakup, and This is because/or appears as flickering of light emitted from one or more pixels.

As can be seen in bit-plane graph 582 and bit-plane graph 584, as the reordering occurs, and as the most significant bits are reordered to emit first to cause gray levels of the bit-plane graphs, The bit-plane pattern tends to look like the ideal bit-plane shown in the bit-plane graph 586 . The error also decreases as reordering occurs, as shown in error graph 588 , error graph 590 , error graph 592 , and error graph 594 . Perceived image quality can be improved from reducing error counts through realignment of the bit-planes. The ideal case (e.g., bit-plane graph 586) is such that, through increasing the number of reorders, the bit-plane graph 586 tends to a gradual bit-plane change as the gray level increases, and how the total error tends to be for a certain number of total states represented by the bit-plane (e.g., 6 bits correspond to 64 total states, the following relationship follows: number of states = 2 ⁿ , where n is the number of bits).

Referring back to FIG. 23 for details on how row driver 60 operates memory circuitry 560 to perform a binary pulse width modulation reordering emission scheme, row driver 60 reorders from memory circuitry 560 . Enables and/or disables control signals to coordinate the transmission of the DATA 412 . For example, row driver 60 may selectively enable and/or disable Sel signals 415 to transmit respective bits from inverter pairs 408 . In some embodiments, row driver 60 selectively enables Sel signals 415 in response to bit-plane clock 106 defining emission periods for bit positions of DATA 412 . can be enabled and/or disabled.

At a high level, and for the ideal realignment case, row driver 60 writes DATA 412 to CSimage. The memory circuitry 560 may be operated to transmit the data signal 247 from the most significant bit to the least significant bit. When the bit of DATA 412 is a logic low, the row driver 60 effectively operates the memory circuitry 560 to skip the logic low emission period and to emit light according to the next logic high emission period. Upon transmission of all logic high bits represented in DATA 412 , row driver 60 pauses for a duration equal to the total emission period of the logic rows, or in some embodiments, releases new DATA( 412) is processed. For example, referring to emission reordering example 600, if DATA 412 is equal to 1111, CSimage.data signal 247 is memory circuitry 560 as “1111” having a total emission period equal to “1111”. ) on the other hand, when the DATA 412 is equal to “0011”, the CSimage.data signal 247 transmitted from the memory circuit unit 560 is equal to “1100”, where the respective bits are equal to “0011” and With the same emission period, and when DATA 412 is equal to “0100”, data is written into “1000” for transmission as CSimage.data signal 247 . Ultimately, a single pulse width of the light emission is generated from the data corresponding to the binary pulse width modulated emission scheme.

During reordering, the row driver 60 may operate the memory circuitry 560 to either release the bit or ignore the bit if the bit stored in the memory is zero. Row driver 60 may operate in several different modes of operation based on the number of reorderings that row driver 60 wishes to perform. For example, in the case of one reordering, the row driver 60 may have two modes of operation, whereas in the case of three reorderings, the row driver 60 may have eight modes of operation.

The row driver 60 may determine in which mode of operation to operate based at least in part on a comparison of the current emission time and the quadrant time. The row driver 60 may compare the current time to predefined time frames defining a mode of operation (eg, the first mode of operation corresponds to an emission of a first length). These different modes of operation may define how the row driver 60 prioritizes image data to cause emission. For example, for one reordering example, the row driver 60 in the first mode of operation operates the bit-plane (eg, switch 104 ) when the first most significant bit is equal to the binary state “0”. may allow light emission according to the bit-plane (meaning how a pixel is generally operated to emit light in response to binary states of the image data used to ', the row driver 60 may allow the light emission regardless of the light emission defined by the bit-plane to cause the bit-plane realignment to occur.

For each mode of operation, regardless of the number of reorderings, the row driver 60 may perform similar control actions. The row driver 60 in each mode of operation, through each bit of DATA 412, starts with the least significant bit (e.g., DATA[0] 412A) and the most significant bit (e.g., DATA[n-1] (412) for one reordering, DATA[n-2] (412)) for two reorderings, and repeats the process of proceeding to the previous bit. For each iteration, starting with DATA[0], row driver 60 resets S node, precharges memory circuitry 560, and transfers DATA[n] 412B into SR latch 562. Enable the Sel signal 415B to allow transmission of bits, and enable the Sel signal 415 corresponding to the current repetition of the least significant bit, so that the current repetition of the most significant bit or least significant bit is transmitted to the CSimage.data signal 247 to be sent as

The row driver 60 may operate the memory circuit unit 560 differently based on an operation mode. For example, when row driver 60 is operating in the first mode of operation, row driver 60 further enables enabling of Sel signal 415B and DATA[n]( Precharges the memory circuitry 560 between allowing transmission of the bits of 412B and enables the Sel signal 415 corresponding to the current repetition of the least significant bit. Additionally or alternatively, for modes of operation other than the first mode of operation, the row driver enables the Sel signal 415B and other Sel signals 415 corresponding to a number of most significant bits equal to the number of reorderings. (e.g., Sel signals 415 for DATA[n] 412B and for DATA[n-1] 412 for two reorderings, DATA[n] 412B for three reorderings Enable Sel signals 415 for , for DATA[n-1] 412, and for DATA[n-2] 412) and corresponding to the current repetition of the least significant bit (e.g., DATA[0](412A) for 1st iteration, DATA[1](412) for 2nd iteration, DATA[2](412) for 3rd iteration) Enable Sel signal 415 ends by doing

Thus, for the example of two reorderings, the row driver 60 can operate in four different modes of operation for the stored DATA 412 having six bits. For the first mode of operation (e.g., corresponding to 1/4 of the gray level values between 0 and the gray level threshold of 16), the row driver 60, in addition to the SET signal for each bit of DATA 412, , reset the S node, precharge (e.g., enable Precharge signal 416), enable Sel[6] 415, enable SET signal 602, precharge, Enable Sel[5] 415, enable SET signal 602, precharge, and enable Sel[n] 415 (e.g., for first iteration n=0, Sel [0] (415A is enabled), increment the value of n from 0 at each iteration until DATA[4] (412) is reached. For the second mode of operation (eg corresponding to 2/4 of the gray level values between the gray level threshold of 16 and the gray level threshold of 32 being twice the gray level threshold), the row driver 60 , In addition to the SET signal for , reset the S node, precharge, enable Sel[6](415B), enable the SET signal 602, precharge, and Sel[5](415) can be enabled, and Sel[n]415, incrementing the value of n from 0 at each iteration until DATA[4] 412 is reached. For a third mode of operation (eg, corresponding to three-quarters of gray level values between 32 twice the gray level threshold and 48 three times the gray level threshold), the row driver 60 , each of the DATA 412 In addition to the SET signal for bits of enable, precharge, enable Sel[6](415B), enable Sel[n](415), from 0 to n at each iteration until DATA[4](412) is reached can be incremented. For the fourth mode of operation (eg, corresponding to 4/4 of the gray level values between 48 which is 3 times the gray level threshold and 64 which is 4 times the gray level threshold), the row driver 60 , each of the DATA 412 In addition to the SET signal for the bit of , reset the S node, precharge, enable Sel[6](415B), enable Sel[5](415), and Sel[n](415) can be enabled to increment the value of n at each iteration until DATA[4] 412 is reached.

To illustrate otherwise, FIG. 25 includes a bit-plane graph 604 representing a binary pulse width modulated emission scheme in which two reorders are implemented with three color channels. As shown, the bit-plane graph 582 corresponding to the two reorderings is represented in the bit-plane graph 604 over time and as three color channels of one pixel 70 . The row driver 60 may time the emissions with respect to the quadrants, where for two realignment cases, one quadrant 606 may correspond approximately to one quarter of the emission time (eg, 1/1/2). 2 ⁿ , where n is equal to the number of reorderings). These quadrants 606 may be similar to the modes of operation described above. As time increases, the electronic display 18 may change the emission priority - in other words, giving the two most significant bits of the image data for a particular pixel 70 higher during emission than given to the other bits. Emission priority may be given. The electronic display 18, in some embodiments, manages the emission based on a comparison of the most significant bits with the value represented by the counter, such that the binary state "00 on the edge (eg, rising or falling edge) of the clocking signal. increment up from " to binary state "11" (eg, where one period of the clocking signal corresponds to the duration of one quadrant). Thus, in these embodiments, with respect to subpixels 72 of pixel 70 , for first quadrant 606A, output logic if the two most significant bits (MSB) are equal to binary state “00”. As generally summarized in overview 610 , subpixel 72 may emit according to bit-plane 608 (eg, according to binary data as stored in memory 78 being represented), but 2 If the most significant bits are equal to the binary states "11", "01", and/or "10", then the subpixel is the duration of the emission period of the channel of the first quadrant 606 (eg, the first color channel (corresponding to time duration 609).

To summarize the other three quadrants, subpixel 72 emits light according to bit-plane 608 when, while operating in second quadrant 606B, the two most significant bits are equal to binary state “01”. It emits light, emitting light when the two most significant bits are equal to binary state “10” and/or “11”, and not emitting light when two most significant bits are equal to binary state “00”. During operation in the third quadrant 606C, the subpixel 72 emits light according to the bit-plane 608 when the most significant bits are equal to the binary state "10", and the two most significant bits are equal to "11". Emit light if equal to ", and do not emit light if the two most significant bits are equal to "00" and/or "01". Further, while operating in the fourth quadrant 606D, the subpixel 72 emits light according to the bit-plane 608 if the two most significant bits are equal to the binary state "11", No light is emitted if the most significant bits are equal to "00", "01", and/or "10". Thus, in this manner, subpixel 72 is operated to realign the light emission corresponding to the two most significant bits, such that the light emission of the two most significant bits occurs before light emission according to bit-plane 608 .

To help present content, FIG. 26 shows a timing diagram of a binary pulse width modulated emission scheme in which two reorders are implemented with three color channels. This timing diagram shows the relationship between the loading of digital data into memory 78 substantially concurrently with other actions performed by row driver 60 . For example, data loading of the most significant bits of the green channel occurs at time 612 of emission of the least significant bits of the red channel. Comparing FIG. 26 with FIG. 25 , as just described for the fourth quadrant 606D, the row driver 60 indicates that the subpixel 72 is represented by data stored in and transmitted from the memory 78 . Allows to emit light according to the bit-plane being As shown in the timing diagram, the total emission duration for all three color channels is approximately equal to three times the channel-specific emission duration.

A binary pulse comprising an SR latch 562 coupled to memory circuitry 560 , MWRs 406 , MSELs 410 , inverter pairs 408 , inverter pair 498 , analog driver circuitry 561 . An exemplary embodiment of a pixel operated by row driver 60 to follow a width modulation reordering emission scheme is shown in FIG. This figure shows, for example, that various pixel circuitry and analog driving circuitry may be used with memory circuitry 560 and memory-in-pixel techniques.

It is intended to be illustrative and not limiting. 27 shows an example of a memory circuitry 560 as applied to a digital mirror display (DMD).

In general, the illustrated memory circuitry 560 operates to receive DATA 412 corresponding to the target gray level for the color channel of the pixel 70 corresponding to the memory circuitry 560 . As shown, the memory circuitry 560 includes different color groups in memory for each color channel. In this embodiment, pixel 70 has memory circuitry for each color channel instead of unique subpixels 72 for each color channel (eg, R-G-B). The row driver 60 may operate the color channels through enabling the color group (CG) signal 564 . Upon activation of the CG transistor (MCG) 565 , the stored DATA 412 is transmitted towards the analog driver circuit portion 561 . The row driver 60 may only allow one color channel to be transmitted at a time. Thus, the illustrated memory circuitry 560 facilitates color sequential output from individual memory circuitry to a shared output circuitry coupled to the DMD electrode.

The row driver 60 may operate the illustrated memory circuitry 560 similar to the memory circuitry 560 of FIG. 23 . Thus, for one example of two reorderings, row driver 60 may operate in four different modes of operation, where the mode of operation is selected based on the gray level value of DATA 412 . After writing the DATA 412 to the inverter pairs 408 , the row driver 60 transfers the stored DATA 412 to the SR latch 562 at a time to drive the DMD electrode through the analog driver circuitry 561 . The memory circuit unit 560 is operated to transmit one bit at a time. Row driver 60 drives memory circuitry 560 in different modes of operation to selectively enable and/or disable CG signals 564 (eg, corresponding to bit-plane 7 ). enable 564B to transmit red data), and reorder DATA 412 to generate a single pulse width modulated signal from the binary pulse width modulated emission data.

For example, and as described above, for a first mode of operation (eg, corresponding to gray levels between zero and a gray level threshold), the row driver 60 resets the S node, precharges, Sel Enable [n] 415B, enable SET signal 602, precharge, enable Sel[n-1] 415, enable SET signal 602, precharge Charge and enable Sel[0] (415A). The row driver repeats the first mode of operation for each bit of DATA 412, from the first bit to DATA[0] until DATA[n-2] (where 2 corresponds to the number of reorderings) is reached. ](412A) can be incremented. The row driver 60 may operate as described in the discussions with respect to FIG. 23 while in the second, third, and fourth modes of operation.

27, memory circuitry 654, color channel select transistors 656, inverter pair 498, analog driver circuitry, operated by row driver 60 to follow a single pulse width modulated emission scheme. An exemplary embodiment of a pixel 650 including 561 , and a comparator 490 electrically coupled to light emitting circuitry (not shown) is shown in FIG. 28 . This figure is illustrative and not restrictive, for example, any suitable pixel circuitry may include memory circuitry and memory-in-pixel techniques, such as additional and and/or may be used with any combination of alternative embodiments. 28 is included to show an example of a pixel 650 as applied to a liquid crystal display (LCD), wherein the operation of memory circuitry 654 and comparator 490 generally follows the process shown and described in FIG. 22 . can

In general, the pixel 650 is managed by a row driver 60 that enables the write_en signal 414 to allow the writing of bits of DATA 412 into memory, e.g., inverter pairs 408 . DATA 412 is received during the data write process. During the data writing process, the pixel 650 transmits gray level digital data for a red color channel (DATA) 412R, gray level digital data for a green color channel (DATA) 412G, and a blue color channel (DATA). Receive gray level digital data for 412B, where pixel 650 receives DATA 412 in serial data transmissions to each of memory circuitry 654 and/or in parallel data transmissions. When the DATA 412 is written into the memory of the pixel 650 , the comparator 490 , with the DATA 412 from the memory, counting circuitry, such as the counter 130 , and/or the transmitted data from any suitable counting method. Perform automatic comparison of counts. Using the same methods described in comparator 490 from FIG. 21 , comparator 490 is generated when DATA 412 and count 658 from the counting circuitry are equal (e.g., matches all bits). 1", or "0" if not equal (eg, one or more bits do not match). Row driver 60 sends a CG signal 564 to respective transistors of color channel select transistors 656, such as a color channel for color sequential emission, eg, red for emission through a shared output stage; Enables either the green or blue color channels. When the row driver 60 enables transmission from the color channel, the MTCH bit is sent to the memory circuitry 492 for storage. Row driver 60 may enable the EMIT signal to allow light emission according to the stored MTCH bit, as described above. Additionally or alternatively, row driver 60 may enable a GHOST signal that does not cause emission to occur, at least in part, regardless of the stored MTCH bits in memory circuitry 492 . To emit light, row driver 60 enables the EMT signal, causing the stored MTCH bits to be transmitted to analog driver circuitry 561 coupled to the high and low reference voltages. The stored MTCH bit is transmitted to analog driver circuitry 561 that activates and/or deactivates MS 566 coupled to the LC electrode in response to reference voltages (eg, MS 566A, MS 566B). do. The reference voltages, although shown as 5 [V] and VSS, may be any suitable voltage used to drive the LC electrode upon activation of MS 566 .

In accordance with the structure described above, the pixel 650 may be operated to emit according to a single pulse width modulated emission scheme. Different embodiments may be operated by the row driver 60 to emit according to different emission schemes. For example, the color channel of pixel 650 may generally operate according to a binary pulse width modulated emission scheme when the digital data transmitted to pixel 650 changes and comparator 490 is removed.

As discussed throughout this disclosure, it should be understood that memory-in-pixel techniques are valid for various embodiments and display technologies. It should also be understood that for each reference voltage discussed or disclosed in the figures, additional or alternative reference voltages may be used. Additionally or alternatively, although described as reducing or eliminating reliance on using a frame buffer, it is noted that memory-in-pixel techniques may, in some embodiments, be used in conjunction with a frame buffer. Moreover, although memory circuitry has been described as storing 6 bits, 12 bits, 8 bits, and/or 16 bits, any suitable memory structure may be used to store any suitable number of bits. You have to understand that you can.

As briefly discussed in FIG. 21 , a memory-in-pixel technique to allow moving memory 78 into a smart buffer as opposed to, or in addition to, including memory 78 within subpixel 72 itself. Some adjustments to these may be applied in general. 29 shows this generally in terms of a memory-in-pixel architecture electronic display 700 and a smart buffer architecture electronic display 702 . Memory-in-pixel architecture The electronic display 700, as shown, includes a memory 78 within each subpixel 72 located in an active area 704 of the electronic display 18, where the active Region 704 includes both light emitting components of the electronic display and communication couplings to support data transmission to the light emitting components. Memory-in-pixel architecture In electronic display 700 , digital data is transmitted from memory 708 to each respective subpixel 72 for localized buffering in memory 78 . In some embodiments, digital data is transmitted from memory 708 to source region 710 prior to transmission into memory 78 for localized buffering (eg, buffering within subpixel 72 ). However, memory substantially similar to memory 78 is included within smart buffer 712 of smart buffer architecture electronic display 702 , while still eliminating or at least reducing reliance on the frame buffer, from active area 704 to memory. (78) can be further removed. By moving the memory 78 into the smart buffer 712 , the row driver 60 causes the input latches ( 714 ) and output latch 716 . Here, the smart buffer 712 may represent any suitable buffer memory disposed within the integrated circuit of the electronic display 18 but outside the active area of the electronic display 18 .

30 shows an example of a smart buffer embodiment of memory 78 circuitry including memory circuitry 750 , comparator 752 , memory circuitry 754 , and output inverter 756 . This circuit functions similarly to the memory circuitry shown in FIG. 21 , where the smart buffer of FIG. 30 is a write_en control that allows the writing of digital data to the memory circuitry 750 (eg, an inverter pair). Receive digital data in response to signal 757 . Accordingly, the general operation of memory circuitry 754 and comparator 752 may generally follow the process shown and described in FIG. 22 . The smart buffer of FIG. 30 may have memory 78 circuitry for each subpixel 72 of active area 704 . The digital data value may be stored in the memory circuitry 750 until a new value of the digital data is written into the smart buffer for a particular subpixel 72 .

When digital data is transmitted into the memory circuitry 750, the comparator 752 determines whether all bits of the digital data match the output (CNT/CNT_b) from the counting circuitry. Similar to the above-described embodiments, the counting circuit unit counts to allow light emission according to the gray level represented by the digital data. The comparator may output a logical 0 "0" as the MTCH bit, until the digital data matches the count - then the comparator outputs a logical 1 "1" as the MTCH bit. The MTCH bits are typically transmitted to and stored in the memory circuitry 754, while the inverted value of the MTCH bits is transmitted onto an output inverter 756 and ultimately onto a corresponding subpixel, causing light emission and/or stop

Continuing with the transmit path of the MTCH bit, FIG. 31 shows pixel circuitry 780 that may be used with the smart buffer circuitry of FIG. Pixel circuitry 780 is, in response to write_en control signal 786 , an input latch, both operative to latch digital data transmitted from a smart buffer, eg, smart buffer 712 . 782 (eg, an inverter pair) and an output latch 784 (eg, an inverter pair). Upon latching, digital data may be automatically transmitted to the gate of driving transistor 788 . Similar to that discussed above, the driving transistor 788 is activated in response to the digital data according to the value of the digital data, and the driving current is transmitted through the light emitting circuit portion of the pixel circuit portion 780, for example, the light emitting diode 790 . make it

Accordingly, technical effects of the present invention include techniques for implementing a memory in one or more pixels of an electronic display to improve processing techniques of image data for presentation. The techniques include systems and methods for receiving image data to operate a light emitting element of a pixel to emit light, storing the image data in memory within the pixel, and transmitting the image to driver circuitry. Moreover, any suitable pixel circuitry that implements memory-in-pixel techniques may still benefit from reducing the bandwidths used to convey the same image as not using memory-in-pixel techniques, while still benefiting from binary It can be used to implement different emission schemes, including a pulse width modulated emission scheme, a binary pulse width modulated reordered emission scheme, a single pulse width modulated emission scheme, and a pulse density modulated emission scheme. These pixel circuits enabling emission schemes can be coupled to a pixel circuit with a hybrid drive to increase the responsiveness of the LED to electrical signals.

The techniques described herein may be applied and incorporated into a variety of display technologies and should not be limited to the specific embodiments shown and/or described herein. For example, while pixels with memory are shown as having a light emitting diode as the light modulation device, memory-in-pixel techniques are generally applied to different pixel circuitry to support various display technologies using various light modulation devices. can In this way, suitable pixel circuitry for supporting light emission through a light emitting diode, a digital mirror display, an organic light emitting diode, or circuitry supporting a liquid crystal display, a plasma display, or a dot-matrix display, each having a memory within the pixel, at least Improvement of data transmission bandwidths and ease of programming of pixels can be achieved.

The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It is further to be understood that the claims are not limited to the specific forms disclosed, but rather are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.

The techniques presented and claimed herein clearly improve the technical field of the present invention and therefore refer to and apply to material objects and specific examples of practical nature that are not abstract, intangible, or purely theoretical. Additionally, one or more elements in which any claims appended to the end of this specification are designated as "means for [performing] [function]..." or "steps for [performing] [function]..." If included, such elements are 35 USC 112(f) is intended to be construed. However, for any claims that include elements designated in any other way, those elements are subject to 35 U.S.C. It is not intended to be construed under 112(f).

Exemplary embodiments may include:

Illustrative Embodiment 1: An electronic display comprising:

an active area comprising a first pixel, wherein the first pixel is formed in the active area, the first pixel configured to emit light in response to the image data; and

a controller configured to transmit image data to the first pixel;

The first pixel is:

an organic light emitting diode configured to emit light in response to the image data;

a memory configured to digitally store image data received from the controller; and

An electronic display comprising: driver circuitry configured to receive image data from a memory, wherein the driver circuitry is configured to cause the organic light emitting diode to emit light in response to the image data.

Exemplary Embodiment 2: The electronic display of Exemplary Embodiment 1, wherein the controller is configured to transmit image data to the memory of the first pixel via the data line of the active region.

Exemplary Embodiment 3: The controller of Exemplary Embodiment 1, wherein the controller is configured to transmit the image data to the multiplexing circuitry via the data line of the active region, and wherein the controller is configured to mediate the transmission of the image data to the memory of the first pixel. and control the multiplexing circuitry for

Exemplary Embodiment 4: The image data of Exemplary Embodiment 3, wherein the image data includes two or more color channels corresponding to an image to be displayed, and the controller sends a first multiplexing control signal to cause a memory of a first pixel to be programmed. and program a memory associated with the first color channel of image data at a first time through enabling, wherein the controller is configured to program a memory associated with the first color channel of the image data through enabling the second multiplexing control signal to cause the memory of the second pixel to be programmed. and program a memory associated with the second color channel of image data in time.

Exemplary Embodiment 5: The controller of Exemplary Embodiment 1, wherein the controller is configured to program a memory of a first pixel with image data, the image data is associated with a first color channel and programmed at a first time, and wherein the controller is configured to: An electronic display configured to program a memory of one pixel with a second image data, wherein the second image data is associated with a second color channel and is programmed a second time.

Exemplary Embodiment 6: The electronic display of Exemplary Embodiment 1, wherein the memory of the first pixel is configured to operate as an in-display frame buffer for a first pixel in the electronic display.

Exemplary Embodiment 7: The memory of the first pixel is configured to receive the counter signal and image data, and the memory is configured to cause the organic light emitting diode to emit light according to the binary pulse width modulation emission scheme. and actuate the switch by transmitting image data based at least in part on the counter signal to operate the switch.

Exemplary Embodiment 8: The organic light emitting diode according to Exemplary Embodiment 1, wherein the driver circuitry of the first pixel comprises a comparator configured to receive a signal indicative of a number and image data, wherein the comparator is configured according to a single pulse width modulated emission scheme. and actuate the switch based at least in part on the image data and the signal indicative of the number to cause the light to emit light.

Exemplary Embodiment 9: The driver circuitry of Exemplary Embodiment 1, wherein the driver circuitry comprises an adder configured to add the image data to a defined value of the accumulator during the summing process, and wherein the carry bit from the summing process is transmitted to the pulse density modulated emission scheme. and actuating the switch to cause the organic light emitting diode to emit light accordingly.

Illustrative Embodiment 10: A subpixel of a specific color in an electronic display, comprising:

a memory configured to receive a signal representing a value within the data range;

a first terminal configured to receive a first voltage signal;

a second terminal configured to receive a second voltage signal; and

a light emitting diode configured to emit light based at least in part on a signal representative of a value within the data range, wherein the memory is configured to cause a current to be transmitted through the light emitting diode to cause light emission, wherein the current is the first voltage signal and a subpixel based at least in part on the second voltage signal.

Exemplary Embodiment 11: The memory of Exemplary Embodiment 10, wherein the memory comprises a register configured to receive a counter signal and a signal representing a value within a data range, wherein the memory comprises a light emitting diode configured to emit light according to a binary pulse width modulated emission scheme. and operate the switch by transmitting a signal representing a value within the data range based at least in part on the counter signal to cause it to emit.

Exemplary Embodiment 12: The signal of Exemplary Embodiment 10, comprising a comparator configured to receive a signal representative of a number and a signal representative of a value within a data range, wherein the comparator operates on a signal representative of a number and a signal representative of a value within a data range. and operate the light emitting diode to emit light according to a single pulse width modulated emission scheme based on the subpixel.

Exemplary Embodiment 13: The adder of Exemplary Embodiment 10, comprising an adder configured to add a signal representing a value within a data range to a defined value of an accumulator configured to be coupled to the adder during a summing process; The carry bit from the process is configured to operate the light emitting diode to emit light according to a pulse density modulated emission scheme.

Exemplary Embodiment 14: The memory of Exemplary Embodiment 10, wherein the memory receives a signal representative of a value within the data range for a period of time before allowing the signal representative of a value within the data range to be used to cause light to be emitted from the light emitting diode. A subpixel configured to act as a frame buffer for storage.

Exemplary Embodiment 15 A pixel comprising:

a first subpixel of the pixel, the first subpixel corresponding to a first color channel, the first subpixel comprising:

a first memory configured to store a first signal representing a first value within a first data range used to convey image data of a first color channel for the pixel; and

first driver circuitry configured to receive a first signal representative of a first value from a first memory and configured to cause the first light emitting diode to emit light based at least in part on the first signal representative of the first value; Ham -; and

a second subpixel of the pixel, the second subpixel corresponding to a second color channel, the second subpixel comprising:

a second memory configured to store a second signal representing a second value within a second data range used to convey image data of a second color channel for the pixel; and

and a second driver circuitry configured to receive a second signal indicative of a second value from the second memory and configured to cause the second light emitting diode to emit light based at least in part on the second signal indicative of the second value; containing - a pixel.

Exemplary Embodiment 16: The first subpixel of Exemplary Embodiment 15, wherein the first subpixel is configured to be programmed with a first signal representative of a first value at a first time, and wherein the second subpixel is configured to be programmed with a first signal representative of a first value at a second time. a pixel configured to be programmed with a second signal representing the first time occurring prior to the second time.

Exemplary Embodiment 17: The first subpixel according to Exemplary Embodiment 16, wherein the first signal is configured to be transmitted to the first subpixel via the multiplexing circuitry configured to operate in response to the first control signal transmitted at a first time, and wherein the signal is configured to cease transmission to the first subpixel in response to the multiplexing circuitry receiving the second control signal transmitted at a second time.

Exemplary Embodiment 18: The pixel of Exemplary Embodiment 15, wherein the first memory is configured to operate as a frame buffer for the first subpixel.

Exemplary Embodiment 19: The first subpixel of Exemplary Embodiment 15, wherein the first subpixel comprises a first counter, wherein the first memory is configured to receive an output from the first counter, wherein the output from the first memory is a counter a pixel configured to activate the switch in response to an output from the first memory, wherein the output from the first memory is configured to operate the first light emitting diode to emit light according to a binary pulse width modulated emission scheme.

Exemplary Embodiment 20: The first driver circuitry of Exemplary Embodiment 15, wherein the first driver circuitry outputs an output from the first memory and an output from a counter configured to correspond to a time difference between increments of a gray level associated with the first color channel. a comparator configured to receive, wherein the first driver circuitry is configured to operate the first light emitting diode based at least in part on an output from the comparator.

Illustrative Embodiment 21 An electronic display comprising:

a memory formed in an active area of the electronic display or formed in an integrated circuit portion of the electronic display outside the active area, wherein the memory is configured to store digital data signals representing values within a data range;

a driver disposed within the active region, wherein the driver is configured to generate one or more analog electrical signals in response to the digital data signal; and

An electronic display comprising: a light modulation device disposed on the active area, the light modulation device configured to emit light based at least in part on one or more analog electrical signals.

Exemplary Embodiment 22: The light modulating device of Exemplary Embodiment 21, wherein the light modulating device is a light emitting diode, a digital mirror display, an organic light emitting diode, or devices supporting a liquid crystal display, a plasma display, or a dot-matrix display, or their An electronic display, including any combination.

Exemplary Embodiment 23: The light modulation device of Exemplary Embodiment 21, wherein the light modulation device comprises a light emitting diode, wherein the light emitting diode and driver support a global cathode or global anode configuration configured to emit light using one or more analog electrical signals. An electronic display configured to:

Exemplary Embodiment 24: The light modulating device of Exemplary Embodiment 21, wherein the light modulation device comprises a light emitting diode, wherein the light emitting diode and driver support a global cathode or global anode configuration configured to emit light using one or more analog electrical signals. An electronic display configured to:

Exemplary Embodiment 25: The memory of Exemplary Embodiment 24, wherein the memory comprises a transistor configured to be activated in response to a select control signal, and wherein the first subset of digital data signals is configured to be transmitted to the driver in response to activation of the transistor. being an electronic display.

Exemplary Embodiment 26 The electronic display of Exemplary Embodiment 24, wherein the first pair of inverters are configured to output the first subset of digital data signals to the sense amplifier prior to outputting to the driver.

Illustrative Embodiment 27: The example of embodiment 24, comprising a switch/reset (SR) latch configured to be coupled to an output of a first pair of inverters and a second pair of inverters configured to be coupled to an output of the switch/reset latch. and the switch/reset latch and the second inverter pair are configured to enable a binary pulse width modulated emission scheme with realignment.

Exemplary Embodiment 28 The electronic display of Exemplary Embodiment 24, wherein the memory comprises a second pair of inverters configured to store a second subset of digital data signals transmitted to the pixels.

Exemplary Embodiment 29: The first inverter of Exemplary Embodiment 28, wherein the first subset of digital data signals and the second subset of digital data signals are responsive to the controller enabling the write-enabled control signal. Electronic display, transmitted in pairs.

Illustrative Embodiment 30: A pixel of an electronic display, comprising:

a memory configured to store a first digital data signal transmitted from the column driver to the pixel, the first digital data signal configured to correspond to an image to be displayed via having a value within a data range to convey a portion of the image, the memory comprising: ,

one or more inverter pairs configured to receive a first digital data signal transmitted from the column driver to the memory in the pixel; and

a comparator configured to receive a first digital data signal and a second digital data signal from one or more pairs of inverters, the comparator to output a control signal in response to determining when the first digital data signal matches the second digital data signal configured - contains -; and

A pixel comprising: a driver configured to receive a control signal from a memory, wherein the driver is configured to cause light to be emitted from the pixel based at least in part on the control signal.

Exemplary Embodiment 31 The pixel of Exemplary Embodiment 30 comprising a counter configured to output to a comparator an indication of the counted current number as the second digital data signal.

Exemplary Embodiment 32 The pixel of Exemplary Embodiment 30 comprising a transistor configured to enable precharging of a memory.

Exemplary Embodiment 33 The pixel of Exemplary Embodiment 30 comprising an additional inverter pair separate from the one or more inverter pairs configured to store the output from the comparator prior to transmission to the driver as a control signal.

Exemplary Embodiment 34: The pixel of Exemplary Embodiment 33, wherein the further inverter pair is reset between the first storage of the first output and the second storage of the second output.

Exemplary Embodiment 35: The pixel of Exemplary Embodiment 30, comprising a transistor configured to enable a control signal to be output from a comparator to be transmitted to a driver, wherein the transistor is configured to be activated in response to an emission enable signal.

Exemplary Embodiment 36 The pixel of Exemplary Embodiment 30, comprising an additional memory corresponding to a color channel associated with displaying an image, wherein the additional memory is configured to be coupled to the driver.

Illustrative Embodiment 37: An electronic display comprising:

a controller configured to generate one or more digital data signals to cause an image to be displayed;

a buffer comprising a first memory configured to store a first digital data signal of the one or more data signals, the first digital data signal configured to cause a portion of the image to be displayed on the electronic display; and

a plurality of pixels configured to emit light in response to one or more digital data signals, each pixel of the plurality of pixels comprising:

a driver configured to receive a first digital data signal from the first memory, wherein the driver is configured to generate an analog data signal in response to the first digital data signal transmitted from the first memory; and

An electronic display comprising: a light emitting circuitry configured to be coupled to the driver, the light emitting circuitry being configured to emit light based at least in part on the analog data signal.

Exemplary Embodiment 38: The second digital data signal of Exemplary Embodiment 37, comprising selection circuitry configured to be coupled to an output of the first memory and an output of the second memory, wherein the buffer is further configured to store a second digital data signal an electronic display comprising a memory, wherein the selection circuitry is configured to select the first memory for outputting the first digital data signal to the driver independently of selecting the second memory.

Exemplary Embodiment 39: The 38, wherein the selection circuitry is configured to be coupled to an output of an inverter pair, wherein the inverter pair is configured to store an output from the first memory when the selection circuitry operates in the first state. and wherein the inverter pair is configured to store the output from the second memory when the select circuit portion operates in the second state.

Exemplary Embodiment 40: The example of embodiment 37, wherein each pixel comprises counting circuitry configured to be coupled to a first subpixel, wherein the first subpixel comprises a comparator, the comparator comprising an output from the counting circuitry and compare to the output from the first memory.

Illustrative Embodiment 41: A pixel circuit for an electronic display, comprising:

a memory configured to store a digital data signal representing a value within the data range;

a light emitting diode configured to emit light based at least in part on the digital data signal;

an initialization transistor configured to initialize the pixel circuit before the light emitting diode emits light; and

A pixel circuit comprising a driving transistor configured to be activated based at least in part on a digital data signal.

Exemplary Embodiment 42: The light emitting diode of Exemplary Embodiment 41, comprising voltage drive circuitry configured to be coupled to an anode of the light emitting diode, wherein the voltage drive circuitry is configured to boost the anode of the light emitting diode at the beginning of a light emitting period of the light emitting diode being a pixel circuit.

Exemplary Embodiment 43 The driving transistor of Exemplary Embodiment 41, wherein the driving transistor is configured as a metal oxide semiconductor field effect transistor (MOSFET), and the pixel circuit comprises a plurality of light emitting diodes configured to cause the light emitting diode to emit light in response to the control signals. A pixel circuit comprising p-type or n-type MOSFETs.

Exemplary Embodiment 44: The pixel circuit of Exemplary Embodiment 41, comprising reset circuitry configured to be coupled in parallel to the light emitting diode, wherein the reset circuitry is configured to reset the anode voltage of the light emitting diode after an emission period.

Exemplary Embodiment 45: The hybrid drive of Exemplary Embodiment 41, comprising a hybrid drive comprising voltage drive and current drive circuitry, wherein the hybrid drive comprises a voltage data signal, a plurality of and operate the light emitting diode to emit light in response to the reference voltages of and the image data control signal.

Exemplary Embodiment 46: The auto-zero transistor of illustrative embodiment 41, comprising an auto-zero transistor configured to be activated in response to an auto-zero control signal, wherein the voltage value at the source node of the auto-zero transistor is the source of the auto-zero transistor. and increase until the voltage value of the node is equal to the voltage value of the gate voltage of the driving transistor.

Exemplary Embodiment 47: The memory of Exemplary Embodiment 41, wherein the memory comprises a register configured to store the digital data signal, and a comparator configured to compare the digital data signal to a number configured to be generated by the counter, wherein the memory comprises the driving transistor and transmit an output from the comparator to activate the pixel circuit.

Exemplary Embodiment 48: The driving transistor according to Exemplary Embodiment 41, to cause light emission according to a binary pulse width modulated emission scheme, a single pulse width modulated emission scheme, or a pulse density modulated emission scheme, or any combination thereof. and additional circuitry configured to operate in conjunction with the memory to activate the pixel circuit.

Illustrative Embodiment 49: An electronic display comprising:

a controller configured to generate one or more digital data signals to cause an image to be displayed; and

a plurality of pixels configured to emit light in response to one or more digital data signals, a first pixel of the plurality of pixels comprising:

a memory configured to receive a first digital data signal generated by the controller based at least in part on the image;

a light emitting circuit portion configured to emit light based at least in part on the first digital data signal;

an initialization transistor configured to initialize the first pixel before the light emitting circuitry emits light; and

and a driving transistor configured to be activated based at least in part on the first digital data signal.

Exemplary Embodiment 50: The method of Exemplary Embodiment 49, comprising a second pixel of the plurality of pixels, wherein the memory of the second pixel comprises: a time period when the memory of the first pixel is configured to receive the first digital data signal; is configured to receive the second digital data signal at a different time.

Exemplary Embodiment 51 The electronic display of Exemplary Embodiment 50, wherein the controller is configured to mediate transmission of the one or more digital data signals to the one or more pixels via controlling the multiplexing circuitry.

Exemplary Embodiment 52: The electronic display of Exemplary Embodiment 49, wherein the light emitting circuitry comprises a light emitting diode, and wherein the first pixel comprises a voltage drive circuitry configured to boost an anode of the light emitting diode during the light emission period of the light emitting diode. .

Exemplary Embodiment 53 The first pixel emits light in response to the voltage data signal, the plurality of reference voltages, and the image data control signal based at least in part on the first digital data signal. and hybrid drive circuitry configured to operate the light emitting circuitry to

Exemplary embodiment 54: The light emitting circuitry of illustrative embodiment 49, wherein the light emitting circuitry supports a light emitting diode, an organic light emitting diode, or a liquid crystal display, a plasma display panel, a dot-matrix display, a digital mirror drive display, or any combination thereof An electronic display comprising a circuit unit to:

Illustrative Embodiment 55: A method comprising:

sending, via the controller, a first value at a first time into a first memory of a first pixel;

performing, via the controller, an initialization process to prepare the first pixel to emit light according to the first value;

performing, via the controller, a programming process to program the nodes of the first pixel to one or more voltage values; and

performing, via the controller, an emitting process, wherein the performing of the emitting process is configured to cause light to be emitted from the light emitting circuitry of the first pixel.

Exemplary Embodiment 56 The step of Exemplary Embodiment 55 wherein transmitting the first value into the first memory comprises:

by enabling, via the controller, the first multiplexing control signal to allow transmission of the first value into the first memory at a first time; and

mediating programming of the second memory of the first memory and the second pixel by disabling, via the controller, a second multiplexing control signal to cease transmission of the first value into the second memory at a first time; How to.

Exemplary Embodiment 57 The programming process of Exemplary Embodiment 45 includes:

enabling, via the controller, an auto-zero control signal; and

disabling, via the controller, the auto-zero control signal after a defined time.

Exemplary Embodiment 58 The emitting process of Exemplary Embodiment 45 includes:

enabling, via the controller, a voltage drive control signal configured to cause boosting of the light emitting circuitry; and

emitting, through the controller, an image data control signal configured to activate the driving transistor according to a binary pulse width modulated emission scheme, a single pulse width modulated emission scheme, a pulse density modulated emission scheme, or any combination thereof; , Way.

Exemplary Embodiment 59: The method of Exemplary Embodiment 45, comprising performing a reset process to reset the light emitting circuitry to prepare for future light emission.

Exemplary Embodiment 60: The initialization process of Exemplary Embodiment 45, wherein the initialization process comprises, via a controller, enabling a select control signal to cause charging of the capacitor, through charging of the capacitor, the capacitor is driven configured to cause a current to be transmitted through the first pixel.

Claims (25)

An electronic display comprising:
an active area comprising a row of pixels, the row of pixels comprising a first subpixel and a second subpixel, the first subpixel configured to emit light in response to the first image data; and
a controller configured to transmit the first image data to the first subpixel at a first time and to transmit second image data to the second subpixel at a second time;
The first sub-pixel includes:
a current source configured to generate a current;
an organic light emitting diode configured to emit the light in response to the current;
a memory configured to digitally store the first image data received from the controller; and
driver circuitry configured to receive a control signal generated based at least in part on the first image data stored in the memory, wherein the driver circuitry transmits, at least in part, the current to the organic light emitting diode in response to the control signal. An electronic display configured to cause an organic light emitting diode to emit the light. The memory according to claim 1, wherein the memory of the first subpixel is configured to receive a counter signal and the first image data, the memory causing the organic light emitting diode to emit the light according to a binary pulse width modulation emission scheme. and transmit the first image data based at least in part on the counter signal to operate a switch. 2. The device of claim 1, wherein the driver circuitry of the first subpixel comprises a comparator configured to receive a signal indicative of a number and the first image data, the comparator configured to cause the organic light emitting diode according to a single pulse width modulated emission scheme. and actuate a switch based at least in part on the signal indicative of the number and the first image data to cause the light to emit. 5. The scheme of claim 1, wherein the driver circuitry comprises an adder configured to add the first image data to a defined value of an accumulator during a summing process, wherein a carry bit from the summing process is a pulse density modulated emission scheme. and operate a switch to cause the organic light emitting diode to emit the light according to 2. The method of claim 1, wherein the controller is configured to program the memory of the first subpixel with the first image data, the first image data being associated with a first color channel and programmed at the first time, the and a controller is configured to program the memory of the first subpixel with the second image data, the second image data being associated with a second color channel and programmed at the second time. An electronic display comprising:
a memory formed in an active area of the electronic display, the memory configured to store a digital data signal representing a value within a data range;
a first pixel disposed within the active area, the first pixel configured to transmit one or more analog electrical signals to a light modulation device in response to a first control signal generated based at least in part on the digital data signal including drivers;
and the light modulation device is configured to emit light in response to receiving the one or more analog electrical signals. 7. The method of claim 6, wherein the light modulation device comprises a light emitting diode, a digital mirror display, an organic light emitting diode, or devices that support a liquid crystal display, a plasma display, or a dot-matrix display, or any combination thereof. electronic display. 7. The electronic display of claim 6, wherein the memory comprises three or more inverter pairs each configured to store a respective bit of the digital data signal. 9. The electronic display of claim 8, wherein the three or more inverter pairs are each configured to output the respective bit to a sense amplifier at different times prior to outputting to the driver. 7. The switch of claim 6 comprising a switch/reset (SR) latch configured to output a signal to a gate of a switch, the switch responsive to a signal from the switch/reset (SR) latch to accept an input of a second pair of inverters. An electronic display configured to couple to ground. 7. The method of claim 6, wherein the memory is configured to output one or more bits of the digital data signal to circuitry configured to generate the first control signal based at least in part on the digital data signal, the second control signal comprising: An electronic display comprising a plurality of signals indicative of a count maintained by circuitry. 12. The method of claim 11, wherein the circuitry includes a comparator, wherein the one or more bits are transmitted from the memory to the comparator, the comparator responsive to determining that the count matches a value within the data range. An electronic display that generates a signal. 7. The global cathode or global anode of claim 6, wherein the light modulation device comprises a light emitting diode, the light emitting diode and the driver configured to emit light using the one or more analog electrical signals. ) an electronic display configured to support configuration. A pixel circuit for an electronic display, comprising:
a driving transistor coupled between the current source and the light emitting diode, the light emitting diode configured to emit light in response to a signal transmitted from the current source through the driving transistor;
a memory configured to store a digital data signal representing a value within the data range;
a comparator configured to compare the digital data signal to an indication of the number and transmit an output to activate the driving transistor based on the comparison, wherein a counter is configured to generate the indication of the number; and
and an initialization transistor configured to initialize the pixel circuit before the light emitting diode emits light. 15. The light emitting diode of claim 14, comprising voltage drive circuitry configured to be coupled to an anode of the light emitting diode, wherein the voltage drive circuitry is configured to boost the anode of the light emitting diode at the beginning of a light emitting period of the light emitting diode. , pixel circuit. 15. The method of claim 14, wherein the driving transistor is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET), and wherein the pixel circuit is configured such that the light emitting diode emits light in response to control signals. A pixel circuit comprising a plurality of p-type or n-type MOSFETs configured to 15. The pixel circuit of claim 14, comprising reset circuitry configured to be coupled in parallel to the light emitting diode, wherein the reset circuitry is configured to reset the anode voltage of the light emitting diode after an emission period. 15. The method of claim 14, comprising a hybrid drive, wherein the hybrid drive comprises voltage drive and current drive circuitry, wherein the hybrid drive comprises a voltage data signal, a plurality of reference voltages, based at least in part on the digital data signal; and operate the light emitting diode to emit light in response to an image data control signal. 15. The method of claim 14, together with the memory to activate the driving transistor to cause light emission according to a binary pulse width modulated emission scheme, a single pulse width modulated emission scheme, a pulse density modulated emission scheme, or any combination thereof. and additional circuitry configured to operate. 15. The pixel circuit of claim 14, wherein the memory comprises a register configured to store the digital data signal. An electronic device having a display comprising a plurality of pixels, the electronic device comprising:
A pixel of the plurality of pixels comprises:
a first subpixel of the pixel, the first subpixel corresponding to a first color channel, the first subpixel comprising:
a first memory configured to store a first digital data signal representing a first value within a first data range used to convey image data of the first color channel for the pixel; and
first driver circuitry configured to transmit one or more first analog electrical signals to a first optical modulation device in response to a first control signal generated based at least in part on the first digital data signal; and
a second subpixel of the pixel, the second subpixel corresponding to a second color channel, the second subpixel comprising:
a second memory configured to store a second digital data signal representing a second value within a second data range used to convey image data of the second color channel for the pixel; and
and second driver circuitry configured to transmit one or more second analog electrical signals to a second optical modulation device in response to a second control signal generated based at least in part on the second digital data signal; , electronic devices. 22. The method of claim 21, wherein the first subpixel is configured to be programmed with the first digital data signal at a first time, and the second subpixel is configured to be programmed with the second digital data signal at a second time; wherein the first time occurs prior to the second time. 23. The method of claim 22, wherein the first digital data signal is configured to be transmitted to the first subpixel through a multiplexing circuitry configured to operate in response to a third control signal transmitted at the first time, and wherein the first digital data signal is transmitted to the first subpixel. and a signal is configured to cease transmission to the first subpixel in response to the multiplexing circuitry receiving a fourth control signal transmitted at the second time. The electronic device of claim 21 , wherein the first memory is configured to operate as a frame buffer for the first subpixel. 22. The method of claim 21, wherein the first subpixel comprises a first counter, and wherein the first memory is configured to receive an output from the first counter, wherein the output from the first memory is from the first counter. and activate a switch in response to an output of , wherein the output from the first memory is configured to operate the first light modulation device to emit light according to a binary pulse width modulated emission scheme.

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