CN110444589A - 一种具有过流保护功能的igbt - Google Patents

一种具有过流保护功能的igbt Download PDF

Info

Publication number
CN110444589A
CN110444589A CN201910806529.5A CN201910806529A CN110444589A CN 110444589 A CN110444589 A CN 110444589A CN 201910806529 A CN201910806529 A CN 201910806529A CN 110444589 A CN110444589 A CN 110444589A
Authority
CN
China
Prior art keywords
layer
type
dielectric layer
igbt
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910806529.5A
Other languages
English (en)
Other versions
CN110444589B (zh
Inventor
张金平
王康
赵阳
刘竞秀
李泽宏
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201910806529.5A priority Critical patent/CN110444589B/zh
Publication of CN110444589A publication Critical patent/CN110444589A/zh
Application granted granted Critical
Publication of CN110444589B publication Critical patent/CN110444589B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明属于功率半导体器件技术领域，涉及绝缘栅双极型晶体管(IGBT),具体涉及一种具有过流保护功能的IGBT。通过在传统的IGBT结构基础上集成一个PMOS结构，同时在PMOS上连接一个二极管与电阻，PMOS结构能够提供检测电流，当检测电流流过PMOS上连接的电阻时，会在电阻上产生一个压降，通过检测电阻上压降的大小可以迅速判断器件是否发生过流现象，且该过流保护方法简单，高效，能有效保证器件的安全工作。

Description

一种具有过流保护功能的IGBT
技术领域
本发明属于功率半导体器件技术领域，涉及绝缘栅双极型晶体管(IGBT),具体涉及一种具有过流保护功能的IGBT。
技术背景
绝缘栅双极型晶体管(IGBT)作为新一代的电力电子器件因其结合了场效应晶体管(MOSFET)和双极结晶型晶体管(BJT)的优点，既具有MOSFET易于驱动、输入阻抗低、开关速度快的优点，又具有BJT通态电流密度大、导通压降低、损耗小、稳定性好的优点。因而发展为现代电力电子电路中的核心电子元器件之一，被广泛应用于交通、通信、家用电器及航空航天各个领域。IGBT的运用极大地改善了电力电子系统的性能。
当前市场上IGBT(如图1所示)的单管使用的越来越频繁，在大部分应用中，一直都是采用电流互感器或电流传感器对IGBT器件进行过流检测，这个过程周期长、响应慢，问题多，当出现过流时器件会因为这些因素可能导致器件因过流而失效，为了保证IGBT单管使用的效率，必须采用一种快捷、方便、相应速度快的过流保护方法来保护IGBT器件，甚至保护整个系统的正常运行。
发明内容
本发明为了克服现有的IGBT过流保护方法的不足，本发明提出了一种具有过流保护功能的IGBT结构，通过在传统的IGBT结构基础上集成一个PMOS结构，同时在PMOS上连接一个二极管与电阻，PMOS结构能够提供检测电流，当检测电流流过PMOS上连接的电阻时，会在电阻上产生一个压降，通过检测电阻上压降的大小可以迅速判断器件是否发生过流现象。
本发明的技术方案如下：
一种具有过流保护功能的IGBT结构，其元胞结构示意图如图2所示，包括：从下至上依次层叠设置的背部集电极金属1、P型集电区2、N型场阻止层3和N-漂移区4；所述N-漂移区4上方具有P型埋层13、沟槽结构、N型电荷存储层5；其特征在于：所述沟槽结构包括：栅电极81、栅介质层71、分离栅电极82、分离栅介质层72；所述N型电荷存储层5上方具有P型基区6；所述P型基区6上方具有并排设置且相互独立的N+发射区9、P+接触区10；所述P型埋层上方具有N型埋层14,；所述N型埋层14上方具有P型掺杂区15；所述P型掺杂区15上方具有接触金属16；所述介质层72上方、隔离介质层73上方、栅介质层71上方、栅电极81上方具有介质层11；所述分离栅电极82上方、N+发射区9上方、P+接触区10上方具有发射极金属12上方具有发射极金属12；所述栅电极81、栅介质层71上方具有介质层11；所述接触金属16与发射极金属12之间串联；连接有二极管17、电阻18；所述电阻18两端具有电压检测接口AB。
进一步的，一种具有过流保护功能的IGBT结构示意图如图3所示，其特点是将分离栅82改成L型包围住栅电极71。
进一步的，一种具有过流保护功能的IGBT结构示意图如图4所示，其特点是将二极管17集成到器件内部，N+半导体171和P+半导体172构成二极管17。
进一步的，一种具有过流保护功能的IGBT结构示意图如图5所示，其特点是将金属16替换成肖特基接触金属161。
进一步的，一种具有过流保护功能的IGBT结构示意图如图6所示，其特点是将电阻18集成到器件内部，所述电阻18由多晶掺杂材料21、接触金属22构成。
进一步，一种具有过流保护功能的IGBT结构示意图如图7所示，其特点是将P型掺杂层15、N型埋层14、P型埋层13部分替换成P型埋层23且串联2个二极管17。
进一步的本发明中的IGBT器件半导体材料采用Si、SiC、GaAs或者GaN,沟槽填充材料采用多晶Si、SiC、GaAs或者GaN，且各部分可以采用相同的材料也可采用不同材料组合。
进一步的，所述器件结构不仅适用于IGBT器件，将器件背面的P型集电区2换为N+层，所述结构同样适用于MOSFET器件。
本发明的工作原理
当发射极12接低电位，集电极2接高电位，栅电极81接大于其阈值电压的高电位时，器件处于正向导通状态，电流从IGBT的MOS沟道流走，当集电极电压继续增大时，由P型埋层13、N型埋层14、P型掺杂层15与分离栅电极82构成的PMOS结构开启，PMOS结构为空穴的流动提供额外的通路，与PMOS相连的电阻18上会有电流流过，会在电阻18上产生一个压降，当器件工作在稳定状态时，流过电阻18上的电流是恒定的，当器件因外部环境或工作电路发生故障而导致发生过流现象时，流过电阻18上的电流会随之增大，其上的压降也随之增大，通过接口AB检测电阻18上的压降可以迅速判断器件是否发生过流现象从而触发外部的过流保护机制保护器件不损坏。
本发明的有益效果表现在：
针对现有的IGBT过流保护方法的不足，本发明提出的一种具有过流保护功能的IGBT结构，通过在传统的IGBT结构基础上集成一个PMOS结构，同时在PMOS上连接一个二极管与电阻，PMOS结构能够提供检测电流，当检测电流流过PMOS上连接的电阻时，会在电阻上产生一个压降，通过检测电阻上压降的大小可以迅速判断器件是否发生过流现象，且该过流保护方法简单，高效，能有效保证器件的安全工作。
附图说明
图1是传统IGBT半元胞结构示意图，其中，1是集电极金属，2是P+集电区，3是N型场阻止层，4是N-漂移区，5是N型电荷存储层，6是P型基区，7是栅介质层，8是多晶栅电极，9是N+发射区，10是P+接触区，11是介质层，12是发射极金属。
图2是本发明实施例1提出的一种具有过流保护功能的IGBT的元胞结构示意图；
图3是本发明实施例2提出的一种具有过流保护功能的IGBT的元胞结构示意图；
图4是本发明实施例3提出的一种具有过流保护功能的IGBT的元胞结构示意图；
图5是本发明实施例4提出的一种具有过流保护功能的IGBT的元胞结构示意图；
图6是本发明实施例5提出的一种具有过流保护功能的IGBT的元胞结构示意图；
图7是本发明实施例6提出的一种具有过流保护功能的IGBT的元胞结构示意图；
图2至图7中，其中，1是集电极金属，2是P+集电区，3是N型场阻止层，4是N-漂移区，5是N型电荷存储层，6是P型基区，71是栅介质层，72分离栅介质层，73是介质层，74是介质层，81是栅电极，82是分离栅电极，9是N+发射区，10是P+接触区，11是介质层，12是发射极金属，13是P型埋层，14是N型埋层，15是P型掺杂层，16是接触金属，161肖特基接触金属，17是二极管，171是二极管N+半导体部分，172是二极管P+半导体接触部分，18是电阻，19是接触金属，20是隔离介质层,21是多晶掺杂材料，22是接触金属，23是P型埋层。
具体实施方式
以下结合附图，对本发明的原理和特性做进一步的说明，所举实施例只用于解释本发明，并非用于限定本发明的范围。
实施例1
一种具有过流保护功能的IGBT结构，其元胞结构示意图如图2所示，包括：从下至上依次层叠设置的背部集电极金属1、P型集电区2、N型场阻止层3和N-漂移区4；所述N-漂移区4上方具有P型埋层13、沟槽结构、N型电荷存储层5；其特征在于：所述沟槽结构包括：栅电极81、栅介质层71、分离栅电极82、分离栅介质层72，隔离介质层73；所述N型电荷存储层5上方具有P型基区6；所述P型基区6上方具有并排设置且相互独立的N+发射区9、P+接触区10；所述P型埋层上方具有N型埋层14,；所述N型埋层14上方具有P型掺杂区15；所述P型掺杂区15上方具有接触金属16；栅介质层71上方、隔离介质层73、栅介质层72、栅电极81上方具有介质层11；所述分离栅电极82、N+发射区9上方、P+接触区10上方具有发射极金属12；；所述接触金属16与发射极金属12之间连接有二极管17、电阻18；所述电阻18两端具有电压检测接口AB；所述沟槽深度大于N型电荷存储层5的深度；所述栅电极81通过栅介质层71与N+发射区9、P+发射区10、P型基区9、N型电荷存储层5、N-漂移区4相连；所述栅电极81通过介质层73与分离栅电极82相连；所述分离栅电极82通过分离栅介质层72与P型埋层13、N型埋层14、P型掺杂层15相连；所述二极管17阳极与金属16相连，阴极与电阻18相连；所述电阻18一端与二极管阴极相连，另一端与发射极金属12相连；所述P型埋层的结深可以与沟槽深度相等，也可以延伸到沟槽另一侧。
实施例2
一种具有过流保护功能的IGBT结构，其元胞结构示意图如图3所示，包括：从下至上依次层叠设置的背部集电极金属1、P型集电区2、N型场阻止层3和N-漂移区4；其特征在于：所述N-漂移区4上方具有P型埋层13、沟槽结构、N型电荷存储层5；其特征在于：所述沟槽结构包括：栅电极81、栅介质层71、分离栅电极82、分离栅介质层72，介质层74；所述N型电荷存储层5上方具有P型基区6；所述P型基区6上方具有并排设置且相互独立的N+发射区9、P+接触区10；所述P型埋层上方具有N型埋层14,；所述N型埋层14上方具有P型掺杂区15；所述P型掺杂区15上方具有接触金属16；所述栅电极81上方、栅介质层71上方、栅介质层72上方具有介质层11；所述分离栅电极82上方、N+发射区9上方、P+接触区10上方具有发射极金属12；所述接触金属16与发射极金属12之间连接有二极管17、电阻18；所述电阻18两端具有电压检测接口AB，其特点是：所述分离栅82深度大于N型电荷存储层5的深度；所述栅电极81的深度大于P型基区6的深度小于N型电荷存储层5的深度；所述栅电极81通过栅介质层71与N+发射区9、P+发射区10、P型基区9相连；所述栅电极81通过介质层71与分离栅电极82相连；所述分离栅电极82通过分离栅介质层72与P型埋层13、N型埋层14、P型掺杂层15相连，所述分离栅电极82通过介质层74与N型电荷存储层5、N-漂移区4相连，所述分离栅电极81呈L型包围住栅电极81，所述介质层74的厚度大于或等于栅介质层71的厚度；所述二极管17阳极与金属16相连，阴极与电阻18相连；所述电阻18一端与二极管阴极相连，另一端与发射极金属12相连；所述P型埋层的结深可以与沟槽深度相等，也可以延伸到沟槽另一侧。
实施例3
一种具有过流保护功能的IGBT结构，其元胞结构示意图如图4所示，其特征在于在实施例1的基础上，将二极管17集成到器件内部，二极管17有N+半导体171与P+半导体172构成。
该结构通过将二极管17集成到器件内部提高了器件的集成度，同时简化外部电路的复杂度。
实施例4
一种具有过流保护功能的IGBT结构，其元胞结构示意图如图5所示，其特征在于在实施例2的基础上，将接触金属16替换成肖特基接触金属161。
该结构通过将接触金属16替换成肖特基接触金属161进一步降低了金属与P型掺杂层的接触电阻，提高了过流检测的灵敏度。
实施例5
一种具有过流保护功能的IGBT结构，其元胞结构示意图如图6所示，其特征在于在实施例1的基础上，将电阻18集成到器件内部，电阻18由多晶掺杂材料21接触金属22构成
该结构通过将电阻18集成到器件内部提高了器件的集成度。
实施例6
一种具有过流保护功能的IGBT结构，其元胞结构示意图如图7所示，其特征在于在实施例2的基础上将将P型掺杂层15、N型埋层14、P型埋层13部分替换成P型埋层23且串联2个二极管17。
增加二极管的数量提高了电流嵌位的效果，使得P型埋层23不易在低电压下导通。

Claims (8)

1.一种具有过流保护功能的IGBT，其元胞结构，包括：从下至上依次层叠设置的背部集电极金属(1)、P型集电区(2)、N型场阻止层(3)和N-漂移区(4)；所述N-漂移区(4)上方沿器件横向方向依次具有P型埋层(13)、沟槽结构、N型电荷存储层(5)；其特征在于：所述沟槽结构包括：栅电极(81)、栅介质层(71)、分离栅电极(82)、分离栅介质层(72)，隔离介质层(73)；所述N型电荷存储层(5)上方具有P型基区(6)；所述P型基区(6)上方具有并列设置的N+发射区(9)、P+接触区(10)；所述P型埋层上方具有N型埋层(14)；所述N型埋层(14)上方具有P型掺杂区(15)；所述P型掺杂区(15)上方具有接触金属(16)；栅介质层(71)上方、隔离介质层(73)、栅介质层(72)、栅电极(81)上方具有介质层(11)；所述分离栅电极(82)、N+发射区(9)上方、P+接触区(10)上方具有发射极金属(12)；；所述接触金属(16)与发射极金属(12)之间连接有二极管(17)、电阻(18)；所述电阻(18)两端具有电压检测接口AB；所述沟槽深度大于N型电荷存储层(5)的深度；所述栅电极(81)通过栅介质层(71)与N+发射区(9)、P+发射区(10)、P型基区(9)、N型电荷存储层(5)、N-漂移区(4)相连；所述栅电极(81)通过介质层(73)与分离栅电极(82)相连；所述分离栅电极(82)通过分离栅介质层(72)与P型埋层(13)、N型埋层(14)、P型掺杂层15相连；所述二极管(17)阳极与金属(16)相连，阴极与电阻(18)相连；所述电阻(18)一端与二极管阴极相连，另一端与发射极金属(12)相连。所述P型埋层(13)范围从与与栅介质层(72)接触一侧延伸到栅介质层(71)一侧。
2.一种具有过流保护功能的IGBT，其元胞结构，包括：从下至上依次层叠设置的背部集电极金属(1)、P型集电区(2)、N型场阻止层(3)和N-漂移区(4)；所述N-漂移区(4)上方沿器件横向方向依次具有P型埋层(13)、沟槽结构、N型电荷存储层(5)；其特征在于：所述沟槽结构包括：栅电极(81)、栅介质层(71)、分离栅电极(82)、分离栅介质层(72)，介质层74；所述N型电荷存储层(5)上方具有P型基区(6)；所述P型基区(6)上方具有并排设置且相互独立的N+发射区(9)、P+接触区(10)；所述P型埋层上方具有N型埋层(14)；所述N型埋层(14)上方具有P型掺杂区(15)；所述P型掺杂区(15)上方具有接触金属(16)；所述栅电极(81)上方、栅介质层(71)上方、栅介质层(72)上方具有介质层(11)；所述分离栅电极(82)上方、N+发射区(9)上方、P+接触区(10)上方具有发射极金属(12)；所述接触金属(16)与发射极金属(12)之间连接有二极管(17)、电阻(18)；所述电阻(18)两端具有电压检测接口AB，其特点是：所述分离栅82深度大于N型电荷存储层(5)的深度；所述栅电极(81)的深度大于P型基区(6)的深度小于N型电荷存储层(5)的深度；所述栅电极(81)通过栅介质层(71)与N+发射区(9)、P+发射区(10)、P型基区(9)相连；所述栅电极(81)通过介质层(71)与分离栅电极(82)相连；所述分离栅电极(82)通过分离栅介质层(72)与P型埋层(13)、N型埋层(14)、P型掺杂层15相连，所述分离栅电极(82)通过介质层74与N型电荷存储层(5)、N-漂移区(4)相连，所述分离栅电极(81)呈L型包围住栅电极(81)，所述介质层(74)的厚度大于或等于栅介质层(71)的厚度；所述二极管(17)阳极与金属(16)相连，阴极与电阻(18)相连；所述电阻(18)一端与二极管阴极相连，另一端与发射极金属(12)相连。所述P型埋层(13)范围从与与栅介质层(72)接触一侧延伸到栅介质层(71)一侧。
3.根据权利要求1所述一种具有过流保护功能的IGBT，其特征在于，将二极管(17)集成到器件内部，二极管(17)由N+半导体(171)与P+半导体(172)构成。
4.根据权利要求2所述一种具有过流保护功能的IGBT，其特征在于，将接触金属(16)替换成肖特基接触金属(161)。
5.根据权利要求1所述一种具有过流保护功能的IGBT，其特征在于，将电阻(18)集成到器件内部，所述电阻(18)由多晶掺杂材料(21)、接触金属(22)构成。
6.根据权利要求2所述一种具有过流保护功能的IGBT，其特征在于，将P型掺杂层(15)、N型埋层(14)、P型埋层(13)部分替换成P型埋层(23)且串联2个二极管(17)。
7.根据权利要求1所述一种具有过流保护功能的IGBT，其特征在于，所述器件半导体材料采用Si、SiC、GaAs或者GaN,沟槽填充材料采用多晶Si、SiC、GaAs或者GaN，且各部分可以采用相同的材料也可采用不同材料组合。
8.根据权利要求1所述一种具有过流保护功能的IGBT，其特征在于，将器件背面的P型集电区(2)换为N+层，所述结构同样适用于MOSFET器件。
CN201910806529.5A 2019-08-29 2019-08-29 一种具有过流保护功能的igbt Active CN110444589B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910806529.5A CN110444589B (zh) 2019-08-29 2019-08-29 一种具有过流保护功能的igbt

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910806529.5A CN110444589B (zh) 2019-08-29 2019-08-29 一种具有过流保护功能的igbt

Publications (2)

Publication Number Publication Date
CN110444589A true CN110444589A (zh) 2019-11-12
CN110444589B CN110444589B (zh) 2021-03-16

Family

ID=68438267

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910806529.5A Active CN110444589B (zh) 2019-08-29 2019-08-29 一种具有过流保护功能的igbt

Country Status (1)

Country Link
CN (1) CN110444589B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111048594A (zh) * 2019-11-13 2020-04-21 电子科技大学 一种集成快恢复二极管的SiC功率器件
CN111403385A (zh) * 2020-03-02 2020-07-10 电子科技大学 一种具有内嵌肖特基二极管的rc-ligbt器件
CN116632052A (zh) * 2023-06-01 2023-08-22 上海林众电子科技有限公司 一种沟槽栅igbt器件及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557128A (en) * 1994-03-04 1996-09-17 Fuji Electric Co., Ltd. Insulated-gate type bipolar transistor
US20040012052A1 (en) * 2002-07-19 2004-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
CN107799582A (zh) * 2017-10-20 2018-03-13 电子科技大学 一种沟槽栅电荷储存型绝缘栅双极型晶体管及其制造方法
CN109585540A (zh) * 2018-12-04 2019-04-05 电子科技大学 一种具有载流子存储层的平面栅igbt器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557128A (en) * 1994-03-04 1996-09-17 Fuji Electric Co., Ltd. Insulated-gate type bipolar transistor
US20040012052A1 (en) * 2002-07-19 2004-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
CN107799582A (zh) * 2017-10-20 2018-03-13 电子科技大学 一种沟槽栅电荷储存型绝缘栅双极型晶体管及其制造方法
CN109585540A (zh) * 2018-12-04 2019-04-05 电子科技大学 一种具有载流子存储层的平面栅igbt器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PING LI ET AL: "A Low On-state Voltage and Saturation Current TIGBT With Self-Biased pMOS", 《IEEE ELECTRON DEVICE LETTERS》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111048594A (zh) * 2019-11-13 2020-04-21 电子科技大学 一种集成快恢复二极管的SiC功率器件
CN111048594B (zh) * 2019-11-13 2022-03-15 电子科技大学 一种集成快恢复二极管的SiC功率器件
CN111403385A (zh) * 2020-03-02 2020-07-10 电子科技大学 一种具有内嵌肖特基二极管的rc-ligbt器件
CN116632052A (zh) * 2023-06-01 2023-08-22 上海林众电子科技有限公司 一种沟槽栅igbt器件及其制备方法
CN116632052B (zh) * 2023-06-01 2024-02-09 上海林众电子科技有限公司 一种沟槽栅igbt器件及其制备方法

Also Published As

Publication number Publication date
CN110444589B (zh) 2021-03-16

Similar Documents

Publication Publication Date Title
CN110444589A (zh) 一种具有过流保护功能的igbt
CN103383958B (zh) 一种rc-igbt器件及其制作方法
CN105720094B (zh) 具有过载电流承载能力的半导体器件
CN105448901A (zh) 电子部件
EP3678190A1 (en) Semiconductor device
JPWO2017126167A1 (ja) 半導体装置
EP2822038B1 (en) Insulated gate bipolar transistor
CN109244136B (zh) 槽底肖特基接触SiC MOSFET器件
CN105206656A (zh) 一种逆导型igbt器件
CN104409519A (zh) 一种具有浮岛结构的二极管
US11282937B2 (en) Semiconductor device and power conversion device
CN110034176A (zh) 解决反向恢复失效的逆导型横向绝缘栅双极型晶体管
CN108735808A (zh) 半导体开关元件及其制造方法
CN110504259B (zh) 一种具有过流保护能力的横向igbt
CN116153992B (zh) 一种逆导型绝缘栅双极型晶体管
CN109904221B (zh) 一种超结双向开关
CN205211763U (zh) 一种高压肖特基二极管
CN107134488A (zh) 一种载流子存储增强的绝缘栅双极型晶体管
CN110504312B (zh) 一种具有短路自保护能力的横向igbt
CN213366606U (zh) 覆盖钝化层的mos控制整流器
Kitamura et al. Demonstration of the surge current capability of embedded SBDs in SiC SBD-integrated trench MOSFETs with a thick Cu block
CN114551586B (zh) 集成栅控二极管的碳化硅分离栅mosfet元胞及制备方法
CN106098799A (zh) 一种积累型沟槽二极管
CN103594490A (zh) 晶闸管及晶闸管封装件
CN109148572A (zh) 一种反向阻断型fs-gbt

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant