CN110444507A - Encapsulate the packaging method of cuticula and semiconductor devices - Google Patents
Encapsulate the packaging method of cuticula and semiconductor devices Download PDFInfo
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- CN110444507A CN110444507A CN201910754598.6A CN201910754598A CN110444507A CN 110444507 A CN110444507 A CN 110444507A CN 201910754598 A CN201910754598 A CN 201910754598A CN 110444507 A CN110444507 A CN 110444507A
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- film
- sub
- cuticula
- reflection layer
- encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Laminated Bodies (AREA)
Abstract
A kind of packaging method encapsulating cuticula and semiconductor devices, the encapsulation cuticula include: the first sub- film and the second sub- film of stacking, and the back side of the first sub- film and the positive opposite and mutual of the described second sub- film are pasted；Wherein, the front of the described first sub- film has viscosity；The first sub- film has multiple hollow holes.The present invention program can be when removing encapsulates cuticula, a possibility that surface material layer for reducing chip is stripped or breakage occurs.
Description
Technical field
The present invention relates to the encapsulation of technical field of semiconductor encapsulation more particularly to a kind of encapsulation cuticula and semiconductor devices
Method.
Background technique
In existing semiconductor packaging, following steps are generally included: then wafer be thinned again to passing through
The wafer (Wafer) of test carries out scribing process, and wafer is cut into small chip (Die), is then packaged to chip, shape
At chip (Chip).Further, it to packaged chip, can be grabbed one by one using mechanical arm.
It in the prior art, is to be affixed on front using blue film (Blue Tape) then to carry out the back side in thinning process
Grinding is thinned, and blue film must be removed after being thinned, however during removal, the surface material layer of chip is easy to happen damage.
By taking the chip is used to prepare imaging sensor as an example, the top surface of described image sensor is often antireflection
Layer ((Anti Reflect Coating, ARC).Specifically, the surface of the anti-reflection layer is relatively smooth, it is easy to clean to go
Except falling in the particulate matter (Particle) of chip surface, and it is capable of providing preferable light transmittance, improves the product of imaging sensor
Matter.
However, in removing blue membrane process, it is easy to uncover the anti-reflection layer part or local damage, seriously affects production
Quality.
Summary of the invention
The technical problem to be solved by the present invention is to provide the packaging method of a kind of encapsulation cuticula and semiconductor devices, Ke Yi
When removing encapsulation cuticula, a possibility that surface material layer for reducing chip is stripped or breakage occurs.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of encapsulation cuticula, comprising: the sub- film of the first of stacking with
And the second sub- film, the back side of the first sub- film and the front of the described second sub- film are opposite and paste mutually；Wherein, described first
The front of sub- film has viscosity；The first sub- film has multiple hollow holes.
Optionally, the shape of described hole is selected from one or more of: round, ellipse, polygon and irregular
Figure.
Optionally, the sum of area of the multiple hole is S1, and the bonding area of the first sub- film and anti-reflection layer is
S2；Wherein, the ratio of the S1 and S2 is selected from: 20%~80%.
Optionally, the area of each hole and the ratio of S2 are selected from: 0.01%~10%.
Optionally, described hole is arranged in array.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of packaging method of semiconductor devices, comprising: provide
The surface of semiconductor devices, the semiconductor devices is formed with anti-reflection layer；The envelope is placed on the surface of the anti-reflection layer
Fill cuticula, it is described encapsulation cuticula just facing towards the anti-reflection layer；Wherein, the front of the described first sub- film is encapsulation shield
The front of film.
Optionally, the viscosity between the described first sub- film and the second sub- film is more than or equal to the described first sub- film and anti-reflection layer
Between viscosity.
Optionally, the anti-reflection layer surface place encapsulation cuticula include: provide respectively the described first sub- film and
Second sub- film；The first sub- film described in the surface mount of the anti-reflection layer；Described the is pasted at the back side of the described first sub- film
Two sub- films.
Optionally, placing encapsulation cuticula on the surface of the anti-reflection layer includes: to provide front relatively and paste mutually
First sub- film and the second sub- film；The front described in the surface mount of the anti-reflection layer is opposite and the first sub- film for pasting mutually
And the second sub- film.
Optionally, the material of the anti-reflection layer is silica, silicon nitride, silicon oxynitride.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In embodiments of the present invention, the first sub- film for encapsulating cuticula by setting, and encapsulating cuticula has multiple hollow
Hole can reduce the adhesive force for being attached to anti-reflection layer surface, and then removing after it will encapsulate cuticula and anti-reflection layer stickup
When encapsulating cuticula, a possibility that surface material layer for reducing chip is stripped or breakage occurs.
Further, the described first sub- film can be to paste in advance with the second sub- film and be integrated, and provides together and adheres to wafer
Above, to help to reduce the time expended in semiconductor fabrication process.
Further, the described first sub- film can be with the second sub- film and provide respectively, paste above wafer one by one, thus
It can be controlled separately the sticking Quality of each straton film, improve process controllability.
Detailed description of the invention
Fig. 1 to Fig. 2 be in the prior art it is a kind of encapsulate cuticula operative scenario schematic diagram；
Fig. 3 is a kind of top view of first sub- film in the embodiment of the present invention；
Fig. 4 is sectional view of the Fig. 3 along cutting line A1-A2；
Fig. 5 is a kind of top view of second sub- film in the embodiment of the present invention；
Fig. 6 is the sectional view of the first sub- film and the second sub- film of a kind of stacking in the embodiment of the present invention；
Fig. 7 to Fig. 8 is a kind of operative scenario schematic diagram for encapsulating cuticula in the embodiment of the present invention；
Fig. 9 is a kind of flow chart of the packaging method of semiconductor devices in the embodiment of the present invention.
Specific embodiment
As previously mentioned, being to be affixed on front then using blue film (Blue Tape) in thinning process in the prior art
The grinding for carrying out the back side is thinned, and blue film must be removed after being thinned, however during removal, the surface material layer of chip is easy to happen
Damage.
In conjunction with referring to Fig.1 and Fig. 2, Fig. 1 to Fig. 2 be in the prior art it is a kind of encapsulate cuticula operative scenario schematic diagram.
In a kind of forming process of image sensor chip, semiconductor substrate 100 is provided, in semiconductor substrate 100
Surface forms filter 110, forms lens arrangement 120 on the surface of filter 110.
It should be pointed out that the lens arrangement 120 may include multiple convex lens, it can also include relatively flat
The lens material layer that region is formed.
And then anti-reflection layer 130 is formed on the surface of lens arrangement 120.
Further, encapsulation cuticula 140 is provided, the one side of encapsulation cuticula 140 towards the anti-reflection layer 130 has
Viscosity.
Specifically, will use encapsulation cuticula 140 makes it cling chip so that processing is made in packaging technology, adding
When work finishes, it is necessary to remove the encapsulation cuticula 140.
However, often starting anti-reflection layer 130 during dyestripping, cause to remove when serious, so that influencing chip
Quality.
The present inventor has found after study, conventionally, as encapsulation cuticula 140 and anti-reflection layer 130
Stickup is more close, so causing when removing encapsulates cuticula 140, it is difficult to anti-reflection layer 130 be made to be retained in lens arrangement 120
Surface.A kind of encapsulation cuticula is needed, the position of anti-reflection layer 130 can be kept to stablize in removing, reduce by 130 quilt of anti-reflection layer
A possibility that damaged, occurs for removing.
In embodiments of the present invention, the first sub- film for encapsulating cuticula by setting, and encapsulating cuticula has multiple hollow
Hole can reduce the adhesive force for being attached to anti-reflection layer surface, and then removing after it will encapsulate cuticula and anti-reflection layer stickup
When encapsulating cuticula, a possibility that surface material layer for reducing chip is stripped or breakage occurs.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
In conjunction with being a kind of top view of first sub- film in the embodiment of the present invention referring to Fig. 3 and Fig. 4, Fig. 3, Fig. 4 is the edge Fig. 3
The sectional view of cutting line A1-A2.
Specifically, the front of the described first sub- film 241 can have viscosity, and the first sub- film 241 can have multiple
Hollow hole 2411.
In specific implementation, the material of the described first sub- film 241 can use existing suitable material, the embodiment of the present invention
It is without limitation.
Further, the shape of described hole 2411 can be selected from one or more of: round, ellipse, polygon
And irregular figure.
In a kind of specific embodiment of the embodiment of the present invention, the shape of described hole 2411 can be circle, with
When removing the first sub- film 241, since the profile of circular hole 2411 is round and smooth, it is damaged to help avoid the first sub- film 241.
In another specific embodiment of the embodiment of the present invention, the shape of described hole 2411 can be ellipse,
And compared to short internal diameter direction, the long internal diameter direction and peeling direction of the ellipse are more consistent, so as in removing institute
When stating the first sub- film 241, since the profile of the hole 2411 of ellipse is round and smooth, further helps in and avoid the first sub- film 241 broken
Damage.
Further, the sum of area of the multiple hole 2411 is S1, and the first sub- film 241 is viscous with anti-reflection layer
Veneer product is that the ratio of S2, the S1 and S2 can be selected from: 20%~80%.
It should be pointed out that the ratio of the S1 and S2 should not be excessive, the area that otherwise hole 2411 occupies is excessive, holds
Easily lead to sticky deficiency；The ratio of the S1 and S2 should not be excessive, and the area that otherwise hole 2411 occupies is too small, is easy to cause
Adhesive force is still excessively high, still remains a possibility that anti-reflection layer is stripped or breakage occurs.
As a unrestricted example, the ratio that S1 and S2 can be set can be selected from: 20%~80%, in this hair
In a kind of concrete application of bright embodiment, the ratio that S1 and S2 can be set is 40%~60%, for example, 50%.
Further, the area of each hole 2411 and the ratio of S2 can be selected from: 0.01%~10%.
The ratio of the area and S2 that are pointed out that each hole 2411 should not be excessive, otherwise single hole 2411
The area of occupancy is excessive, is easy to cause the when removing first sub- film 241 that breakage occurs；The area of each hole 2411 and the ratio of S2
Value should not be too small, and the area that otherwise single hole 2411 occupies is too small, is easy to cause adhesive force still excessively high, still remains anti-
A possibility that reflecting layer is stripped or breakage occurs.
Ratio as a unrestricted example, area and S2 that each hole 2411 can be set can be selected from:
0.01%~10%, in a kind of concrete application of the embodiment of the present invention, the area and S2 of each hole 2411 can be set
Ratio is 0.1%~1%, for example, 0.05%.
Further, described hole 2411 can be arranged in array.
In embodiments of the present invention, it can be arranged in array by the way that hole 2411 is arranged, point of hole 2411 can be made
Cloth more have orderliness and more uniformly, help not only to be easily peeled off when removing the first sub- film 241 but also effectively prevent making first
Breakage occurs for sub- film 241.
It is a kind of top view of second sub- film in the embodiment of the present invention referring to Fig. 5, Fig. 5.
Wherein, the described second sub- film 242 can be complete cuticula.
In specific implementation, the material of the described second sub- film 242 can use existing suitable material, the embodiment of the present invention
It is without limitation.
Referring to Fig. 6, Fig. 6 is the sectional view of the first sub- film and the second sub- film of a kind of stacking in the embodiment of the present invention.
It specifically, can be opposite and viscous mutually by the front at the back side of the described first sub- film 241 and the described second sub- film 242
Patch encapsulates cuticula 240 to be formed.
In specific implementation, the back side that the first sub- film 241 can be set has viscosity, and the second sub- film 242 can also be arranged
Front there is viscosity, the front of the back side that the first sub- film 241 can also be arranged and the second sub- film 242 all has viscosity.
It is a kind of operative scenario signal for encapsulating cuticula in the embodiment of the present invention in conjunction with reference Fig. 7 and Fig. 8, Fig. 7 to Fig. 8
Figure.
In a kind of forming process of image sensor chip, semiconductor substrate 200 is provided, in semiconductor substrate 200
Surface forms filter 210, forms lens arrangement 220 on the surface of filter 210.
It should be pointed out that the lens arrangement 220 may include multiple convex lens, it can also include relatively flat
The lens material layer that region is formed.
And then anti-reflection layer 230 is formed on the surface of lens arrangement 220.
Further, the material of the anti-reflection layer 230 can be silica, silicon nitride, silicon oxynitride.
Wherein, compared to the top surface of lens arrangement 220, the surface of anti-reflection layer 230 is relatively smooth, is easy subsequent
Cleaning removal falls in the particulate matter on its surface in technique, and is capable of providing preferable light transmittance, improves the product of imaging sensor
Matter.
And then encapsulation cuticula 240 as shown in Figure 6 is provided, the front of the encapsulation cuticula 240 has viscosity and towards institute
State anti-reflection layer 230.
Specifically, the front of the first sub- film 241 is the front of the encapsulation cuticula 240.
Further, by the encapsulation cuticula 240 be placed in it is described put the surface in reflecting layer 230, and then be packaged
After the operation of technique, the encapsulation cuticula 240 is removed.
In a kind of concrete application of the embodiment of the present invention, as shown in figure 8, after removing encapsulates cuticula 240, anti-reflection layer
230 still keep the fit-state with lens arrangement.
In embodiments of the present invention, the first sub- film 241 for encapsulating cuticula 240 by setting, and encapsulating cuticula 240 has more
A hollow hole, can be after it will encapsulate cuticula 240 and the stickup of anti-reflection layer 230, and reduction is attached to 230 surface of anti-reflection layer
Adhesive force, and then when removing cuticula, reduce a possibility that anti-reflection layer 230 is stripped or breakage occurs.
Referring to Fig. 9, Fig. 9 is a kind of flow chart of the packaging method of semiconductor devices in the embodiment of the present invention.The method
May include step S91 to step S92:
Step S91: semiconductor devices is provided, the surface of the semiconductor devices is formed with anti-reflection layer；
Step S92: encapsulation cuticula is placed on the surface of the anti-reflection layer, the encapsulation cuticula is just prevented facing towards described
Reflecting layer.
Wherein, the front of the described first sub- film is the front of the encapsulation cuticula.
It further, may include: to provide front relatively the step of encapsulation cuticula is placed on the surface of the anti-reflection layer
And the first sub- film and the second sub- film pasted mutually；The front described in the surface mount of the anti-reflection layer is opposite and viscous mutually
The the first sub- film and the second sub- film of patch.
In embodiments of the present invention, the described first sub- film can be to paste in advance with the second sub- film and be integrated, and provide together
And adhere to above wafer, to help to reduce the time expended in semiconductor fabrication process.
It further, may include: described in offer respectively the step of encapsulation cuticula is placed on the surface of the anti-reflection layer
First sub- film and the second sub- film；The first sub- film described in the surface mount of the anti-reflection layer；In the back of the described first sub- film
Paste the second sub- film in face.
In embodiments of the present invention, the described first sub- film can be with the second sub- film and provide respectively, paste wafer one by one
Above, so as to control the sticking Quality of each straton film respectively, process controllability is improved.
Further, the viscosity between the described first sub- film and the second sub- film is more than or equal to the described first sub- film and antireflection
Viscosity between layer.
In embodiments of the present invention, it is more than or equal to described first by the viscosity between the described first sub- film and the second sub- film
Viscosity between sub- film and anti-reflection layer can further decrease the first sub- film and anti-reflection layer be removed or generated damaged possibility
Property.
In embodiments of the present invention, the first sub- film for encapsulating cuticula by setting, and encapsulating cuticula has multiple hollow
Hole can reduce the adhesive force for being attached to anti-reflection layer surface, and then removing after it will encapsulate cuticula and anti-reflection layer stickup
When encapsulating cuticula, a possibility that surface material layer for reducing chip is stripped or breakage occurs.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of encapsulation cuticula characterized by comprising
The the first sub- film and the second sub- film stacked, the back side of the first sub- film and the front of the described second sub- film are opposite and mutual
Mutually paste；
Wherein, the front of the described first sub- film has viscosity；
The first sub- film has multiple hollow holes.
2. encapsulation cuticula according to claim 1, which is characterized in that
The shape of described hole is selected from one or more of: round, ellipse, polygon and irregular figure.
3. encapsulation cuticula according to claim 1, which is characterized in that
The sum of area of the multiple hole is S1, and the bonding area of the first sub- film and anti-reflection layer is S2；
Wherein, the ratio of the S1 and S2 is selected from: 20%~80%.
4. encapsulation cuticula according to claim 3, which is characterized in that
The area of each hole and the ratio of S2 are selected from: 0.01%~10%.
5. encapsulation cuticula according to claim 1, which is characterized in that
Described hole is arranged in array.
6. a kind of packaging method of semiconductor devices characterized by comprising
Semiconductor devices is provided, the surface of the semiconductor devices is formed with anti-reflection layer；
Any one of claim 1 to 5 encapsulation cuticula, the front of the encapsulation cuticula are placed on the surface of the anti-reflection layer
Towards the anti-reflection layer；
Wherein, the front of the described first sub- film is the front of the encapsulation cuticula.
7. the packaging method of semiconductor devices according to claim 6, which is characterized in that
Viscosity between the first sub- film and the second sub- film is more than or equal to the viscosity between the described first sub- film and anti-reflection layer.
8. the packaging method of semiconductor devices according to claim 6, which is characterized in that on the surface of the anti-reflection layer
Placing encapsulation cuticula includes:
Described first sub- film and the second sub- film are provided respectively；
The first sub- film described in the surface mount of the anti-reflection layer；
The second sub- film is pasted at the back side of the described first sub- film.
9. the packaging method of semiconductor devices according to claim 6, which is characterized in that on the surface of the anti-reflection layer
Placing encapsulation cuticula includes:
The the first sub- film and the second sub- film that front is opposite and pastes mutually are provided；
The front described in the surface mount of the anti-reflection layer is opposite and the first sub- film and the second sub- film pasted mutually.
10. the packaging method of semiconductor devices according to claim 6, which is characterized in that
The material of the anti-reflection layer is silica, silicon nitride, silicon oxynitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910754598.6A CN110444507A (en) | 2019-08-15 | 2019-08-15 | Encapsulate the packaging method of cuticula and semiconductor devices |
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| CN102897708A (en) * | 2011-07-29 | 2013-01-30 | 美新半导体（无锡）有限公司 | Cutting method for MEMS wafer |
| CN106711091A (en) * | 2017-01-20 | 2017-05-24 | 中国科学院微电子研究所 | MEMS wafer cutting method and MEMS chip manufacturing method |
| CN109994390A (en) * | 2019-04-09 | 2019-07-09 | 深圳市圆方科技新材料有限公司 | A kind of pre-packaged method of chip |
-
2019
- 2019-08-15 CN CN201910754598.6A patent/CN110444507A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165371A (en) * | 2005-12-09 | 2007-06-28 | Toshiba Corp | Method of manufacturing semiconductor device |
| CN102120560A (en) * | 2010-01-12 | 2011-07-13 | 南茂科技股份有限公司 | Cutting method for micro-electro-mechanical wafer |
| CN102897708A (en) * | 2011-07-29 | 2013-01-30 | 美新半导体（无锡）有限公司 | Cutting method for MEMS wafer |
| CN106711091A (en) * | 2017-01-20 | 2017-05-24 | 中国科学院微电子研究所 | MEMS wafer cutting method and MEMS chip manufacturing method |
| CN109994390A (en) * | 2019-04-09 | 2019-07-09 | 深圳市圆方科技新材料有限公司 | A kind of pre-packaged method of chip |
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Application publication date: 20191112 |