CN116053126A - Ultrathin chip plasma cutting process - Google Patents
Ultrathin chip plasma cutting process Download PDFInfo
- Publication number
- CN116053126A CN116053126A CN202310063270.6A CN202310063270A CN116053126A CN 116053126 A CN116053126 A CN 116053126A CN 202310063270 A CN202310063270 A CN 202310063270A CN 116053126 A CN116053126 A CN 116053126A
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- China
- Prior art keywords
- wafer
- cutting
- photoresist
- adhesive
- temporary bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000005520 cutting process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 239000000853 adhesive Substances 0.000 claims abstract description 17
- 230000001070 adhesive effect Effects 0.000 claims abstract description 17
- 238000000227 grinding Methods 0.000 claims abstract description 17
- 239000003292 glue Substances 0.000 claims abstract description 16
- 239000002390 adhesive tape Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 6
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000004026 adhesive bonding Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 claims abstract description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000006303 photolysis reaction Methods 0.000 claims description 3
- 230000015843 photosynthesis, light reaction Effects 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 239000000084 colloidal system Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a plasma cutting process of an ultrathin chip, and relates to the technical field of chip cutting; the method comprises the following steps: photoetching, gluing, exposing and developing the wafer; reserving the photoresist of the circuit area, and removing the photoresist above the cutting; coating temporary bonding glue, and fully filling gaps of the cutting channels by the glue; sticking a back grinding adhesive tape; thinning the wafer, and attaching the thinned wafer to a iron ring with a cutting film; removing the adhesive from the temporary bonding adhesive by laser, removing the back grinding adhesive tape, and then cleaning the adhesive to clean the adhesive in the gap of the cutting channel; and removing the silicon layer and the photoresist in the dicing channel area from the thinned wafer to achieve the effect of separating DIE and DIE dicing. Through increasing the temporary bonding technology, utilize the temporary bonding glue to fill the cutting way gap, guarantee that grinding sticky tape attached can not form the sunken region on a plane, guarantee that follow-up grinding attenuate can be with the wafer attenuate to limit thickness, reduce the risk that the wafer breaks.
Description
Technical Field
The invention relates to the technical field of chip cutting, in particular to a plasma cutting process for an ultrathin chip.
Background
The chip size of the integrated circuit is continuously reduced, the chip size is smaller and smaller, and the too small size cannot be cut and separated by using a conventional blade and laser in the wafer packaging process, so that the wafer needs to be cut and separated by using a gas plasma cutting mode.
The conventional process flow is to apply photoresist on the front surface of a wafer (fig. 1-3) for photoetching, expose the dicing channel area through exposure and development, etch and remove the silicon layer of the dicing channel area through gas etching, and then clean and remove the photoresist to realize DIE separation of the wafer.
Defects of the prior art are as follows: because the back grinding adhesive tape is attached to the photoresist, the problem that the back grinding adhesive tape is concave exists in the cutting area, the silicon layer is removed by applying quite large external force when the wafer is thinned, the concave area can form larger stress due to unevenness, and when the wafer thinning degree is larger, the concave area of the grinding adhesive tape can form larger stress due to unevenness, so that the ground ultrathin wafer is extremely easy to crack.
Therefore, the invention provides a plasma cutting process for ultrathin chips
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides an ultrathin chip plasma cutting process.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a plasma cutting process of an ultrathin chip comprises the following steps:
s1: photoetching, gluing, exposing and developing the wafer; reserving the photoresist of the circuit area, and removing the photoresist above the cutting channel;
s2: coating temporary bonding glue, and fully filling gaps of the cutting channels by the glue;
s3: sticking a back grinding adhesive tape;
s4: thinning the wafer, and attaching the thinned wafer to a iron ring with a cutting film;
s5: removing the adhesive from the temporary bonding adhesive by laser, removing the back grinding adhesive tape, and then cleaning the adhesive to clean the adhesive in the gap of the cutting channel;
s6: and removing the silicon layer and the photoresist in the dicing channel area from the thinned wafer to achieve the effect of separating DIE and DIE dicing.
Preferably: in the step S1, the thickness of the photoresist is 10-30 mu m.
Preferably: in the step S2, the thickness of the colloid is 10-30 mu m.
Preferably: in S2, the temporary bonding glue is coated by using a high-speed rotating coating method.
Preferably: in the step S3, the thickness is reduced to 30-50 mu m during the thinning.
Preferably: in the step S5, the bonding glue is removed by laser photolysis.
Preferably: in S5, the photoresist is ensured to remain on the wafer during cleaning.
Preferably: in S6, the method for removing the silicon layer uses a plasma dry etching.
Preferably: in the step S6, the photoresist is removed by a wet method.
The beneficial effects of the invention are as follows:
1. according to the invention, by adding the temporary bonding process and filling the cutting channel gap with the temporary bonding adhesive, the grinding adhesive tape is attached on a plane without forming a concave area, the wafer can be thinned to the limit thickness by subsequent grinding thinning, and the risk of wafer breakage is reduced.
Drawings
FIGS. 1-3 are schematic diagrams of prior art processes;
fig. 4 is a schematic structural diagram of step S1 in the ultra-thin chip plasma dicing process according to the present invention;
fig. 5 is a schematic structural diagram of step S2 in the ultra-thin chip plasma dicing process according to the present invention;
fig. 6 is a schematic structural diagram of step S3 in the ultra-thin chip plasma dicing process according to the present invention;
fig. 7 is a schematic structural diagram of step S4 in the ultra-thin chip plasma dicing process according to the present invention;
fig. 8 is a schematic structural diagram of step S5 in the ultra-thin chip plasma dicing process according to the present invention;
fig. 9 is a schematic structural diagram of step S6 in the ultra-thin chip plasma dicing process according to the present invention.
Detailed Description
The technical scheme of the patent is further described in detail below with reference to the specific embodiments.
In the description of this patent, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "disposed" are to be construed broadly, and may be fixedly connected, disposed, detachably connected, disposed, or integrally connected, disposed, for example. The specific meaning of the terms in this patent will be understood by those of ordinary skill in the art as the case may be.
Example 1:
an ultrathin chip plasma cutting process, as shown in figures 1-8, comprises the following steps:
s1: photoetching, gluing, exposing and developing the wafer; reserving the photoresist of the circuit area, and removing the photoresist above the cutting channel;
s2: coating temporary bonding glue, and fully filling gaps of the cutting channels by the glue;
s3: sticking a back grinding adhesive tape;
s4: thinning the wafer, and attaching the thinned wafer to a iron ring with a cutting film;
s5: removing the adhesive from the temporary bonding adhesive by laser, removing the back grinding adhesive tape, and then cleaning the adhesive to clean the adhesive in the gap of the cutting channel;
s6: and removing the silicon layer and the photoresist in the dicing channel area from the thinned wafer to achieve the effect of separating DIE and DIE dicing.
Example 2:
as shown in fig. 1-8, the plasma dicing process for ultra-thin chips is improved in embodiment 1: in the step S1, the thickness of the photoresist is 10-30 mu m.
In the step S2, the thickness of the colloid is 10-30 mu m.
In S2, the temporary bonding glue is coated by using a high-speed rotating coating method.
In the step S3, the thickness is reduced to 30-50 mu m during the thinning.
In the step S5, the bonding glue is removed by laser photolysis.
In S5, the photoresist is ensured to remain on the wafer during cleaning.
In S6, the method for removing the silicon layer uses a plasma dry etching.
In the step S6, the photoresist is removed by a wet method.
The invention comprises the following steps: through increasing the temporary bonding technology, utilize the temporary bonding to glue and fill the cutting way gap, guarantee that grinding sticky tape attached can not form the sunken region on a plane, guarantee that follow-up grinding attenuate can be with the wafer thickness limit (30 um ~ 50 um), reduce the risk that the wafer breaks.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (9)
1. The ultrathin chip plasma cutting process is characterized by comprising the following steps of:
s1: photoetching, gluing, exposing and developing the wafer; reserving the photoresist of the circuit area, and removing the photoresist above the cutting channel;
s2: coating temporary bonding glue, and fully filling gaps of the cutting channels by the glue;
s3: sticking a back grinding adhesive tape;
s4: thinning the wafer, and attaching the thinned wafer to a iron ring with a cutting film;
s5: removing the adhesive from the temporary bonding adhesive by laser, removing the back grinding adhesive tape, and then cleaning the adhesive to clean the adhesive in the gap of the cutting channel;
s6: and removing the silicon layer and the photoresist in the dicing channel area from the thinned wafer to achieve the effect of separating DIE and DIE dicing.
2. The ultra-thin chip plasma dicing process of claim 1, wherein in S1, the photoresist thickness is 10-30 μm.
3. The ultra-thin chip plasma dicing process of claim 1, wherein in S2, the gel thickness is 10-30 μm.
4. The process of claim 3, wherein in S2, the temporary bonding glue is applied by a high-speed spin coating method.
5. The ultra-thin chip plasma dicing process of claim 1, wherein in S3, the thickness is reduced to 30-50 μm.
6. The process of claim 1, wherein in S5, the bonding glue is removed by laser photolysis.
7. The ultra-thin chip plasma dicing process of claim 6, wherein in S5, the photoresist is kept on the wafer during cleaning.
8. The ultra-thin chip plasma dicing process of claim 1, wherein in S6, the silicon layer is removed by plasma dry etching.
9. The ultra-thin chip plasma dicing process of claim 8, wherein in S6, the photoresist is removed by wet method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310063270.6A CN116053126A (en) | 2023-01-16 | 2023-01-16 | Ultrathin chip plasma cutting process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310063270.6A CN116053126A (en) | 2023-01-16 | 2023-01-16 | Ultrathin chip plasma cutting process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116053126A true CN116053126A (en) | 2023-05-02 |
Family
ID=86127175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310063270.6A Pending CN116053126A (en) | 2023-01-16 | 2023-01-16 | Ultrathin chip plasma cutting process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116053126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117219502A (en) * | 2023-11-07 | 2023-12-12 | 天通控股股份有限公司 | Single-sided thinning method of bonding wafer |
-
2023
- 2023-01-16 CN CN202310063270.6A patent/CN116053126A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117219502A (en) * | 2023-11-07 | 2023-12-12 | 天通控股股份有限公司 | Single-sided thinning method of bonding wafer |
| CN117219502B (en) * | 2023-11-07 | 2024-01-12 | 天通控股股份有限公司 | Single-sided thinning method of bonding wafer |
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