CN110416232B - Array substrate, manufacturing method thereof, display panel and display device - Google Patents
Array substrate, manufacturing method thereof, display panel and display device Download PDFInfo
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- CN110416232B CN110416232B CN201910779054.5A CN201910779054A CN110416232B CN 110416232 B CN110416232 B CN 110416232B CN 201910779054 A CN201910779054 A CN 201910779054A CN 110416232 B CN110416232 B CN 110416232B
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- 239000000758 substrate Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 123
- 239000001301 oxygen Substances 0.000 claims abstract description 123
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 123
- 239000010409 thin film Substances 0.000 claims abstract description 74
- 238000000151 deposition Methods 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 239000012495 reaction gas Substances 0.000 claims description 6
- 210000003168 insulating cell Anatomy 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 23
- 238000000137 annealing Methods 0.000 description 10
- 230000001502 supplementing effect Effects 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the application provides an array substrate, a manufacturing method of the array substrate, a display panel and a display device. The array substrate includes a driving thin film transistor region and a switching thin film transistor region, and includes: a substrate base plate; a light shielding layer on the substrate and including multiple light shielding structures in the driving TFT region; a first oxygen-containing buffer layer on the light-shielding layer; the second oxygen-containing buffer layer is positioned on the first oxygen-containing buffer layer, has higher oxygen content than the first oxygen-containing active layer and comprises a plurality of second oxygen-containing buffer units positioned in the driving thin film transistor area; and the active layer comprises a plurality of active islands, each active island comprises a first active island positioned in the area of the driving thin film transistor and a second active island positioned in the area of the switching thin film transistor, the first active island is positioned on the second oxygen-containing buffer unit, and the second active island is positioned on the first oxygen-containing buffer layer. The embodiment can improve the uniformity of the threshold voltage of the array substrate, thereby improving the display quality of the display panel.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel and a display device.
Background
The thin film transistor with the Top Gate structure (Top Gate) has the advantages of lower parasitic capacitance, better refreshing frequency, shorter channel, smaller size and the like, and can better meet the development requirements of high definition and high refreshing frequency of the display panel.
In order to improve the stability of a Top Gate structured driving thin Film Transistor (DR TFT), a light blocking structure is provided below the DR TFT, and a light blocking structure is not provided below a switching thin Film Transistor (SW TFT). The light shielding structures can lead the buffer layer to be heated unevenly in the subsequent annealing process, so that the oxygen supplementing capacity of the buffer layer below the DR TFT to the active layer of the DR TFT is different from the oxygen supplementing capacity of the buffer layer below the SW TFT to the active layer of the SW TFT. This causes the difference in threshold voltage (Vth) between the DR TFT and the SW TFT, which affects the uniformity of Vth of the entire array substrate, so that some TFTs of the display panel may not be turned on normally under some conditions, thereby reducing the display quality of the display panel.
Disclosure of Invention
The application provides an array substrate, a manufacturing method thereof, a display panel and a display device aiming at the defects of the existing mode, and aims to solve the technical problem that threshold voltages (Vth) of DR TFT and SW TFT are different due to the fact that a shading structure exists in the prior art.
In a first aspect, an embodiment of the present application provides an array substrate including a driving thin film transistor region and a switching thin film transistor region, the array substrate including:
a substrate base plate;
the shading layer is positioned on the substrate and comprises a plurality of shading structures positioned in the driving thin film transistor area;
a first oxygen-containing buffer layer on the light-shielding layer;
the second oxygen-containing buffer layer is positioned on the first oxygen-containing buffer layer and comprises a plurality of second oxygen-containing buffer units positioned in the driving thin film transistor area;
an active layer including a plurality of active islands, the active islands including a plurality of first active islands located in the driving thin film transistor region and a plurality of second active islands located in the switching thin film transistor region, the first active islands being located on the second oxygen-containing buffer units, the second active islands being located on the first oxygen-containing buffer layers;
wherein the oxygen content of the first oxygen-containing buffer layer is lower than the oxygen content of the second oxygen-containing buffer layer.
Optionally, the material of the first oxygen-containing buffer layer and the material of the second oxygen-containing buffer layer are both silicon oxide materials.
Optionally, the thickness of the first oxygen-containing buffer layer is 300nm-500 nm; the thickness of the second oxygen-containing buffer layer is 100nm-300 nm.
Optionally, the material of the active layer comprises one or a combination of indium gallium zinc oxide, indium zinc oxide and indium tin zinc oxide.
Optionally, the array substrate further includes:
a first insulating layer including a plurality of first insulating cells on the active island;
a first metal layer including a plurality of gates on the first insulating unit;
the second insulating layer is positioned on the first metal layer and comprises a plurality of through holes penetrating through the second insulating layer;
and the second metal layer comprises a plurality of sources and a plurality of drains, wherein the sources and the drains are respectively connected with the corresponding active islands through the through holes.
In a second aspect, an embodiment of the present application provides a display panel, including the array substrate.
In a third aspect, an embodiment of the present application provides a display device, including the display panel described above.
In a fourth aspect, an embodiment of the present application provides a method for manufacturing an array substrate, where the array substrate includes a driving thin film transistor region and a switching thin film transistor region, and the method includes:
depositing a shading layer on a substrate, and carrying out graphical processing on the shading layer to obtain a plurality of shading structures positioned in the driving thin film transistor area;
depositing a first oxygen-containing buffer layer on the light-shielding layer;
depositing a second oxygen-containing buffer layer on the first oxygen-containing buffer layer, and performing graphical processing on the second oxygen-containing buffer layer to form a second oxygen-containing buffer unit positioned in the driving thin film transistor area;
depositing an active layer, and performing patterning processing on the active layer to obtain a plurality of active islands, wherein the active islands include a plurality of first active islands located in the driving thin film transistor area and a plurality of second active islands located in the switching thin film transistor area, the first active islands are located on the second oxygen-containing buffer units, and the second active islands are located on the first oxygen-containing buffer layers;
wherein the oxygen content of the first oxygen-containing buffer layer is lower than the oxygen content of the second oxygen-containing buffer layer.
Optionally, the depositing a first oxygen-containing buffer layer on the light shielding layer includes: controlling the reaction gas N2O and SiH4Depositing the first oxygen-containing buffer layer on the light-shielding layer at a first ratio;
said depositing a second oxygen-containing buffer layer on said first oxygen-containing buffer layer comprises: controlling the reaction gas N2O and SiH4Depositing the second oxygen-containing buffer layer on the light-shielding layer at a second ratio;
wherein the first ratio is less than the second ratio.
Optionally, the manufacturing method further includes:
depositing a first insulating layer on the active layer, and performing patterning on the first insulating layer to form a plurality of first insulating units, wherein the first insulating units are positioned on the active islands;
depositing a first metal layer on the first insulating layer, and performing patterning processing on the first metal layer to form a gate electrode on the first insulating unit;
depositing a second insulating layer on the first metal layer, and carrying out patterning treatment on the second insulating layer to form a through hole penetrating through the second insulating layer;
and depositing a second metal layer on the second insulating layer, and performing graphical processing on the second metal layer to form a plurality of source electrodes and a plurality of drain electrodes, wherein the source electrodes and the drain electrodes are respectively connected with the corresponding active islands through the via holes.
The technical scheme provided by the embodiment of the application has the following beneficial technical effects:
in the array substrate, the manufacturing method thereof, the display panel and the display device provided by the embodiment, since the active layer below the first active island is affected by more heat due to the existence of the light shielding structure in the annealing process, by making the oxygen content of the buffer layer under the first active island higher than the oxygen content of the buffer layer under the second active island, it is possible to, after annealing, so that the oxygen supplementing capacity of the buffer layer below the first active island to the first active island is approximately the same as the oxygen supplementing capacity of the buffer layer below the second active island to the second active island, thereby reducing the difference between the threshold voltage of the driving thin film transistor and the threshold voltage of the switching thin film transistor, improving the uniformity of the threshold voltage of the entire array substrate, and then avoided the display panel in some circumstances partial thin-film transistor can't normally turn on the condition, improved the display quality of display panel.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional view of another array substrate provided in an embodiment of the present application;
fig. 3 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart illustrating a step S1 in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart illustrating a step S2 in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart illustrating a step S3 in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic flowchart illustrating a step S4 in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic flowchart illustrating a step S5 in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic flowchart illustrating a step S6 in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 10 is a schematic flowchart illustrating a step S7 in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic flowchart of step S8 in the method for manufacturing an array substrate according to the embodiment of the present application.
Description of the drawings:
1-a substrate base plate;
2-a light-shielding layer; 21-a light-shielding structure;
3-a first oxygen containing buffer layer;
4-a second oxygen-containing buffer layer; 41-a second oxygen-containing buffer unit;
5-an active layer; 51-active islands; 511-a first active island; 512-second active island;
6-a first insulating layer; 61-a first insulating unit;
7-a first metal layer; 71-a gate;
8-a second insulating layer; 81-via holes;
9-a second metal layer; 91-source electrode; 92-a drain electrode;
a-a driving thin film transistor region; b-switching the thin film transistor region.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
In order to improve the stability of a Top Gate structured driving thin Film Transistor (DR TFT), a light blocking structure is provided below the DR TFT, and a light blocking structure is not provided below a switching thin Film Transistor (SW TFT).
However, the inventors of the present application consider that the buffer layer is heated unevenly in the subsequent annealing process due to the light shielding structures, so that the oxygen supplement capability of the buffer layer under the DR TFT to the active layer of the DR TFT is different from the oxygen supplement capability of the buffer layer under the SW TFT to the active layer of the SW TFT. This causes the threshold voltage (Vth) of the DR TFT and the SW TFT to be different (normally, the threshold voltage of the DR TFT is lower than the threshold voltage of the SW TFT), which affects the uniformity of the entire array substrate Vth, so that in some cases, some TFTs of the display panel cannot be turned on normally, thereby reducing the display quality of the display panel.
The application provides an array substrate, a manufacturing method thereof, a display panel and a display device, and aims to solve the technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
The present embodiment provides an array substrate, as shown in fig. 1, including a driving thin film transistor region a and a switching thin film transistor region B. The array substrate includes:
a base substrate 1;
a light shielding layer 2, which is positioned on the substrate 1 and comprises a plurality of light shielding structures 21 positioned in the driving thin film transistor area A;
a first oxygen-containing buffer layer 3 on the light-shielding layer 2;
a second oxygen-containing buffer layer 4 on the first oxygen-containing buffer layer 3, including a plurality of second oxygen-containing buffer units 41 in the driving thin film transistor region a;
an active layer 5 including a plurality of active islands 51, the active islands 51 including a first active island 511 located in the driving thin film transistor area a and a second active island 512 located in the switching thin film transistor area B, the first active island 51 being located on the second oxygen-containing buffer unit 41, the second active island 512 being located on the first oxygen-containing buffer layer 3;
wherein, the oxygen content of the first oxygen-containing buffer layer 3 is lower than that of the second oxygen-containing buffer layer 4.
In the array substrate provided by this embodiment, because the active layer below the first active island 511 is affected by more heat due to the existence of the light shielding structure 21 in the annealing process, after annealing, the oxygen content of the buffer layer below the first active island 511 is higher than the oxygen content of the buffer layer below the second active island 512, so that the oxygen supplementing capability of the buffer layer below the first active island 511 to the first active island 511 is approximately the same as the oxygen supplementing capability of the buffer layer below the second active island 152 to the second active island 512, thereby reducing the difference between the threshold voltage of the driving thin film transistor and the threshold voltage of the switching thin film transistor, improving the uniformity of the threshold voltage of the entire array substrate, further avoiding the situation that a part of the thin film transistor of the display panel cannot be normally conducted under some conditions, and improving the display quality of the display panel.
With continued reference to fig. 1, optionally, the substrate 1 is a glass substrate. It should be understood that the substrate 1 may be other types of substrate.
Further, with continued reference to fig. 1, the material of the first oxygen-containing buffer layer 3 and the material of the second oxygen-containing buffer layer 4 are both silicon oxide (SiO)xAnd x is a positive number). Specifically, under the condition that the oxygen content of the first oxygen-containing buffer layer 3 is lower than the oxygen content of the second oxygen-containing buffer layer 4, the oxygen content of the silicon oxide material can be adjusted according to the actual application requirement of the array substrate.
Further, with continued reference to fig. 1, the thickness of the first oxygen-containing buffer layer 3 is 300nm to 500 nm; the thickness of the second oxygen-containing buffer layer 4 is 100nm to 300 nm.
Further, with continued reference to fig. 1, the material of the active layer 5 includes one or a combination of indium gallium zinc oxide, indium zinc oxide and indium tin zinc oxide.
Further, with continued reference to fig. 2, the array substrate provided in this embodiment further includes:
a first insulating layer 6 including a plurality of first insulating cells 61 on the active islands 51;
a first metal layer 7 including a plurality of gates 71 on the first insulating unit 61;
a second insulating layer 8 on the first metal layer 7, including a plurality of via holes 81 penetrating the second insulating layer 8;
and the second metal layer 9 includes a plurality of sources 91 and a plurality of drains 92, wherein the sources 91 and the drains 92 are respectively connected to the corresponding active islands 51 through the vias 81.
Specifically, the active island 51, the first insulating unit 61, the gate electrode 71, the second insulating layer 8, the source electrode 91, and the drain electrode 92 collectively form a thin film transistor, wherein the thin film transistor in the driving thin film transistor region a is a driving thin film transistor DR TFT, and the thin film transistor in the switching thin film transistor region B is a switching thin film transistor SW TFT.
Based on the same inventive concept, the present embodiment provides a display panel including the array substrate in the above embodiments. Therefore, the display panel provided in this embodiment has the beneficial effects of the array substrate in the above embodiments, and the description thereof is omitted here.
Based on the same inventive concept, the present embodiment provides a display device including the display panel in the above embodiments. Therefore, the display device provided in this embodiment has the beneficial effects of the display panel in the above embodiments, and the description thereof is omitted.
Based on the same inventive concept, the present embodiment provides a manufacturing method of an array substrate, referring to fig. 3 and combining fig. 4 to 7, the array substrate includes a driving thin film transistor region a and a switching thin film transistor region B, and the manufacturing method of the present embodiment includes:
s1: a light shielding layer 2 is deposited on the substrate 1, and the light shielding layer 2 is patterned to obtain a plurality of light shielding structures 21 in the driving thin film transistor area a.
S2: a first oxygen-containing buffer layer 3 is deposited on the light-shielding layer 2.
S3: a second oxygen-containing buffer layer 4 is deposited on the first oxygen-containing buffer layer 3, and the second oxygen-containing buffer layer 4 is patterned to form a second oxygen-containing buffer unit 41 located in the driving thin film transistor region a.
S4: depositing an active layer 5, and performing a patterning process on the active layer 5 to obtain a plurality of active islands 51, where the active islands 51 include a first active island 511 located in a driving thin film transistor area a and a second active island 512 located in a switching thin film transistor area B, the first active island 511 is located on the second oxygen-containing buffer unit 41, and the second active island 512 is located on the first oxygen-containing buffer layer 3.
Wherein, the oxygen content of the first oxygen-containing buffer layer 3 is lower than that of the second oxygen-containing buffer layer 4.
In the manufacturing method of the array substrate provided by this embodiment, since the active layer under the first active island 511 is affected by more heat due to the existence of the light shielding structure 21 in the annealing process, by making the oxygen content of the buffer layer under the first active island 511 higher than the oxygen content of the buffer layer under the second active island 512, it is possible to, after annealing, such that the buffer layer under the first active island 511 has an oxygen-supplementing capability to the first active island 511, the oxygen replenishment capacity of the buffer layer under the second active island 152 for the second active island 512 tends to be the same, thereby reducing the difference between the threshold voltage of the driving thin film transistor and the threshold voltage of the switching thin film transistor, improving the uniformity of the threshold voltage of the entire array substrate, and then avoided the display panel in some circumstances partial thin-film transistor can't normally turn on the condition, improved the display quality of display panel.
Further, in the manufacturing method provided by this embodiment:
referring to fig. 5, step S2 includes: controlling the reaction gas N2O and SiH4Depositing a first oxygen-containing buffer layer 3 on the light-shielding layer 2 at a first ratio;
referring to fig. 6, the step S3 of depositing the second oxygen-containing buffer layer 2 on the first oxygen-containing buffer layer 3 includes: controlling the reaction gas N2O and SiH4A second oxygen containing buffer layer 4 is deposited on the first oxygen containing buffer layer 3 in a second ratio.
Wherein the first ratio is less than the second ratio.
Specifically, the first ratio and the second ratio both refer to N2O and SiH4The ratio of the gas flow rates of (a). The first ratio can be controlled between 30/1 and 50/1, and the second ratio can be controlled between 60/1 and 80/1. Preferably, the first ratio is controlled at 40/1 and the second ratio is controlled at 70/1.
Further, with reference to fig. 3 and with reference to fig. 8 to 11, the manufacturing method provided in this embodiment further includes:
s5: a first insulating layer 6 is deposited on the active layer 5, and the first insulating layer 6 is patterned to form a plurality of first insulating cells 61, the first insulating cells 61 being located on the active islands 51.
S6: a first metal layer 7 is deposited on the first insulating layer 6, and the first metal layer 7 is patterned to form a gate electrode 71 on the first insulating unit 61.
S7: a second insulating layer 8 is deposited on the first metal layer 7 and the second insulating layer 8 is patterned to form a via 81 through the second insulating layer.
S8: a second metal layer 9 is deposited on the second insulating layer 8, and the second metal layer 9 is patterned to form a plurality of source electrodes 91 and a plurality of drain electrodes 92, the source electrodes 91 and the drain electrodes 92 being connected to the corresponding active islands 51 through the vias 81, respectively.
Specifically, the active island 51, the first insulating unit 61, the gate electrode 71, the second insulating layer 8, the via hole 81, the source electrode 91, and the drain electrode 92 collectively constitute a thin film transistor, wherein the thin film transistor in the driving thin film transistor area a is a driving thin film transistor DR TFT, and the thin film transistor in the switching thin film transistor area B is a switching thin film transistor SW TFT.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
in the array substrate, the manufacturing method thereof, the display panel and the display device provided by the embodiment, since the active layer below the first active island is affected by more heat due to the existence of the light shielding structure in the annealing process, by making the oxygen content of the buffer layer under the first active island higher than the oxygen content of the buffer layer under the second active island, it is possible to, after annealing, so that the oxygen supplementing capacity of the buffer layer below the first active island to the first active island is approximately the same as the oxygen supplementing capacity of the buffer layer below the second active island to the second active island, thereby reducing the difference between the threshold voltage of the driving thin film transistor and the threshold voltage of the switching thin film transistor, improving the uniformity of the threshold voltage of the entire array substrate, and then avoided the display panel in some circumstances partial thin-film transistor can't normally turn on the condition, improved the display quality of display panel.
Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.
Claims (10)
1. An array substrate including a driving thin film transistor region and a switching thin film transistor region, the array substrate comprising:
a substrate base plate;
the shading layer is positioned on the substrate and comprises a plurality of shading structures positioned in the driving thin film transistor area;
a first oxygen-containing buffer layer on the light-shielding layer;
the second oxygen-containing buffer layer is positioned on the first oxygen-containing buffer layer and comprises a plurality of second oxygen-containing buffer units positioned in the driving thin film transistor area;
an active layer including a plurality of active islands, the active islands including a plurality of first active islands located in the driving thin film transistor region and a plurality of second active islands located in the switching thin film transistor region, the first active islands being located on the second oxygen-containing buffer units, the second active islands being located on the first oxygen-containing buffer layers;
wherein the oxygen content of the first oxygen-containing buffer layer is lower than the oxygen content of the second oxygen-containing buffer layer.
2. The array substrate of claim 1, wherein the first oxygen-containing buffer layer and the second oxygen-containing buffer layer are both made of silicon oxide.
3. The array substrate of claim 2,
the thickness of the first oxygen-containing buffer layer is 300nm-500 nm;
the thickness of the second oxygen-containing buffer layer is 100nm-300 nm.
4. The array substrate of claim 1,
the material of the active layer comprises one or a combination of indium gallium zinc oxide, indium zinc oxide and indium tin zinc oxide.
5. The array substrate of claim 1, further comprising:
a first insulating layer including a plurality of first insulating cells on the active island;
a first metal layer including a plurality of gates on the first insulating unit;
the second insulating layer is positioned on the first metal layer and comprises a plurality of through holes penetrating through the second insulating layer;
and the second metal layer comprises a plurality of sources and a plurality of drains, wherein the sources and the drains are respectively connected with the corresponding active islands through the through holes.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. A display device characterized by comprising the display panel according to claim 6.
8. A manufacturing method of an array substrate, wherein the array substrate comprises a driving thin film transistor region and a switching thin film transistor region, the manufacturing method comprises the following steps:
depositing a shading layer on a substrate, and carrying out graphical processing on the shading layer to obtain a plurality of shading structures positioned in the driving thin film transistor area;
depositing a first oxygen-containing buffer layer on the light-shielding layer;
depositing a second oxygen-containing buffer layer on the first oxygen-containing buffer layer, and performing graphical processing on the second oxygen-containing buffer layer to form a second oxygen-containing buffer unit positioned in the driving thin film transistor area;
depositing an active layer, and performing patterning processing on the active layer to obtain a plurality of active islands, wherein the active islands include a plurality of first active islands located in the driving thin film transistor area and a plurality of second active islands located in the switching thin film transistor area, the first active islands are located on the second oxygen-containing buffer units, and the second active islands are located on the first oxygen-containing buffer layers;
wherein the oxygen content of the first oxygen-containing buffer layer is lower than the oxygen content of the second oxygen-containing buffer layer.
9. The method of manufacturing according to claim 8,
the depositing a first oxygen-containing buffer layer on the light-shielding layer includes: controlling the reaction gas N2O and SiH4Depositing the first oxygen-containing buffer layer on the light-shielding layer at a first ratio;
said depositing a second oxygen-containing buffer layer on said first oxygen-containing buffer layer comprises: controlling the reaction gas N2O and SiH4Depositing the second oxygen-containing buffer layer on the light-shielding layer at a second ratio;
wherein the first ratio is smaller than the second ratio, and the first ratio and the second ratio are both N2O and SiH4The ratio of the gas flow rates of (a).
10. The method of manufacturing according to claim 8 or 9, further comprising:
depositing a first insulating layer on the active layer, and performing patterning on the first insulating layer to form a plurality of first insulating units, wherein the first insulating units are positioned on the active islands;
depositing a first metal layer on the first insulating layer, and performing patterning processing on the first metal layer to form a gate electrode on the first insulating unit;
depositing a second insulating layer on the first metal layer, and carrying out patterning treatment on the second insulating layer to form a through hole penetrating through the second insulating layer;
and depositing a second metal layer on the second insulating layer, and performing graphical processing on the second metal layer to form a plurality of source electrodes and a plurality of drain electrodes, wherein the source electrodes and the drain electrodes are respectively connected with the corresponding active islands through the via holes.
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| CN107039465A (en) * | 2017-04-28 | 2017-08-11 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method, display panel and display device |
| CN108039351A (en) * | 2017-12-04 | 2018-05-15 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
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| CN107039465A (en) * | 2017-04-28 | 2017-08-11 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method, display panel and display device |
| CN108039351A (en) * | 2017-12-04 | 2018-05-15 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
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