CN110416166A - Semiconductor package and preparation method thereof - Google Patents
Semiconductor package and preparation method thereof Download PDFInfo
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- CN110416166A CN110416166A CN201810393579.0A CN201810393579A CN110416166A CN 110416166 A CN110416166 A CN 110416166A CN 201810393579 A CN201810393579 A CN 201810393579A CN 110416166 A CN110416166 A CN 110416166A
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- layer
- joint face
- plastic packaging
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- surface circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The invention proposes a kind of semiconductor packages, it is characterized in that, the semiconductor package includes: main body substrate, side including upper surface circuit, lower surface circuit and connection the upper surface circuit and lower surface circuit, electrical communication between the upper surface circuit and lower surface circuit；Chip, including the first joint face and the second joint face being oppositely arranged, first joint face is electrically connected at the lower surface circuit；Plastic packaging layer coats the side of the substrate completely, and the plastic packaging layer at least partly coats the lower surface circuit and chip；Carry on the back layer gold, at least one first metallic connection parts being connected including the second joint face with the chip, first metallic connection parts include extending and protruding the plane of flattening outside the plastic packaging layer, and the sum of area of the plane of flattening is greater than the area of second joint face.The present invention solves the heat dissipation problem of chip while reducing production cost, meets and be higher than 3 grades of packaging body moisture sensitive of requirement.
Description
Technical field
The invention belongs to field of semiconductor manufacture more particularly to a kind of semiconductor package and preparation method thereof.
Background technique
It is general using in chip back because controlling the radiating requirements of chip and packaging body in existing chip-packaging structure
Deposited metal (back gold) reduces thermal resistance.
Meanwhile for the biggish large chip of radiating requirements, at present mainly by wafer directly back gold deposition and
Molding mode carries out.However, radiating by this method, if desired after being thinned on wafer of the thickness less than 180um
Gold is carried on the back, needs to carry out using the expensive support pattern being temporarily bonded.Meanwhile another solution is buried using substrate
Enter the mode of formula chip, but equally there is also serious yield issues.
Above two radiator structure and mode all there may be the problem of substrate exposure, the corresponding reliability of encapsulating structure compared with
It is low, and cannot generally pass through moisture sensitive grade 1(MSL1) requirement, so that packaging body is easy dampness.
Summary of the invention
To solve the above-mentioned problems, the invention proposes a kind of semiconductor package, the semiconductor package packets
It includes:
Main body substrate, the side including upper surface circuit, lower surface circuit and connection the upper surface circuit and lower surface circuit
Face, electrical communication between the upper surface circuit and lower surface circuit；
Chip, including the first joint face and the second joint face being oppositely arranged, first joint face be electrically connected at it is described under
Surface circuit；
Plastic packaging layer coats the side of the main body substrate completely, and the plastic packaging layer at least partly coats the lower surface circuit
And chip；
Carry on the back layer gold, including at least one first metallic connection parts that the second joint face with the chip is connected, described first
Metallic connection parts include extending and protruding the plane of flattening outside the plastic packaging layer, and the sum of area of the plane of flattening is greater than described second
The area of joint face.
As a further improvement of the present invention, the plastic packaging layer is flush with second joint face, the semiconductor package
Assembling structure further includes the stress buffer dielectric layer for being covered in second joint face and plastic packaging layer simultaneously, and first metal connects
Socket part passes through the stress buffer dielectric layer and is connected with second joint face, and the plane of flattening protrudes the stress buffer
Outside dielectric layer.
As a further improvement of the present invention, the semiconductor package further includes electrically connecting with the lower surface circuit
The 3D interconnecting piece connect, the plastic packaging layer at least partly coats the 3D interconnecting piece, and the back layer gold further includes connecting with the 3D
Second metallic connection parts of socket part connection.
As a further improvement of the present invention, metal heat sink is provided in the 3D interconnecting piece.
As a further improvement of the present invention, the 3D interconnecting piece includes the heat-conducting layer for being coated on its outer surface.
As a further improvement of the present invention, the main body substrate further includes that at least one layer is layed in the upper surface circuit
On high-frequency stabilization low-loss layer.
As a further improvement of the present invention, the semiconductor package includes being set to the high-frequency stabilization low-loss
The functional module being electrically connected on layer and with the upper surface circuit.
As a further improvement of the present invention, the semiconductor package includes damp-proof layer, and the damp-proof layer fitting is solid
Change in the high-frequency stabilization low-loss layer and at least partly covers the functional module.
As a further improvement of the present invention, the non-bulging main body substrate in the edge of the damp-proof layer side setting and
The plastic packaging layer is coated on the edge of the damp-proof layer.
As a further improvement of the present invention, the semiconductor package includes being set to the high-frequency stabilization low-loss
Support portion on layer and the outer layer function substrate being set on the support portion, the outer layer function substrate include at least two layers
The stack layer of stacked on top is filled by high frequency low dielectric constant and low loss material between the stack layer.
As a further improvement of the present invention, the semiconductor package includes that outer layer function substrate support is viscous
It ties in the damp-proof layer on the support portion.
The invention also provides a kind of production methods of semiconductor package, which comprises
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Damp-proof layer is provided and is bonded solidification in the high-frequency stabilization low-loss layer to cover the functional module；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Support plate is provided, separable temporary adhesion layer is equipped on the support plate, by the main body substrate upside-down mounting in the support plate
So that the temporary adhesion layer covers and fits in the damp-proof layer；
The main body substrate is filled with plastic packaging material, make the plastic packaging layer to be formed coat completely the main body substrate, chip and
3D interconnecting piece；
The support plate and temporary adhesion layer are separated, the plastic packaging layer is thinned to and is exposed the second connection of at least partly described chip
Face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold.
As a further improvement of the present invention, the step " provides damp-proof layer and to be bonded solidification low in the high-frequency stabilization
Depletion layer is to cover the functional module " and step " forming at least one 3D interconnecting piece in the lower surface circuit " between also wrap
It includes:
To the skirt selectivity of the damp-proof layer excision forming is so that the non-bulging main body substrate in the edge of the damp-proof layer
Side.
As a further improvement of the present invention, the step " is filled the main body substrate with plastic packaging material, makes to be formed
Plastic packaging layer coat the main body substrate, chip and 3D interconnecting piece completely " further include:
The plastic packaging layer also coats the edge of the damp-proof layer completely.
As a further improvement of the present invention, the step " separates the support plate and temporary adhesion layer, by the plastic packaging layer
It is thinned and exposes the second joint face and the 3D interconnecting piece of at least partly described chip " it specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
The invention also provides the production methods of second of semiconductor package, which comprises
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Damp-proof layer is provided and is bonded solidification in the high-frequency stabilization low-loss layer to cover the functional module；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Temporary adhesion layer is provided, enhancing frame is provided in the temporary adhesion layer, by the main body substrate upside-down mounting in the increasing
So that the temporary adhesion layer covers and fits in the damp-proof layer in temporary adhesion layer in strong frame；
The main body substrate is filled with plastic packaging material, make the plastic packaging layer to be formed coat completely the main body substrate, chip and
3D interconnecting piece；
The enhancing frame and temporary adhesion layer are separated, the plastic packaging layer is thinned and is exposed the second of at least partly described chip
Joint face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold.
As a further improvement of the present invention, the step " provides damp-proof layer and to be bonded solidification low in the high-frequency stabilization
Depletion layer is to cover the functional module " and step " forming at least one 3D interconnecting piece in the lower surface circuit " between also wrap
It includes:
To the skirt selectivity of the damp-proof layer excision forming is so that the non-bulging main body substrate in the edge of the damp-proof layer
Side.
As a further improvement of the present invention, the step " is filled the main body substrate with plastic packaging material, makes to be formed
Plastic packaging layer coat the main body substrate, chip and 3D interconnecting piece completely ":
The plastic packaging layer also coats the edge of the damp-proof layer completely.
As a further improvement of the present invention, step " the separation enhancing frame and the temporary adhesion layer, by the modeling
Sealing is thinned and exposes the second joint face and the 3D interconnecting piece of at least partly described chip " it specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
The invention also provides the production methods of the third semiconductor package, which comprises
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Support portion is formed on the high-frequency stabilization low-loss layer；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Support plate is provided, separable temporary adhesion layer is equipped on the support plate, by the support portion and the temporary adhesion layer
It is bonded and makes the main body substrate upside-down mounting in the support plate；
The main body substrate is filled with plastic packaging material, the plastic packaging layer to be formed is made to coat the main body substrate, chip, 3D completely
The side of interconnecting piece and the support portion；
The support plate and temporary adhesion layer are separated, the plastic packaging layer is thinned to and is exposed the second connection of at least partly described chip
Face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold；
Outer layer function substrate is provided, the lower surface of the outer layer function substrate is bonded admittedly by damp-proof layer with the support portion
Change.
As a further improvement of the present invention, the step " separates the support plate and temporary adhesion layer, by the plastic packaging layer
It is thinned and exposes the second joint face and the 3D interconnecting piece of at least partly described chip " it specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
The invention also provides the production methods of the 4th kind of semiconductor package, which comprises
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Support portion is formed on the high-frequency stabilization low-loss layer；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Temporary adhesion layer is provided, enhancing frame is provided in the temporary adhesion layer, by the main body substrate upside-down mounting in the increasing
So that the support portion is bonded with the temporary adhesion layer in temporary adhesion layer in strong frame；
The main body substrate is filled with plastic packaging material, the plastic packaging layer to be formed is made to coat the main body substrate, chip, 3D completely
The side of interconnecting piece and the support portion；
The enhancing frame and temporary adhesion layer are separated, the plastic packaging layer is thinned and is exposed the second of at least partly described chip
Joint face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold；
Outer layer function substrate is provided, the lower surface of the outer layer function substrate is bonded admittedly by damp-proof layer with the support portion
Change.
As a further improvement of the present invention, step " the separation enhancing frame and the temporary adhesion layer, by the modeling
Sealing is thinned and exposes the second joint face and the 3D interconnecting piece of at least partly described chip " it specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
Beneficial effects of the present invention: semiconductor package proposed by the present invention, by the way that plastic packaging layer is coated main body substrate
Side and the cladding main body substrate lower surface circuit and chip, can also expire while making entire encapsulating structure more stable
Requirement that is sufficient and being higher than 3 grades of moisture sensitive, and pass through the second connection at least one first metallic connection parts and chip
Face is connected, and solves the heat dissipation problem of chip while reducing production cost, while the first metallic connection parts include extending
And the plane of flattening outside plastic packaging layer is protruded, the sum of area of the plane of flattening is greater than the area of the second joint face of chip, further enhances
The heat-sinking capability of semiconductor package.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of first embodiment of the invention；
Fig. 2 is the structural schematic diagram of second embodiment of the invention；
Fig. 3 is the structural schematic diagram of third embodiment of the invention；；
Fig. 4 is the structural schematic diagram of fourth embodiment of the invention；；
Fig. 5 is the structural schematic diagram of fifth embodiment of the invention；；
Fig. 6 is the structural schematic diagram of sixth embodiment of the invention；
Fig. 7 is the structural schematic diagram of a production method of the invention；
Fig. 8 is the structural schematic diagram of another production method of the present invention.
Specific embodiment
Although not each embodiment only includes one only it should be appreciated that this specification is described according to embodiment
Vertical technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should be by specification
As a whole, the technical solutions in the various embodiments may also be suitably combined, formed it will be appreciated by those skilled in the art that
Other embodiments.
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
The specific embodiment of technical solution of the present invention described in detail below:
Embodiment 1:
Join shown in Fig. 1, in the first embodiment of the invention, semiconductor package includes main body substrate 100, chip 200, plastic packaging
Layer 300 and back layer gold 400.
Specifically, main body substrate 100 includes upper surface circuit 110, lower surface circuit 120 on the other side and connection
The side 130 of upper surface circuit 110 and lower surface circuit 120, and the upper surface circuit 110 of main body substrate 100 and lower surface electricity
Electrical communication between road 120；It should be noted that the main body substrate 100 referred in the embodiment of the present invention can be used homogeneity or
Heterogeneous circuit board structure stacks, by the way that electric connection structure is arranged in assist side and is stacked with come realization body substrate 100
Conducting up and down.
Meanwhile chip 200 includes the first joint face 210 and the second joint face 220 being oppositely arranged, in the present embodiment
In, the first joint face 210 is electrically connected at the lower surface circuit 120 of main body substrate 100；It should be noted that in the present embodiment
The upper surface circuit 110 of mentioned main body substrate 100 and lower surface circuit 120 have been limited only to facilitate description it are specific
Structural relation, and there is no specific and fixed positional relationship, in other embodiments of the present invention, the first joint face 210 can also
It is electrically connected with the upper surface circuit 110 of main body substrate 100.
In the first embodiment of the invention, plastic packaging layer 300 side 130 of cladding main body substrate 100, lower surface circuit completely
120 and chip 200.
Carrying on the back layer gold 400 includes the first metallic connection parts 410 being connected with the second joint face 220 of chip 200；Specifically
, the first metallic connection parts 410 may be configured as by PVD process deposit copper or titanium, certainly, may be alternatively provided as electro-coppering or
Nickel；In the present embodiment, the first metallic connection parts 410 are set as copper post and include extension and protrude prolonging outside plastic packaging layer 300
Developable surface 411, specifically, the plane of flattening 411 forms the protection copper post protective film just like materials such as Ni/Pd/Au/Sn, and the plane of flattening 411
The sum of area be greater than the area of the second joint face 220 so that the plane of flattening 411 possesses more when docking with PCB main board or cooling fin
Big contact surface is to enhance the heat-sinking capability of chip 200.
Main body substrate 100 in the present embodiment further includes at least one layer of high-frequency stabilization being layed on upper surface circuit 110
Low-loss layer 140, meanwhile, semiconductor package further include be set on high-frequency stabilization low-loss layer 140 and with upper surface electricity
The functional module 700 that road 110 is electrically connected, specifically, the functional module 700 in the present embodiment is set as Anneta module, and
According to different functional modules 700 for the different demands in terms of high-frequency and stability, high-frequency stabilization low-loss layer 140 can be with
The different numbers of plies is targetedly set, such as AiP antenna applications, then needs at least one layer of high-frequency stabilization low-loss layer
140。
Semiconductor package further includes damp-proof layer 800, and in the present embodiment, the fitting solidification of damp-proof layer 800 is steady in high frequency
Determine low-loss layer 140 and functional module 700 is completely covered to reduce influence of the moisture to functional module 700, specifically, moisture-proof
Layer 800 is set as high frequency low dielectric constant and low loss material, to not have an impact to the signal transmitting and receiving of functional module 700；Together
When, in the first embodiment of the invention, damp-proof layer 800 also protrudes out main body substrate 100 other than being covered in functional module 700
Side 130 and be covered on plastic packaging layer 300, further enhance the moisture sensitive grade of semiconductor package.
Certainly, in other embodiments of the present invention, the edge of damp-proof layer 800 may be alternatively provided as non-bulging main body substrate 100
Side 130 be arranged, and plastic packaging layer 300 is also coated on the edge of damp-proof layer 800 and enhances the binding force of damp-proof layer 800.
Particularly, semiconductor package further includes having the 3D interconnecting piece 600, In being electrically connected with lower surface circuit 120
In the present embodiment, 3D interconnecting piece 600 is set as tin ball, and plastic packaging layer 300 is coated on 3D interconnecting piece 600 completely, meanwhile, carry on the back layer gold
400 further include having the second metallic connection parts 420 to recline with 600 phase of 3D interconnecting piece, likewise, 420 He of the second metallic connection parts
As first metallic connection parts 410, be also configured as copper post, and formed just like made of the materials such as Ni/Pd/Au/Sn for protecting
The protective film of copper post.
Embodiment 2:
Join shown in Fig. 2, compared with first embodiment, the main distinction is second embodiment of the invention, and plastic packaging layer 300 does not wrap completely
Chip 200 and 3D interconnecting piece 600 are covered, and plastic packaging layer 300 is flush with the second joint face 220,3D interconnecting piece 600 at least partly reveals
Out.
Meanwhile semiconductor package further includes the stress being covered on the second joint face 220 and plastic packaging layer 300 simultaneously
Buffer dielectric layer 500, the first metallic connection parts 410 pass through stress buffer dielectric layer 500 and are connected with the second joint face 220, and
And the plane of flattening 411 protrudes outside stress buffer dielectric layer 500.
By covering the second joint face 220 with the stress buffer dielectric layer 500 of low-temperature setting in second embodiment of the invention
With plastic packaging layer 300, enhance the protection to chip 200, it is therefore prevented that encapsulating structure surface attachment when due to generate stress and
Chip 200 is damaged, the strength and stability of semiconductor package is enhanced.
In addition to above-mentioned distinguishing feature, the structure of second embodiment of the invention is identical with first embodiment, herein not
It repeats more.
Embodiment 3, embodiment 4 and embodiment 5:
In conjunction with shown in Fig. 3, Fig. 4 and Fig. 5, on the basis of second embodiment of the invention, by changing the specific of 3D interconnecting piece 600
Structure, the invention also provides 3rd embodiment, fourth embodiment and the 5th embodiments.
Join shown in Fig. 3, in the third embodiment, metal heat sink 610 is provided in 3D interconnecting piece 600, specifically, by 3D
Interconnecting piece 600 is set as tin ball, and metal heat sink 610 is set as copper caryosphere, copper caryosphere is coated on and in Yu Xiqiu to be formed
3D interconnecting piece 600, the heat dissipation performance after enhancing 3D interconnecting piece 600 and the connection of the second metallic connection parts 420.
Embodiment 4:
Join shown in Fig. 4, in the fourth embodiment, 3D interconnecting piece 600 is set as Copper column structure and is coated in the outer surface of copper post
The heat-conducting layer 620 made of High-heat-conductiviinsulation insulation material, to enhance the heat dissipation performance of semiconductor package.
Embodiment 5:
Join shown in Fig. 5, in the 5th embodiment, 3D interconnecting piece 600 is set as hollow Copper column structure, and copper is filled in copper post
Cream 630, while the heat-conducting layer 620 of useful High-heat-conductiviinsulation insulation material production is also coated in the outer surface of copper post, it further enhances
The heat dissipation performance of semiconductor package.
Further, in third embodiment of the invention, fourth embodiment and the 5th embodiment, the side of damp-proof layer 800
The side 130 that edge may be configured as non-bulging main body substrate 100 is arranged, and plastic packaging layer 300 is coated on the edge of damp-proof layer 800 to increase
The binding force of strong damp-proof layer 800.
In addition, remaining structure feature of 3rd embodiment, fourth embodiment and the 5th embodiment is and in second embodiment
It is identical, not described here any more.
Embodiment 6:
Join shown in Fig. 6, in sixth embodiment of the invention, semiconductor package further includes being set to high-frequency stabilization low-loss layer
Support portion 141 on 140, and the outer layer function substrate 900 being set on support portion 141.
Specifically, outer layer function substrate 900 is set as outer layer antenna substrate, and the stack layer including two layers of stacked on top
910, antenna chip 920 is provided on stack layer 910, meanwhile, pass through high frequency low dielectric constant and low loss material between stack layer 910
Material filling.
Meanwhile in order to enable outer layer function substrate 900 to be well fixed, in sixth embodiment of the invention, partly lead
Body encapsulating structure further includes that outer layer function substrate 900 is supported the damp-proof layer 800 that is bonded on support portion 141, not only can be to prevent
The entrance of sealing vapour also enhances the stability of outer layer function substrate 900.
Likewise, remaining structure feature in sixth embodiment is identical with second embodiment, not described here any more.
Further, referring to figs. 7 and 8, the invention also provides the production methods of four kinds of semiconductor packages.
Method one:
A1, provider's substrate 100, upper surface circuit 110 of the main body substrate 100 including side 130 and electrical communication is under
Surface circuit 120；
A2, at least one layer of high-frequency stabilization low-loss layer 140 is laid in upper surface circuit 110；
A3, the functional module 700 being electrically connected with upper surface circuit 110 is implanted on high-frequency stabilization low-loss layer 140；
A4, damp-proof layer 800 is provided and is bonded solidification in high-frequency stabilization low-loss layer 140 with covering function module 700；
A5, to the skirt selectivity of damp-proof layer 800 excision forming are so that the non-bulging main body substrate 100 in the edge of damp-proof layer 800
Side 130.
A6, at least one 3D interconnecting piece 600 is formed in lower surface circuit 120；
A7, provide chip 200, chip 200 includes the first joint face 210 and the second joint face 220, by the first joint face 210 with
Lower surface circuit 120 is electrically connected；
A8, support plate 1000 is provided, separable temporary adhesion layer 1100 is equipped on support plate 1000, by 100 upside-down mounting of main body substrate
In support plate 1000 so that temporary adhesion layer 1100 covers and fits in damp-proof layer 800；
A9, main body substrate 100 is filled with plastic packaging material, makes the plastic packaging layer 300 to be formed cladding main body substrate 100, core completely
The edge of piece 200,3D interconnecting piece 600 and damp-proof layer 800；
Plastic packaging layer 300 is thinned and is exposed the of at least partly chip 200 by A10, separation support plate 1000 and temporary adhesion layer 1100
Two joint faces 220 and 3D interconnecting piece 600；
A11, deposition modeling the first metallic connection parts 410 and the second metallic connection parts 420 and respectively with the second joint face 220 and 3D
The exposed portion of interconnecting piece 600 is joined to form back layer gold 400.
Meanwhile the step A10 of this method can with specifically includes the following steps:
Plastic packaging layer 300 is thinned to and is flush with the second joint face 220 of chip 200;
Stress buffer dielectric layer 500 is covered on plastic packaging layer 300, the second joint face 220 and 3D interconnecting piece 600;
Laser drill is carried out to stress buffer dielectric layer 500 or photoetching is formed to the second joint face 220 and the 3D company of chip 200
Socket part 600 is at least partly exposed.
Method two:
B1, provider's substrate 100, upper surface circuit 110 of the main body substrate 100 including side 130 and electrical communication is under
Surface circuit 120；
B2, at least one layer of high-frequency stabilization low-loss layer 140 is laid in upper surface circuit 110；
B3, the functional module 700 being electrically connected with upper surface circuit 110 is implanted on high-frequency stabilization low-loss layer 140；
B4, damp-proof layer 800 is provided and is bonded solidification in high-frequency stabilization low-loss layer 140 with covering function module 700；
B5, to the skirt selectivity of damp-proof layer 800 excision forming are so that the non-bulging main body substrate 100 in the edge of damp-proof layer 800
Side 130；
B6, at least one 3D interconnecting piece 600 is formed in lower surface circuit 120；
B7, provide chip 200, chip 200 includes the first joint face 210 and the second joint face 220, by the first joint face 210 with
Lower surface circuit 120 is electrically connected；
B8, temporary adhesion layer 1100 is provided, enhancing frame 1300 is provided in temporary adhesion layer 1100, main body substrate 100 is fallen
Loaded in the temporary adhesion layer 1100 in enhancing frame 1300 so that temporary adhesion layer 1100 covers and fits in damp-proof layer 800,
It is provided in round or rectangular metal or pcb board material specifically, enhancing frame 1300 in this method；
B9, main body substrate 100 is filled with plastic packaging material, makes the plastic packaging layer 300 to be formed cladding main body substrate 100, core completely
The edge of piece 200,3D interconnecting piece 600 and damp-proof layer 800；
B10, separation enhancing frame 1300 and temporary adhesion layer 1100, plastic packaging layer 300 is thinned and exposes at least partly chip 200
The second joint face 220 and 3D interconnecting piece 600；
B11, deposition modeling the first metallic connection parts 410 and the second metallic connection parts 420 and respectively with the second joint face 220 and 3D
The exposed portion of interconnecting piece 600 is joined to form back layer gold 400.
Meanwhile the step B10 of this method can with specifically includes the following steps:
Plastic packaging layer 300 is thinned to and is flush with the second joint face 220 of chip 200;
Stress buffer dielectric layer 500 is covered on plastic packaging layer 300, the second joint face 220 and 3D interconnecting piece 600;
Laser drill is carried out to stress buffer dielectric layer 500 or photoetching is formed to the second joint face 220 and the 3D company of chip 200
Socket part 600 is at least partly exposed.
Method three:
C1, provider's substrate 100, upper surface circuit 110 of the main body substrate 100 including side 130 and electrical communication is under
Surface circuit 120；
C2, at least one layer of high-frequency stabilization low-loss layer 140 is laid in upper surface circuit 110；
C3, the functional module 700 being electrically connected with upper surface circuit 110 is implanted on high-frequency stabilization low-loss layer 140；
C4, support portion 141 is formed on high-frequency stabilization low-loss layer 140；
C5, at least one 3D interconnecting piece 600 is formed in lower surface circuit 120；
C6, provide chip 200, chip 200 includes the first joint face 210 and the second joint face 220, by the first joint face 210 with
Lower surface circuit 120 is electrically connected；
C7, support plate 1000 is provided, is equipped with separable temporary adhesion layer 1100 on support plate 1000, by support portion 141 and temporarily
Adhesive layer 1100 is bonded and makes 100 upside-down mounting of main body substrate in support plate 1000；
C8, main body substrate 100 is filled with plastic packaging material, makes the plastic packaging layer 300 to be formed cladding main body substrate 100, core completely
The side 130 of piece 200,3D interconnecting piece 600 and support portion 141；
Plastic packaging layer 300 is thinned and is exposed the of at least partly chip 200 by C9, separation support plate 1000 and temporary adhesion layer 1100
Two joint faces 220 and 3D interconnecting piece 600；
C10, deposition modeling the first metallic connection parts 410 and the second metallic connection parts 420 and respectively with the second joint face 220 and 3D
The exposed portion of interconnecting piece 600 is joined to form back layer gold 400；
C11, outer layer function substrate 900 is provided, the lower surface of outer layer function substrate 900 is passed through into damp-proof layer 800 and support portion 141
Fitting solidification.
Meanwhile the step C9 of this method can with specifically includes the following steps:
Plastic packaging layer 300 is thinned to and is flush with the second joint face 220 of chip 200;
Stress buffer dielectric layer 500 is covered on plastic packaging layer 300, the second joint face 220 and 3D interconnecting piece 600;
Laser drill is carried out to stress buffer dielectric layer 500 or photoetching is formed to the second joint face 220 and the 3D company of chip 200
Socket part 600 is at least partly exposed.
Method four:
D1, provider's substrate 100, upper surface circuit 110 of the main body substrate 100 including side 130 and electrical communication is under
Surface circuit 120；
D2, at least one layer of high-frequency stabilization low-loss layer 140 is laid in upper surface circuit 110；
D3, the functional module 700 being electrically connected with upper surface circuit 110 is implanted on high-frequency stabilization low-loss layer 140；
D4, support portion 141 is formed on high-frequency stabilization low-loss layer 140；
D5, at least one 3D interconnecting piece 600 is formed in lower surface circuit 120；
D6, provide chip 200, chip 200 includes the first joint face 210 and the second joint face 220, by the first joint face 210 with
Lower surface circuit 120 is electrically connected；
D7, temporary adhesion layer 1100 is provided, enhancing frame 1300 is provided in temporary adhesion layer 1100, main body substrate 100 is fallen
Loaded in the temporary adhesion layer 1100 in enhancing frame 1300 so that support portion 141 is bonded with temporary adhesion layer 1100, specifically,
Enhance frame 1300 in this method to be provided in round or rectangular metal or pcb board material；
D8, main body substrate 100 is filled with plastic packaging material, makes the plastic packaging layer 300 to be formed cladding main body substrate 100, core completely
The side 130 of piece 200,3D interconnecting piece 600 and support portion 141；
D9, separation enhancing frame 1300 and temporary adhesion layer 1100, plastic packaging layer 300 is thinned and exposes at least partly chip 200
The second joint face 220 and 3D interconnecting piece 600；
D10, deposition modeling the first metallic connection parts 410 and the second metallic connection parts 420 and respectively with the second joint face 220 and 3D
The exposed portion of interconnecting piece 600 is joined to form back layer gold 400；
D11, outer layer function substrate 900 is provided, the lower surface of outer layer function substrate 900 is passed through into damp-proof layer 800 and support portion 141
Fitting solidification.
Meanwhile the step D9 of this method can with specifically includes the following steps:
Plastic packaging layer 300 is thinned to and is flush with the second joint face 220 of chip 200;
Stress buffer dielectric layer 500 is covered on plastic packaging layer 300, the second joint face 220 and 3D interconnecting piece 600;
Laser drill is carried out to stress buffer dielectric layer 500 or photoetching is formed to the second joint face 220 and the 3D company of chip 200
Socket part 600 is at least partly exposed.
Beneficial effects of the present invention: semiconductor package proposed by the present invention and preparation method thereof, by by plastic packaging layer
The side 130 of 300 cladding main body substrates 100 and the lower surface circuit 120 and chip 200 of the cladding main body substrate 100, allow
Also 3 grades of moisture sensitive of requirement is able to satisfy and is higher than while entirely encapsulating structure is more stable, and by using at least one
First metallic connection parts 410 are connected with the second joint face 220 of chip 200, solve core while reducing production cost
The heat dissipation problem of piece 200, while the first metallic connection parts 410 include extending and protruding the plane of flattening 411 outside plastic packaging layer 300, are prolonged
The sum of area of developable surface 411 is greater than the area of the second joint face 220 of chip 200, further enhances semiconductor package
Heat-sinking capability.
The series of detailed descriptions listed above are illustrated only for possible embodiments of the invention,
The protection scope being not intended to limit the invention, it is all without departing from equivalent embodiment made by technical spirit of the present invention or change should all
It is included within protection scope of the present invention.
Claims (23)
1. a kind of semiconductor package, which is characterized in that the semiconductor package includes:
Main body substrate, the side including upper surface circuit, lower surface circuit and connection the upper surface circuit and lower surface circuit
Face, electrical communication between the upper surface circuit and lower surface circuit；
Chip, including the first joint face and the second joint face being oppositely arranged, first joint face be electrically connected at it is described under
Surface circuit；
Plastic packaging layer coats the side of the main body substrate completely, and the plastic packaging layer at least partly coats the lower surface circuit
And chip；
Carry on the back layer gold, including at least one first metallic connection parts that the second joint face with the chip is connected, described first
Metallic connection parts include extending and protruding the plane of flattening outside the plastic packaging layer, and the sum of area of the plane of flattening is greater than described second
The area of joint face.
2. semiconductor package according to claim 1, which is characterized in that the plastic packaging layer and second joint face
It is flush, the semiconductor package further includes stress buffer Jie for being covered in second joint face and plastic packaging layer simultaneously
Electric layer, first metallic connection parts pass through the stress buffer dielectric layer and are connected with second joint face, and described prolong
Developable surface protrudes outside the stress buffer dielectric layer.
3. semiconductor package according to claim 1, which is characterized in that the semiconductor package further include with
The 3D interconnecting piece that the lower surface circuit is electrically connected, the plastic packaging layer at least partly coat the 3D interconnecting piece, and the back
Layer gold further includes the second metallic connection parts connecting with the 3D interconnecting piece.
4. semiconductor package according to claim 3, which is characterized in that be provided with metal in the 3D interconnecting piece and dissipate
Warmware.
5. semiconductor package according to claim 3, which is characterized in that the 3D interconnecting piece is coated on outside it
The heat-conducting layer on surface.
6. semiconductor package according to claim 1, which is characterized in that the main body substrate further includes at least one layer
The high-frequency stabilization low-loss layer being layed on the upper surface circuit.
7. semiconductor package according to claim 6, which is characterized in that the semiconductor package includes setting
In the functional module being electrically connected on the high-frequency stabilization low-loss layer and with the upper surface circuit.
8. semiconductor package according to claim 7, which is characterized in that the semiconductor package includes moisture-proof
Layer, damp-proof layer fitting solidification in the high-frequency stabilization low-loss layer and at least partly cover the functional module.
9. semiconductor package according to claim 8, which is characterized in that the edge of the damp-proof layer is non-bulging described
The side of main body substrate is arranged and the plastic packaging layer is coated on the edge of the damp-proof layer.
10. semiconductor package according to claim 6, which is characterized in that the semiconductor package includes setting
The support portion being placed on the high-frequency stabilization low-loss layer and the outer layer function substrate being set on the support portion, it is described outer
Layer function substrate includes the stack layer of at least two layers stacked on top, passes through high frequency low dielectric constant and low loss between the stack layer
Material filling.
11. semiconductor package according to claim 10, which is characterized in that the semiconductor package includes will
The outer layer function substrate supports the damp-proof layer being bonded on the support portion.
12. a kind of production method of semiconductor package, which is characterized in that the described method includes:
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Damp-proof layer is provided and is bonded solidification in the high-frequency stabilization low-loss layer to cover the functional module；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Support plate is provided, separable temporary adhesion layer is equipped on the support plate, by the main body substrate upside-down mounting in the support plate
So that the temporary adhesion layer covers and fits in the damp-proof layer；
The main body substrate is filled with plastic packaging material, make the plastic packaging layer to be formed coat completely the main body substrate, chip and
3D interconnecting piece；
The support plate and temporary adhesion layer are separated, the plastic packaging layer is thinned to and is exposed the second connection of at least partly described chip
Face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold.
13. semiconductor package production method according to claim 12, which is characterized in that the step " provides anti-
Damp layer is simultaneously bonded solidification in the high-frequency stabilization low-loss layer to cover the functional module " and step it is " electric in the lower surface
Road forms at least one 3D interconnecting piece " between further include:
To the skirt selectivity of the damp-proof layer excision forming is so that the non-bulging main body substrate in the edge of the damp-proof layer
Side.
14. semiconductor package production method according to claim 13, which is characterized in that the step " uses plastic packaging
Material is filled the main body substrate, and the plastic packaging layer to be formed is made to coat the main body substrate, chip and 3D interconnecting piece completely " also
Include:
The plastic packaging layer also coats the edge of the damp-proof layer completely.
15. semiconductor package production method according to claim 12, which is characterized in that step " the separation institute
Support plate and temporary adhesion layer are stated, the plastic packaging layer is thinned to and is exposed the second joint face of at least partly described chip and described
3D interconnecting piece " specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
16. a kind of production method of semiconductor package, which is characterized in that the described method includes:
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Damp-proof layer is provided and is bonded solidification in the high-frequency stabilization low-loss layer to cover the functional module；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Temporary adhesion layer is provided, enhancing frame is provided in the temporary adhesion layer, by the main body substrate upside-down mounting in the increasing
So that the temporary adhesion layer covers and fits in the damp-proof layer in temporary adhesion layer in strong frame；
The main body substrate is filled with plastic packaging material, make the plastic packaging layer to be formed coat completely the main body substrate, chip and
3D interconnecting piece；
The enhancing frame and temporary adhesion layer are separated, the plastic packaging layer is thinned and is exposed the second of at least partly described chip
Joint face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold.
17. semiconductor package production method according to claim 16, which is characterized in that the step " provides anti-
Damp layer is simultaneously bonded solidification in the high-frequency stabilization low-loss layer to cover the functional module " and step it is " electric in the lower surface
Road forms at least one 3D interconnecting piece " between further include:
To the skirt selectivity of the damp-proof layer excision forming is so that the non-bulging main body substrate in the edge of the damp-proof layer
Side.
18. semiconductor package production method according to claim 17, which is characterized in that the step " uses plastic packaging
Material is filled the main body substrate, and the plastic packaging layer to be formed is made to coat the main body substrate, chip and 3D interconnecting piece completely ":
The plastic packaging layer also coats the edge of the damp-proof layer completely.
19. semiconductor package production method according to claim 16, which is characterized in that step " the separation institute
State enhancing frame and temporary adhesion layer, the plastic packaging layer is thinned and expose at least partly described chip the second joint face and
The 3D interconnecting piece " specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
20. a kind of production method of semiconductor package, which is characterized in that the described method includes:
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Support portion is formed on the high-frequency stabilization low-loss layer；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Support plate is provided, separable temporary adhesion layer is equipped on the support plate, by the support portion and the temporary adhesion layer
It is bonded and makes the main body substrate upside-down mounting in the support plate；
The main body substrate is filled with plastic packaging material, the plastic packaging layer to be formed is made to coat the main body substrate, chip, 3D completely
The side of interconnecting piece and the support portion；
The support plate and temporary adhesion layer are separated, the plastic packaging layer is thinned to and is exposed the second connection of at least partly described chip
Face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold；
Outer layer function substrate is provided, the lower surface of the outer layer function substrate is bonded admittedly by damp-proof layer with the support portion
Change.
21. semiconductor package production method according to claim 20, which is characterized in that step " the separation institute
Support plate and temporary adhesion layer are stated, the plastic packaging layer is thinned to and is exposed the second joint face of at least partly described chip and described
3D interconnecting piece " specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
22. a kind of production method of semiconductor package, which is characterized in that the described method includes:
Provider's substrate, the main body substrate include the upper surface circuit and lower surface circuit of side and electrical communication；
At least one layer of high-frequency stabilization low-loss layer is laid in the upper surface circuit；
The functional module being electrically connected with the upper surface circuit is implanted on the high-frequency stabilization low-loss layer；
Support portion is formed on the high-frequency stabilization low-loss layer；
At least one 3D interconnecting piece is formed in the lower surface circuit；
Chip is provided, chip includes the first joint face and the second joint face, by first joint face and the lower surface circuit
It is electrically connected；
Temporary adhesion layer is provided, enhancing frame is provided in the temporary adhesion layer, by the main body substrate upside-down mounting in the increasing
So that the support portion is bonded with the temporary adhesion layer in temporary adhesion layer in strong frame；
The main body substrate is filled with plastic packaging material, the plastic packaging layer to be formed is made to coat the main body substrate, chip, 3D completely
The side of interconnecting piece and the support portion；
The enhancing frame and temporary adhesion layer are separated, the plastic packaging layer is thinned and is exposed the second of at least partly described chip
Joint face and the 3D interconnecting piece；
The first metallic connection parts of deposition modeling and the second metallic connection parts and respectively with second joint face and 3D interconnecting piece
Exposed portion is joined to form back layer gold；
Outer layer function substrate is provided, the lower surface of the outer layer function substrate is bonded admittedly by damp-proof layer with the support portion
Change.
23. semiconductor package production method according to claim 22, which is characterized in that step " the separation institute
State enhancing frame and temporary adhesion layer, the plastic packaging layer is thinned and expose at least partly described chip the second joint face and
The 3D interconnecting piece " specifically includes:
The plastic packaging layer is thinned to and is flush with the second joint face of the chip;
Stress buffer dielectric layer is covered on the plastic packaging layer, the second joint face and 3D interconnecting piece;
Laser drill is carried out to the stress buffer dielectric layer or photoetching is formed to the second joint face and the 3D company of the chip
Socket part is at least partly exposed.
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| CN202110631929.4A CN113380782B (en) | 2018-04-27 | 2018-04-27 | Semiconductor packaging structure |
| CN201810393579.0A CN110416166B (en) | 2018-04-27 | 2018-04-27 | Semiconductor packaging structure and manufacturing method thereof |
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| CN113380782A (en) | 2021-09-10 |
| CN110416166B (en) | 2021-06-29 |
| CN113380782B (en) | 2023-11-07 |
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