CN110416166B - Semiconductor packaging structure and manufacturing method thereof - Google Patents

Semiconductor packaging structure and manufacturing method thereof Download PDF

Info

Publication number
CN110416166B
CN110416166B CN201810393579.0A CN201810393579A CN110416166B CN 110416166 B CN110416166 B CN 110416166B CN 201810393579 A CN201810393579 A CN 201810393579A CN 110416166 B CN110416166 B CN 110416166B
Authority
CN
China
Prior art keywords
layer
chip
main body
connecting part
body substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810393579.0A
Other languages
Chinese (zh)
Other versions
CN110416166A (en
Inventor
林耀剑
刘硕
周莎莎
陈建
陈雪晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN202110631929.4A priority Critical patent/CN113380782B/en
Priority to CN201810393579.0A priority patent/CN110416166B/en
Publication of CN110416166A publication Critical patent/CN110416166A/en
Application granted granted Critical
Publication of CN110416166B publication Critical patent/CN110416166B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

The invention provides a semiconductor packaging structure, which is characterized by comprising: the main body substrate comprises an upper surface circuit, a lower surface circuit and a side surface for connecting the upper surface circuit and the lower surface circuit, wherein the upper surface circuit and the lower surface circuit are electrically communicated; the chip comprises a first connecting surface and a second connecting surface which are oppositely arranged, and the first connecting surface is electrically connected with the lower surface circuit; the plastic packaging layer completely covers the side face of the substrate, and at least partially covers the lower surface circuit and the chip; back of the body gold layer, include with at least one first metal connecting portion that the second of chip is connected the face and is connected, first metal connecting portion is including extending and protrusion the outer extension face of plastic envelope layer, the area sum of extension face is greater than the area that the second is connected the face. The invention solves the heat dissipation problem of the chip while reducing the production cost, and meets and is higher than the requirement of the package body moisture sensitivity level 3.

Description

Semiconductor packaging structure and manufacturing method thereof
Technical Field
The invention belongs to the field of semiconductor manufacturing, and particularly relates to a semiconductor packaging structure and a manufacturing method thereof.
Background
In the existing chip packaging structure, because of the heat dissipation requirements of the control chip and the packaging body, the thermal resistance is generally reduced by depositing metal (back gold) on the back surface of the chip.
Meanwhile, for a large chip with a large heat dissipation requirement, the process is mainly performed by directly depositing and molding a back gold on a wafer. However, if the wafer with a thickness of less than 180um needs to be back-gold after thinning, the heat dissipation by this method needs to be carried out by using an expensive temporary bonding support method. Meanwhile, another solution is to use a substrate embedded chip, but there is also a serious yield problem.
Both of the above heat dissipation structures and methods may have the problem of substrate exposure, and the package structure has relatively low reliability and generally cannot pass the requirement of moisture sensitivity level 1 (MSL 1) to make the package vulnerable to moisture.
Disclosure of Invention
In order to solve the above problem, the present invention provides a semiconductor package structure, including:
the main body substrate comprises an upper surface circuit, a lower surface circuit and a side surface for connecting the upper surface circuit and the lower surface circuit, wherein the upper surface circuit and the lower surface circuit are electrically communicated;
the chip comprises a first connecting surface and a second connecting surface which are oppositely arranged, and the first connecting surface is electrically connected with the lower surface circuit;
the plastic packaging layer completely covers the side face of the main body substrate, and at least partially covers the lower surface circuit and the chip;
back of the body gold layer, include with at least one first metal connecting portion that the second of chip is connected the face and is connected, first metal connecting portion is including extending and protrusion the outer extension face of plastic envelope layer, the area sum of extension face is greater than the area that the second is connected the face.
As a further improvement of the present invention, the plastic package layer is flush with the second connection surface, the semiconductor package structure further includes a stress buffer dielectric layer covering the second connection surface and the plastic package layer, the first metal connection portion penetrates through the stress buffer dielectric layer to be connected with the second connection surface, and the extension surface protrudes out of the stress buffer dielectric layer.
As a further improvement of the present invention, the semiconductor package structure further includes a 3D connection portion electrically connected to the lower surface circuit, the plastic package layer at least partially covers the 3D connection portion, and the back gold layer further includes a second metal connection portion connected to the 3D connection portion.
As a further improvement of the invention, a metal heat dissipation piece is arranged in the 3D connecting part.
As a further improvement of the present invention, the 3D connection portion includes a heat conductive layer wrapped around an outer surface thereof.
As a further improvement of the invention, the main body substrate further comprises at least one high-frequency stable low-loss layer laid on the upper surface circuit.
As a further improvement of the present invention, the semiconductor package structure includes a functional module disposed on the high-frequency stable low-loss layer and electrically connected to the upper surface circuit.
As a further improvement of the present invention, the semiconductor package structure includes a moisture-proof layer, which is bonded and cured to the high-frequency stable low-loss layer and at least partially covers the functional module.
As a further improvement of the invention, the edge of the moisture-proof layer is not arranged to protrude out of the side surface of the main body substrate, and the plastic package layer is coated on the edge of the moisture-proof layer.
As a further improvement of the present invention, the semiconductor package structure includes a support portion disposed on the high-frequency stable low-loss layer and an outer functional substrate disposed on the support portion, the outer functional substrate includes at least two stacked layers stacked one above the other, and the stacked layers are filled with a high-frequency low-dielectric-constant low-loss material.
As a further improvement of the present invention, the semiconductor package structure includes a moisture-proof layer which supports and adheres the outer layer functional substrate to the supporting portion.
The invention also provides a manufacturing method of the semiconductor packaging structure, which comprises the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
providing a moisture-proof layer and adhering and curing the moisture-proof layer to the high-frequency stable low-loss layer so as to cover the functional module;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a carrier plate, paving a separable temporary bonding layer on the carrier plate, and inversely installing the main body substrate on the carrier plate so that the temporary bonding layer covers and is attached to the moisture-proof layer;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip and the 3D connecting part;
separating the carrier plate and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
and depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the exposed parts of the second connecting surface and the 3D connecting part to form a back gold layer.
As a further improvement of the present invention, the step of "providing a moisture-proof layer and adhering and curing the high-frequency stable low-loss layer to cover the functional module" and the step of "forming at least one 3D connection portion on the lower surface circuit" further include:
and selectively cutting and shaping the edge of the moisture-proof layer so that the edge of the moisture-proof layer does not protrude out of the side surface of the main body substrate.
As a further improvement of the present invention, the step of "filling the main substrate with a molding compound so that the formed molding layer completely covers the main substrate, the chip, and the 3D connection portion" further includes:
the plastic packaging layer also completely covers the edge of the moisture-proof layer.
As a further improvement of the present invention, the step of "separating the carrier plate and the temporary adhesive layer, thinning the plastic sealing layer and exposing at least a part of the second connection surface of the chip and the 3D connection portion" specifically includes:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
The invention also provides a manufacturing method of the second semiconductor packaging structure, which comprises the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
providing a moisture-proof layer and adhering and curing the moisture-proof layer to the high-frequency stable low-loss layer so as to cover the functional module;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a temporary bonding layer, wherein a reinforcing frame is arranged on the temporary bonding layer, and the main body substrate is inversely arranged on the temporary bonding layer in the reinforcing frame so that the temporary bonding layer covers and is attached to the moisture-proof layer;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip and the 3D connecting part;
separating the reinforcing frame and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
and depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the exposed parts of the second connecting surface and the 3D connecting part to form a back gold layer.
As a further improvement of the present invention, the step of "providing a moisture-proof layer and adhering and curing the high-frequency stable low-loss layer to cover the functional module" and the step of "forming at least one 3D connection portion on the lower surface circuit" further include:
and selectively cutting and shaping the edge of the moisture-proof layer so that the edge of the moisture-proof layer does not protrude out of the side surface of the main body substrate.
As a further improvement of the present invention, the step "filling the main substrate with a molding compound so that the formed molding layer completely covers the main substrate, the chip, and the 3D connection portion":
the plastic packaging layer also completely covers the edge of the moisture-proof layer.
As a further improvement of the present invention, the step of "separating the reinforcing frame and the temporary adhesive layer, thinning the molding layer and exposing at least a part of the second connection surface of the chip and the 3D connection portion" specifically includes:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
The invention also provides a manufacturing method of the third semiconductor packaging structure, which comprises the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
a support portion is formed on the high-frequency stable low-loss layer;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a carrier plate, wherein a separable temporary bonding layer is laid on the carrier plate, and the support part is bonded with the temporary bonding layer to enable the main body substrate to be inversely arranged on the carrier plate;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip, the 3D connecting part and the side face of the supporting part;
separating the carrier plate and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the second connecting surface and the exposed part of the 3D connecting part to form a back gold layer;
and providing an outer layer functional substrate, and adhering and curing the lower surface of the outer layer functional substrate with the supporting part through the moisture-proof layer.
As a further improvement of the present invention, the step of "separating the carrier plate and the temporary adhesive layer, thinning the plastic sealing layer and exposing at least a part of the second connection surface of the chip and the 3D connection portion" specifically includes:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
The invention also provides a manufacturing method of a fourth semiconductor packaging structure, which comprises the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
a support portion is formed on the high-frequency stable low-loss layer;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a temporary bonding layer, wherein a reinforcing frame is arranged on the temporary bonding layer, and the main body substrate is inversely arranged on the temporary bonding layer in the reinforcing frame so as to enable the supporting part to be attached to the temporary bonding layer;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip, the 3D connecting part and the side face of the supporting part;
separating the reinforcing frame and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the second connecting surface and the exposed part of the 3D connecting part to form a back gold layer;
and providing an outer layer functional substrate, and adhering and curing the lower surface of the outer layer functional substrate with the supporting part through the moisture-proof layer.
As a further improvement of the present invention, the step of "separating the reinforcing frame and the temporary adhesive layer, thinning the molding layer and exposing at least a part of the second connection surface of the chip and the 3D connection portion" specifically includes:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
The invention has the beneficial effects that: the semiconductor packaging structure provided by the invention has the advantages that the side face of the main body substrate is coated by the plastic packaging layer, and the lower surface circuit and the chip of the main body substrate are coated, so that the whole packaging structure is more stable, and simultaneously, the requirement of the humidity sensitivity level 3 can be met and higher, in addition, the heat dissipation problem of the chip is solved while the production cost is reduced by connecting at least one first metal connecting part with the second connecting face of the chip, meanwhile, the first metal connecting part comprises the extension faces which extend and protrude out of the plastic packaging layer, and the sum of the areas of the extension faces is larger than the area of the second connecting face of the chip, so the heat dissipation capability of the semiconductor packaging structure is further enhanced.
Drawings
FIG. 1 is a schematic structural diagram of a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a second embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a third embodiment of the present invention; (ii) a
FIG. 4 is a schematic structural diagram of a fourth embodiment of the present invention; (ii) a
FIG. 5 is a schematic structural diagram of a fifth embodiment of the present invention; (ii) a
FIG. 6 is a schematic structural diagram of a sixth embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a method of making the present invention;
FIG. 8 is a schematic structural diagram of another method of the present invention.
Detailed Description
It should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art will be able to make the description as a whole, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following detailed description describes specific embodiments of the present invention:
example 1:
referring to fig. 1, in the first embodiment of the present invention, a semiconductor package structure includes a main substrate 100, a chip 200, a molding compound layer 300, and a back gold layer 400.
Specifically, the main body substrate 100 includes an upper surface circuit 110, a lower surface circuit 120 opposite to the upper surface circuit 110, and a side surface 130 connecting the upper surface circuit 110 and the lower surface circuit 120, and the upper surface circuit 110 and the lower surface circuit 120 of the main body substrate 100 are electrically connected; it should be noted that the main body substrate 100 mentioned in the embodiments of the present invention may be stacked using a homogeneous or heterogeneous circuit board structure, and the main body substrate 100 is electrically connected up and down by disposing an electrical connection structure in the circuit board and stacking the electrical connection structure with each other.
Meanwhile, the chip 200 includes a first connection surface 210 and a second connection surface 220 disposed oppositely, in the embodiment, the first connection surface 210 is electrically connected to the lower surface circuit 120 of the main body substrate 100; it should be noted that the upper surface circuit 110 and the lower surface circuit 120 of the main body substrate 100 mentioned in this embodiment are only defined for convenience of describing their specific structural relationships, and there is no specific and fixed positional relationship, and in other embodiments of the present invention, the first connection surface 210 may also be electrically connected to the upper surface circuit 110 of the main body substrate 100.
In the first embodiment of the present invention, the molding compound layer 300 completely covers the side 130, the bottom surface circuit 120 and the chip 200 of the main substrate 100.
The back gold layer 400 includes a first metal connection portion 410 connected to the second connection face 220 of the chip 200; specifically, the first metal connection portion 410 may be configured as copper or titanium deposited by PVD process, and of course, may also be configured as electroplated copper or nickel; in this embodiment, the first metal connecting portion 410 is a copper pillar and includes an extending surface 411 extending and protruding out of the plastic package layer 300, specifically, the extending surface 411 is formed with a protective copper pillar protective film made of materials such as Ni/Pd/Au/Sn, and the sum of the areas of the extending surfaces 411 is larger than the area of the second connecting surface 220, so that the extending surface 411 has a larger contact surface to enhance the heat dissipation capability of the chip 200 when being butted with a PCB motherboard or a heat sink.
The main body substrate 100 in this embodiment further includes at least one high-frequency stable low-loss layer 140 laid on the upper surface circuit 110, and meanwhile, the semiconductor package structure further includes a functional module 700 disposed on the high-frequency stable low-loss layer 140 and electrically connected to the upper surface circuit 110, specifically, the functional module 700 in this embodiment is set as an antenna module, and different numbers of layers can be set in a targeted manner for the high-frequency stable low-loss layer 140 according to different requirements of different functional modules 700 for high frequency and stability, for example, for AiP antenna applications, at least one high-frequency stable low-loss layer 140 is required.
The semiconductor package structure further includes a moisture barrier 800, in this embodiment, the moisture barrier 800 is adhered to the high-frequency stable low-loss layer 140 and completely covers the functional module 700 to reduce the influence of moisture on the functional module 700, specifically, the moisture barrier 800 is made of a high-frequency low-dielectric-constant low-loss material, so that the signal transceiving of the functional module 700 is not influenced; meanwhile, in the first embodiment of the present invention, the moisture barrier 800 is protruded from the side 130 of the main substrate 100 and covered on the molding layer 300 in addition to the functional module 700, so as to further enhance the moisture sensitivity level of the semiconductor package structure.
Of course, in other embodiments of the present invention, the edge of the moisture-proof layer 800 may also be disposed not to protrude from the side 130 of the main substrate 100, and the plastic sealing layer 300 is further wrapped around the edge of the moisture-proof layer 800 to enhance the bonding force of the moisture-proof layer 800.
In particular, the semiconductor package structure further includes a 3D connecting portion 600 electrically connected to the lower surface circuit 120, in this embodiment, the 3D connecting portion 600 is a solder ball, and the molding layer 300 completely covers the 3D connecting portion 600, and the back gold layer 400 further includes a second metal connecting portion 420 attached to the 3D connecting portion 600, and similarly, the second metal connecting portion 420 and the first metal connecting portion 410 are also copper pillars, and a protective film made of materials such as Ni/Pd/Au/Sn for protecting the copper pillars is formed.
Example 2:
referring to fig. 2, the second embodiment of the present invention is different from the first embodiment mainly in that the molding compound layer 300 does not completely cover the chip 200 and the 3D connection portion 600, the molding compound layer 300 is flush with the second connection surface 220, and the 3D connection portion 600 is at least partially exposed.
Meanwhile, the semiconductor package structure further includes a stress buffering dielectric layer 500 covering the second connection surface 220 and the plastic package layer 300, the first metal connection portion 410 penetrates through the stress buffering dielectric layer 500 to be connected with the second connection surface 220, and the extension surface 411 protrudes out of the stress buffering dielectric layer 500.
In the second embodiment of the present invention, the second connection surface 220 and the molding compound layer 300 are covered by the stress buffering dielectric layer 500 cured at a low temperature, so that the protection of the chip 200 is enhanced, the chip 200 is prevented from being damaged by stress generated when the package structure is mounted on the surface, and the strength and stability of the semiconductor package structure are enhanced.
Except for the above-mentioned technical features, the structure of the second embodiment of the present invention is the same as that of the first embodiment, and thus, the description thereof is omitted.
Example 3, example 4 and example 5:
referring to fig. 3, 4 and 5, a third embodiment, a fourth embodiment and a fifth embodiment are provided by changing a specific structure of a 3D connection part 600 on the basis of the second embodiment of the present invention.
Referring to fig. 3, in the third embodiment, a metal heat dissipation member 610 is disposed in the 3D connection portion 600, specifically, the 3D connection portion 600 is disposed as a solder ball, the metal heat dissipation member 610 is disposed as a copper core ball, and the copper core ball is wrapped in the solder ball to form the 3D connection portion 600, so that the heat dissipation performance after the 3D connection portion 600 is connected to the second metal connection portion 420 is enhanced.
Example 4:
referring to fig. 4, in the fourth embodiment, the 3D connection portion 600 is configured as a copper pillar structure, and a heat conduction layer 620 made of a high heat conduction insulating material is coated on an outer surface of the copper pillar to enhance the heat dissipation performance of the semiconductor package structure.
Example 5:
referring to fig. 5, in the fifth embodiment, the 3D connection portion 600 is a hollow copper pillar structure, the copper pillar is filled with copper paste 630, and the outer surface of the copper pillar is also covered with a heat conduction layer 620 made of a high heat conduction insulating material, so as to further enhance the heat dissipation performance of the semiconductor package structure.
Further, in the third, fourth and fifth embodiments of the present invention, the edge of the moisture-proof layer 800 may be disposed not to protrude from the side 130 of the main body substrate 100, and the plastic sealing layer 300 covers the edge of the moisture-proof layer 800 to enhance the bonding force of the moisture-proof layer 800.
In addition, the remaining structural features of the third embodiment, the fourth embodiment and the fifth embodiment are the same as those in the second embodiment, and are not repeated herein.
Example 6:
referring to fig. 6, in the sixth embodiment of the present invention, the semiconductor package structure further includes a support 141 disposed on the high-frequency stable low-loss layer 140, and an outer functional substrate 900 disposed on the support 141.
Specifically, the outer layer functional substrate 900 is configured as an outer layer antenna substrate, and includes two stacked layers 910 stacked up and down, an antenna chip 920 is disposed on the stacked layers 910, and meanwhile, the stacked layers 910 are filled with a high-frequency low-dielectric constant low-loss material.
Meanwhile, in order to fix the outer functional substrate 900 well, in the sixth embodiment of the present invention, the semiconductor package structure further includes a moisture-proof layer 800 that supports and bonds the outer functional substrate 900 to the supporting portion 141, which not only prevents water vapor from entering, but also enhances the stability of the outer functional substrate 900.
Similarly, the remaining structural features in the sixth embodiment are the same as those in the second embodiment, and are not repeated herein.
Furthermore, as shown in fig. 7 and fig. 8, the present invention also provides four methods for manufacturing the semiconductor package structure.
The method comprises the following steps:
1, providing a main body substrate 100, wherein the main body substrate 100 comprises a side surface 130 and an upper surface circuit 110 and a lower surface circuit 120 which are electrically communicated;
a2, laying at least one high-frequency stable low-loss layer 140 on the upper surface circuit 110;
a3, implanting a functional module 700 electrically connected to the top surface circuit 110 on the high frequency stable low loss layer 140;
a4, providing a moisture-proof layer 800 and adhering and curing the moisture-proof layer 800 to the high-frequency stable low-loss layer 140 to cover the functional module 700;
a5, the edge of the moisture barrier 800 is selectively cut to shape so that the edge of the moisture barrier 800 does not protrude beyond the side 130 of the bulk substrate 100.
A6, forming at least one 3D connection 600 on the lower surface circuit 120;
a7, providing a chip 200, wherein the chip 200 includes a first connection face 210 and a second connection face 220, electrically connecting the first connection face 210 with the bottom surface circuit 120;
a8, providing a carrier plate 1000, laying a detachable temporary bonding layer 1100 on the carrier plate 1000, and inversely installing the main substrate 100 on the carrier plate 1000 to make the temporary bonding layer 1100 cover and adhere to the moisture-proof layer 800;
a9, filling the main body substrate 100 with a plastic package material, so that the formed plastic package layer 300 completely covers the edges of the main body substrate 100, the chip 200, the 3D connection part 600 and the moisture-proof layer 800;
a10, separating the carrier board 1000 and the temporary adhesive layer 1100, thinning the plastic package layer 300 and exposing at least part of the second connection face 220 of the chip 200 and the 3D connection part 600;
a11, depositing and forming the first metal connection part 410 and the second metal connection part 420 and respectively connecting with the second connection surface 220 and the exposed part of the 3D connection part 600 to form the back gold layer 400.
Meanwhile, step a10 of the method may further specifically include the following steps:
thinning the plastic packaging layer 300 to be flush with the second connection surface 220 of the chip 200;
covering the plastic package layer 300, the second connection surface 220 and the 3D connection portion 600 with a stress buffer dielectric layer 500;
the stress buffering dielectric layer 500 is laser-drilled or lithographically patterned until the second connection face 220 of the chip 200 and the 3D connection portion 600 are at least partially exposed.
The second method comprises the following steps:
b1, providing a main body substrate 100, wherein the main body substrate 100 comprises a side surface 130 and an upper surface circuit 110 and a lower surface circuit 120 which are electrically communicated;
b2, laying at least one high-frequency stable low-loss layer 140 on the upper surface circuit 110;
b3, implanting a functional module 700 electrically connected to the upper surface circuit 110 on the high frequency stable low loss layer 140;
b4, providing a moisture-proof layer 800 and adhering and curing the moisture-proof layer 800 to the high-frequency stable low-loss layer 140 to cover the functional module 700;
b5, selectively cutting and shaping the edge of the moisture-proof layer 800 so that the edge of the moisture-proof layer 800 does not protrude out of the side 130 of the main body substrate 100;
b6, forming at least one 3D connection 600 on the lower surface circuit 120;
b7, providing a chip 200, wherein the chip 200 includes a first connection face 210 and a second connection face 220, electrically connecting the first connection face 210 with the bottom surface circuit 120;
b8, providing a temporary bonding layer 1100, arranging a reinforcing frame 1300 on the temporary bonding layer 1100, and inversely installing the main body substrate 100 on the temporary bonding layer 1100 in the reinforcing frame 1300 so that the temporary bonding layer 1100 covers and is attached to the moisture-proof layer 800, specifically, the reinforcing frame 1300 is arranged to be a round or square metal or a PCB plate in the method;
b9, filling the main body substrate 100 with a plastic package material, so that the formed plastic package layer 300 completely covers the edges of the main body substrate 100, the chip 200, the 3D connection part 600 and the moisture-proof layer 800;
b10, separating the reinforcing frame 1300 and the temporary adhesive layer 1100, thinning the plastic package layer 300 and exposing at least part of the second connection face 220 of the chip 200 and the 3D connection part 600;
b11, depositing and forming the first metal connection portion 410 and the second metal connection portion 420 and connecting with the second connection surface 220 and the exposed portion of the 3D connection portion 600 to form the back gold layer 400.
Meanwhile, step B10 of the method may further specifically include the following steps:
thinning the plastic packaging layer 300 to be flush with the second connection surface 220 of the chip 200;
covering the plastic package layer 300, the second connection surface 220 and the 3D connection portion 600 with a stress buffer dielectric layer 500;
the stress buffering dielectric layer 500 is laser-drilled or lithographically patterned until the second connection face 220 of the chip 200 and the 3D connection portion 600 are at least partially exposed.
The third method comprises the following steps:
c1, providing a main body substrate 100, wherein the main body substrate 100 comprises a side surface 130 and an upper surface circuit 110 and a lower surface circuit 120 which are electrically connected;
c2, laying at least one high-frequency stable low-loss layer 140 on the upper surface circuit 110;
c3, implanting a functional module 700 electrically connected to the top surface circuit 110 on the high frequency stable low loss layer 140;
c4, a support 141 is formed on the high-frequency stable low-loss layer 140;
c5, forming at least one 3D connection 600 on the lower surface circuit 120;
c6, providing a chip 200, wherein the chip 200 includes a first connection face 210 and a second connection face 220, electrically connecting the first connection face 210 with the bottom surface circuit 120;
c7, providing a carrier board 1000, laying a detachable temporary adhesive layer 1100 on the carrier board 1000, attaching the supporting part 141 and the temporary adhesive layer 1100 and inversely installing the main substrate 100 on the carrier board 1000;
c8, filling the main body substrate 100 with a molding compound, so that the formed molding compound layer 300 completely covers the main body substrate 100, the chip 200, the 3D connection part 600 and the side surface 130 of the support part 141;
c9, separating the carrier board 1000 and the temporary adhesive layer 1100, thinning the plastic package layer 300 and exposing at least part of the second connection face 220 of the chip 200 and the 3D connection part 600;
c10, depositing and molding the first metal connection part 410 and the second metal connection part 420 and respectively connecting the second connection surface 220 and the exposed part of the 3D connection part 600 to form a back gold layer 400;
c11, providing an outer layer functional substrate 900, and bonding and solidifying the lower surface of the outer layer functional substrate 900 with the supporting part 141 through the moisture-proof layer 800.
Meanwhile, step C9 of the method may further specifically include the following steps:
thinning the plastic packaging layer 300 to be flush with the second connection surface 220 of the chip 200;
covering the plastic package layer 300, the second connection surface 220 and the 3D connection portion 600 with a stress buffer dielectric layer 500;
the stress buffering dielectric layer 500 is laser-drilled or lithographically patterned until the second connection face 220 of the chip 200 and the 3D connection portion 600 are at least partially exposed.
The method four comprises the following steps:
d1, providing a main body substrate 100, wherein the main body substrate 100 comprises a side surface 130 and an upper surface circuit 110 and a lower surface circuit 120 which are electrically connected;
d2, laying at least one high-frequency stable low-loss layer 140 on the upper surface circuit 110;
d3, implanting a functional module 700 electrically connected to the upper surface circuit 110 on the high frequency stable low loss layer 140;
d4, a support 141 is formed on the high-frequency stable low-loss layer 140;
d5, forming at least one 3D connection 600 on the lower surface circuit 120;
d6, providing a chip 200, wherein the chip 200 includes a first connection face 210 and a second connection face 220, electrically connecting the first connection face 210 with the bottom surface circuit 120;
d7, providing a temporary bonding layer 1100, arranging a reinforcing frame 1300 on the temporary bonding layer 1100, and inversely installing the main body substrate 100 on the temporary bonding layer 1100 in the reinforcing frame 1300 to make the supporting part 141 attached to the temporary bonding layer 1100, specifically, the reinforcing frame 1300 is arranged to be a round or square metal or PCB plate;
d8, filling the main body substrate 100 with a molding compound, so that the formed molding compound layer 300 completely covers the main body substrate 100, the chip 200, the 3D connection part 600 and the side surface 130 of the support part 141;
d9, separating the reinforcing frame 1300 and the temporary adhesive layer 1100, thinning the plastic package layer 300 and exposing at least part of the second connection face 220 of the chip 200 and the 3D connection part 600;
d10, depositing and molding the first metal connection part 410 and the second metal connection part 420 and respectively connecting the second connection surface 220 and the exposed part of the 3D connection part 600 to form a back gold layer 400;
d11, providing an outer layer functional substrate 900, and bonding and curing the lower surface of the outer layer functional substrate 900 with the supporting part 141 through the moisture-proof layer 800.
Meanwhile, step D9 of the method may further specifically include the following steps:
thinning the plastic packaging layer 300 to be flush with the second connection surface 220 of the chip 200;
covering the plastic package layer 300, the second connection surface 220 and the 3D connection portion 600 with a stress buffer dielectric layer 500;
the stress buffering dielectric layer 500 is laser-drilled or lithographically patterned until the second connection face 220 of the chip 200 and the 3D connection portion 600 are at least partially exposed.
The invention has the beneficial effects that: the invention provides a semiconductor packaging structure and a manufacturing method thereof, wherein a plastic packaging layer 300 is used for coating the side surface 130 of a main body substrate 100, and the lower surface circuit 120 of the main body substrate 100 and a chip 200, so that the whole packaging structure is more stable and can meet the requirement of grade 3 of moisture sensitivity, at the same time, at least one first metal connecting part 410 is connected with a second connecting surface 220 of the chip 200, the heat dissipation problem of the chip 200 is solved while the production cost is reduced, meanwhile, the first metal connecting part 410 comprises an extension surface 411 which extends and protrudes out of the plastic packaging layer 300, and the sum of the areas of the extension surfaces 411 is larger than the area of the second connecting surface 220 of the chip 200, so that the heat dissipation capability of the semiconductor packaging structure is further enhanced.
The above detailed description is merely illustrative of possible embodiments of the present invention and is not intended to limit the scope of the invention, which is intended to include all equivalent embodiments or modifications within the scope of the present invention without departing from the technical spirit of the present invention.

Claims (22)

1. A semiconductor package structure, comprising:
the main body substrate comprises an upper surface circuit, a lower surface circuit and a side surface for connecting the upper surface circuit and the lower surface circuit, wherein the upper surface circuit and the lower surface circuit are electrically communicated;
the chip comprises a first connecting surface and a second connecting surface which are oppositely arranged, and the first connecting surface is electrically connected with the lower surface circuit;
the plastic packaging layer completely covers the side face of the main body substrate, and at least partially covers the lower surface circuit and the chip;
the back gold layer comprises at least one first metal connecting part connected with a second connecting surface of the chip, the first metal connecting part comprises extending surfaces extending out of the plastic package layer, and the sum of the areas of the extending surfaces is larger than that of the second connecting surface;
the plastic-sealed layer with the second is connected the face and is flushed mutually, semiconductor packaging structure still including cover simultaneously the second is connected the face and the stress buffering dielectric layer on plastic-sealed layer, first metal connecting portion pass stress buffering dielectric layer with the second is connected the face and is connected, just the extension face is salient outside the stress buffering dielectric layer.
2. The semiconductor package structure of claim 1, further comprising a 3D connection portion electrically connected to the lower surface circuit, wherein the plastic encapsulation layer at least partially covers the 3D connection portion, and wherein the back gold layer further comprises a second metal connection portion connected to the 3D connection portion.
3. The semiconductor package structure of claim 2, wherein a metal heat spreader is disposed within the 3D connection.
4. The semiconductor package structure of claim 2, wherein the 3D connection comprises a thermally conductive layer wrapped around an outer surface thereof.
5. The semiconductor package structure of claim 1, wherein the body substrate further comprises at least one high frequency stable low loss layer disposed on the upper surface circuitry.
6. The semiconductor package structure of claim 5, wherein the semiconductor package structure comprises a functional module disposed on the high frequency stable low loss layer and electrically connected to the upper surface circuit.
7. The semiconductor package structure of claim 6, wherein the semiconductor package structure comprises a moisture barrier layer that is cured to the high frequency stable low loss layer and at least partially covers the functional module.
8. The semiconductor package structure of claim 7, wherein an edge of the moisture barrier layer is not protruded from a side surface of the main substrate and the molding compound covers the edge of the moisture barrier layer.
9. The semiconductor package structure of claim 5, wherein the semiconductor package structure comprises a support portion disposed on the high-frequency stable low-loss layer and an outer functional substrate disposed on the support portion, the outer functional substrate comprises at least two stacked layers stacked one on top of the other, and the stacked layers are filled with a high-frequency low-dielectric-constant low-loss material.
10. The semiconductor package structure of claim 9, wherein the semiconductor package structure comprises a moisture barrier layer that supports the outer functional substrate bonded to the support portion.
11. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
providing a moisture-proof layer and adhering and curing the moisture-proof layer to the high-frequency stable low-loss layer so as to cover the functional module;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a carrier plate, paving a separable temporary bonding layer on the carrier plate, and inversely installing the main body substrate on the carrier plate so that the temporary bonding layer covers and is attached to the moisture-proof layer;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip and the 3D connecting part;
separating the carrier plate and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
and depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the exposed parts of the second connecting surface and the 3D connecting part to form a back gold layer.
12. The method of claim 11, wherein the steps of providing a moisture barrier and curing the high frequency stable low loss layer to cover the functional module and forming at least one 3D connection on the lower surface circuit further comprise:
and selectively cutting and shaping the edge of the moisture-proof layer so that the edge of the moisture-proof layer does not protrude out of the side surface of the main body substrate.
13. The method of manufacturing a semiconductor package structure according to claim 12, wherein the step of filling the main substrate with a molding compound so that the main substrate, the chip and the 3D connection portion are completely covered by the formed molding compound further comprises:
the plastic packaging layer also completely covers the edge of the moisture-proof layer.
14. The method for manufacturing a semiconductor package structure according to claim 11, wherein the step of separating the carrier board and the temporary adhesive layer, thinning the molding layer and exposing at least a portion of the second connection surface of the chip and the 3D connection portion specifically comprises:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
15. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
providing a moisture-proof layer and adhering and curing the moisture-proof layer to the high-frequency stable low-loss layer so as to cover the functional module;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a temporary bonding layer, wherein a reinforcing frame is arranged on the temporary bonding layer, and the main body substrate is inversely arranged on the temporary bonding layer in the reinforcing frame so that the temporary bonding layer covers and is attached to the moisture-proof layer;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip and the 3D connecting part;
separating the reinforcing frame and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
and depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the exposed parts of the second connecting surface and the 3D connecting part to form a back gold layer.
16. The method of manufacturing a semiconductor package structure according to claim 15, wherein the steps of providing a moisture barrier and curing the high-frequency stable low-loss layer to cover the functional module in a fitting manner and forming at least one 3D connection portion on the lower surface circuit further comprise:
and selectively cutting and shaping the edge of the moisture-proof layer so that the edge of the moisture-proof layer does not protrude out of the side surface of the main body substrate.
17. The method for manufacturing a semiconductor package structure according to claim 16, wherein the step of filling the main body substrate with a molding compound so that the formed molding compound completely covers the main body substrate, the chip and the 3D connection portion "comprises:
the plastic packaging layer also completely covers the edge of the moisture-proof layer.
18. The method for manufacturing a semiconductor package structure according to claim 15, wherein the step of "separating the reinforcing frame and the temporary adhesive layer, thinning the molding layer and exposing at least a portion of the second connection surface of the chip and the 3D connection portion" specifically comprises:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
19. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
a support portion is formed on the high-frequency stable low-loss layer;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a carrier plate, wherein a separable temporary bonding layer is laid on the carrier plate, and the support part is bonded with the temporary bonding layer to enable the main body substrate to be inversely arranged on the carrier plate;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip, the 3D connecting part and the side face of the supporting part;
separating the carrier plate and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the second connecting surface and the exposed part of the 3D connecting part to form a back gold layer;
and providing an outer layer functional substrate, and adhering and curing the lower surface of the outer layer functional substrate with the supporting part through the moisture-proof layer.
20. The method for manufacturing a semiconductor package structure according to claim 19, wherein the step of "separating the carrier board and the temporary adhesive layer, thinning the molding layer and exposing at least a portion of the second connection surface of the chip and the 3D connection portion" specifically comprises:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
21. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a main body substrate, wherein the main body substrate comprises a side surface, an upper surface circuit and a lower surface circuit which are electrically communicated;
laying at least one high-frequency stable low-loss layer on the upper surface circuit;
implanting a functional module electrically connected with the upper surface circuit on the high-frequency stable low-loss layer;
a support portion is formed on the high-frequency stable low-loss layer;
forming at least one 3D connection on the lower surface circuit;
providing a chip, wherein the chip comprises a first connecting surface and a second connecting surface, and the first connecting surface is electrically connected with the lower surface circuit;
providing a temporary bonding layer, wherein a reinforcing frame is arranged on the temporary bonding layer, and the main body substrate is inversely arranged on the temporary bonding layer in the reinforcing frame so as to enable the supporting part to be attached to the temporary bonding layer;
filling the main body substrate with a plastic package material to enable the formed plastic package layer to completely cover the main body substrate, the chip, the 3D connecting part and the side face of the supporting part;
separating the reinforcing frame and the temporary bonding layer, thinning the plastic packaging layer and exposing at least part of the second connecting surface of the chip and the 3D connecting part;
depositing and forming a first metal connecting part and a second metal connecting part and respectively connecting the first metal connecting part and the second metal connecting part with the second connecting surface and the exposed part of the 3D connecting part to form a back gold layer;
and providing an outer layer functional substrate, and adhering and curing the lower surface of the outer layer functional substrate with the supporting part through the moisture-proof layer.
22. The method for manufacturing a semiconductor package structure according to claim 21, wherein the step of "separating the reinforcing frame and the temporary adhesive layer, thinning the molding layer and exposing at least a portion of the second connection surface of the chip and the 3D connection portion" specifically comprises:
thinning the plastic packaging layer to be flush with the second connecting surface of the chip;
covering a stress buffer dielectric layer on the plastic packaging layer, the second connecting surface and the 3D connecting part;
and performing laser drilling or photoetching molding on the stress buffer dielectric layer until the second connecting surface and the 3D connecting part of the chip are at least partially exposed.
CN201810393579.0A 2018-04-27 2018-04-27 Semiconductor packaging structure and manufacturing method thereof Active CN110416166B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110631929.4A CN113380782B (en) 2018-04-27 2018-04-27 Semiconductor packaging structure
CN201810393579.0A CN110416166B (en) 2018-04-27 2018-04-27 Semiconductor packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810393579.0A CN110416166B (en) 2018-04-27 2018-04-27 Semiconductor packaging structure and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202110631929.4A Division CN113380782B (en) 2018-04-27 2018-04-27 Semiconductor packaging structure

Publications (2)

Publication Number Publication Date
CN110416166A CN110416166A (en) 2019-11-05
CN110416166B true CN110416166B (en) 2021-06-29

Family

ID=68346820

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201810393579.0A Active CN110416166B (en) 2018-04-27 2018-04-27 Semiconductor packaging structure and manufacturing method thereof
CN202110631929.4A Active CN113380782B (en) 2018-04-27 2018-04-27 Semiconductor packaging structure

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202110631929.4A Active CN113380782B (en) 2018-04-27 2018-04-27 Semiconductor packaging structure

Country Status (1)

Country Link
CN (2) CN110416166B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103441106A (en) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 Chip flip-mounting BGA encapsulating structure
CN103887258A (en) * 2012-12-21 2014-06-25 辉达公司 Chip package using interposer substrate with through-silicon vias
CN104217967A (en) * 2013-05-31 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 Semiconductor device and manufacturing method thereof
CN104701196A (en) * 2013-12-09 2015-06-10 矽品精密工业股份有限公司 Method for manufacturing semiconductor package
CN107221528A (en) * 2017-06-29 2017-09-29 江苏长电科技股份有限公司 Flush type antenna packages structure and its manufacture method
CN206992105U (en) * 2017-06-29 2018-02-09 江苏长电科技股份有限公司 Chip double-side encapsulates flush type antenna packages structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060245308A1 (en) * 2005-02-15 2006-11-02 William Macropoulos Three dimensional packaging optimized for high frequency circuitry
TWI416641B (en) * 2010-02-22 2013-11-21 Chipmos Technologies Inc Method for manufacturing a semiconductor structure
TWI556387B (en) * 2015-04-27 2016-11-01 南茂科技股份有限公司 Multi chip package structure, wafer level chip package structure and manufacturing method thereof
CN105140213B (en) * 2015-09-24 2019-01-11 中芯长电半导体（江阴）有限公司 A kind of chip-packaging structure and packaging method
CN107910305B (en) * 2017-12-28 2023-08-29 江阴长电先进封装有限公司 Packaging structure and packaging method of wafer-level back gold chip

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887258A (en) * 2012-12-21 2014-06-25 辉达公司 Chip package using interposer substrate with through-silicon vias
CN104217967A (en) * 2013-05-31 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 Semiconductor device and manufacturing method thereof
CN103441106A (en) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 Chip flip-mounting BGA encapsulating structure
CN104701196A (en) * 2013-12-09 2015-06-10 矽品精密工业股份有限公司 Method for manufacturing semiconductor package
CN107221528A (en) * 2017-06-29 2017-09-29 江苏长电科技股份有限公司 Flush type antenna packages structure and its manufacture method
CN206992105U (en) * 2017-06-29 2018-02-09 江苏长电科技股份有限公司 Chip double-side encapsulates flush type antenna packages structure

Also Published As

Publication number Publication date
CN113380782A (en) 2021-09-10
CN113380782B (en) 2023-11-07
CN110416166A (en) 2019-11-05

Similar Documents

Publication Publication Date Title
CN100479135C (en) Semiconductor device and a method for manufacturing of the same
CN102479762B (en) Heat dissipation gain type semiconductor assembly
JP7277056B2 (en) Electronics package with integrated electromagnetic interference shield and method of manufacturing same
TWI381497B (en) Overmolded semiconductor package with an integrated antenna
US9082767B2 (en) Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package
TW200933765A (en) Integrated circuit package system for shielding electromagnetic interference
CN104241255B (en) Electronic component module and its manufacture method
CN101246882A (en) Semiconductor device package with multi-chips and method of the same
JP2013065869A (en) Method of fabricating vertically mountable ic package
CN114512789A (en) Antenna packaging structure and manufacturing method thereof
CN114512790A (en) Antenna packaging structure and manufacturing method thereof
TWM506373U (en) Die packaging with fully or partially fused dielectric leads
CN107342233A (en) Low loss component flush type antenna packages structure and its manufacture method
CN112713098A (en) Antenna packaging structure and packaging method
CN112713097A (en) Antenna packaging structure and packaging method
CN109801883A (en) A kind of fan-out-type stacking encapsulation method and structure
CN110416166B (en) Semiconductor packaging structure and manufacturing method thereof
CN115832147A (en) Stack type packaging body structure, process and light-emitting chip device
CN102403236A (en) Chip exposed semiconductor device and production method thereof
CN114823557A (en) Fan-out type double-sided packaging structure and preparation method thereof
CN210692485U (en) Antenna packaging structure
CN108630626A (en) Without substrate encapsulation structure
CN114695127A (en) Chip packaging method, chip packaging body and electronic device
CN215266272U (en) High-radiating-plate-level fan-out packaging structure based on copper foil carrier plate
CN210692486U (en) Antenna packaging structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant