CN110401454A - A kind of two-part concentration sequence generator for probability calculation - Google Patents
A kind of two-part concentration sequence generator for probability calculation Download PDFInfo
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- CN110401454A CN110401454A CN201910678471.0A CN201910678471A CN110401454A CN 110401454 A CN110401454 A CN 110401454A CN 201910678471 A CN201910678471 A CN 201910678471A CN 110401454 A CN110401454 A CN 110401454A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/20—Increasing resolution using an n bit system to obtain n + m bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
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Abstract
A kind of two-part concentration sequence generator for probability calculation, belongs to integrated circuit fields, and in particular to a kind of switching current type two-part probability calculation concentration sequence generator.It solves the problems, such as not providing in the prior art and generates two-part concentration sequence generator.Analog signal can be directly generated the two-part that probabilistic operation is capable of handling and concentrate sequence by the present invention, two-part concentrates sequence to be obtained respectively by high-order section sequence generation circuitry and low level section sequence generation circuitry, centre can enhance sequence generation process to the insensitivity of bit reversal without using binary representation；Furthermore be conducive to the precision for improving multiplying in probability calculation in centralization distribution by the sequence that the sequence generator generates, and the sequence of this integrated distribution enhances the error correcting capability that system inverts single-bit.Present invention is mainly applied to high performance computation unit, digital signal processing units based on probability calculation, communicate codec unit etc..
Description
Technical field
The invention belongs to integrated circuit fields, and in particular to a kind of switching current type two-part probability calculation concentration sequence is raw
It grows up to be a useful person.
Background technique
Probability calculation is a kind of numerical value computing system of no weight, it is used shared by " 1 " in binary system random bit stream
Ratio carrys out the size of characterize data.Such as in following formula, for decimal fraction 0.25, with being represented in binary as 0.01, in probability
In calculating, it can be indicated with 0001,0100,00100100 etc..
(0.25)10=(0 × 20+0×2-1+1×2-2)10=(0.01)2
=(0001)SC4=(00100100)SC8=(11000000)SC8(formula one)；
One outstanding advantages of probability calculation are, after numerical value is generated by random bit sequence, the original arithmetic of complexity
Operation can be realized by very simple hardware logic electric circuit；For example, addition can realize that multiplication can by a data selector
With by one and Men Shixian, removing rule can be by JK flip-flop realization etc..
Another important feature of probability calculation is exactly fault-tolerance, especially for the bit brought by the external world radiates
Overturn mistake.
In random sequence, it is very small that error brought by mistake, which occurs, for a bit；By taking pure decimal as an example, than
In sequence 00100100, error brought by single bit upset is only 1/8, but in traditional binary system, single-bit is turned over
The raw wrong amplitude of forwarding can reach 0.5, and this characteristic has benefited from probability calculation, and the weight of each of which bit is all
Same.
One typical probability calculation system first has to comprising sequence generator, and sequence generator converts a signal into generally
The manageable random bit sequence of rate computing system.
Traditional sequence generator is constituted as shown in Figure 1, using digital comparator, and numerical value to be converted (can preparatory normalizing
Change between 0~1, and with binary representation) with random number between N number of 0~1 gradually compared with, available required stochastic ordering
Arrange DN.N number of random number is to be obtained by linear feedback shift register (LFSR), and signal is expressed as binary system shape from being input to
Formula is realized by analog-digital converter (ADC).Although probability calculation itself has preferable error resilience performance, binary system pair
Bit reversal is very sensitive, and storage unit (such as register), can under the irradiation by high energy particle under standard CMOS process
To lead to the bit flipping of stored data, i.e. single-particle inversion (SEU) phenomenon.
It include randomizer and ADC based on LFSR in conventional sequence generator, if one, LFSR are by SEU shadow
Sound occurs as overturning, by strong influence sequence generator performance；Secondly, ADC as the randomizer of LFSR before
The interface of digital and analog signaling, wherein necessarily comprising digital storage units such as registers, if ADC is exposed to irradiation for a long time
Under environment, risk can be also brought to the reliability service of system, ADC can add storage unit using triplication redundancy structure
Gu but this probability that circuit can only be made mistake occur reduces, and can not be inherently eliminated the influence of bit reversal bring.
Therefore, during carrying out binary representation to data by ADC in conventional sequence generator, very to bit reversal
Sensitivity, and it is logical by linear feedback shift register (LFSR) by random number between binary data and N number of 0~1 gradually compared with from
And generate random sequence DNDuring, single-particle inversion (SEU) phenomenon also easily occurs, conventional sequence generator is caused to generate
The error rate of random bit sequence is high, and accuracy rate is low.
In addition, according to newest studies have shown that such as being concentrated if the random sequence for participating in operation is converted into determine sequence
It is distributed and is uniformly distributed sequence, then operational precision will be greatly improved.And traditional sequence generator can not directly obtain
Such sequence needs to design circuit again, but still can face binary representation to determine sequence convert process with
And the influence of brought SEU.
It, can in order to improve the minimum resolution of numerical value represented by probability sequence as much as possible under limited sequence length
With the representation method decomposed using multistage.By taking two-part decomposes as an example, pure decimal is indicated with the probability sequence that sequence length is 2N,
The attainable minimum resolution of minimum value or representation method institute that the pure decimal can reach is 1/2N；If by former sequence
Column are decomposed into two isometric subsequencesWithAnd pure decimal is indicated with the method for following formula
Y, then the attainable minimum value of y institute is (1/N) 2–K, 2 are improved using the resolution ratio of two-part decomposition method in this wayK–1Times, K is
Integer greater than 1.It willReferred to as high N bit sequence, willReferred to as low N bit sequence.
The above-mentioned probability sequence representation method using two sections of decomposition can greatly improve the resolution ratio of numerical value expression with after
The precision that reforwarding is calculated, but do not provide the physical circuit for generating two-part probability sequence in the prior art, remain in theoretical rank
Section, and from the foregoing, it can be understood that the probability sequence generator of function admirable should be insensitive to bit flipping, otherwise multistage decomposes bring
Precision, which improves, reliably to be guaranteed, therefore, problem above urgent need to resolve.
Summary of the invention
The present invention is to solve the problems, such as not providing in the prior art and generate two-part concentration sequence generator, this hair
It is bright to provide a kind of two-part concentration sequence generator for probability calculation.
A kind of two-part concentration sequence generator for probability calculation, including sampling holder, subtracter, control logic
Circuit, high-order section sequence generation circuitry and low level section sequence generation circuitry；
High-order section sequence generation circuitry is identical with the internal structure of low level section sequence generation circuitry, and the two timesharing work
Make, high-order section sequence generation circuitry first works, works after low level section sequence generation circuitry；
Sampling holder, for keeping clock Clk in samplingSUnder the action of, analog voltage signal is acquired, is obtained
Voltage VSIt is input to the positive input terminal of high-order section sequence generation circuitry and the positive input terminal of subtracter simultaneously；
The negative input end of high-order section sequence generation circuitry is connect simultaneously with the negative input of its voltage output end and subtracter, and
The voltage of high-order section sequence generation circuitry voltage output end output is VA；
Subtracter, for received voltage VSWith voltage VAIt carries out making poor, the difference V ' of acquisitionAIt is sent into low level section sequence
The positive input terminal of generative circuit；
High-order section sequence generation circuitry, for receiving voltage V to its positive input terminalSVoltage V is received with its negative input endAInto
Row compares, and obtains comparison resultAnd in switch clock ClkAUnder the action of, according to the comparison resultReally
Determine the direction of displacement of output sequence, and passes through the high-order section N concentrations sequence after the output displacement of sequence output end
Wherein,ExtremelyHigh-order section N concentrations sequence is respectively indicated from low to high direction, the 1st to N
Digital signal, N are positive integer；
The negative input end of low level section sequence generation circuitry is connect with its voltage output end, low level section sequence generation circuitry voltage
The voltage of output end output is VB；
Low level section sequence generation circuitry, for receiving voltage V ' to its positive input terminalAVoltage V is received with its negative input endBInto
Row compares, and obtains comparison resultAnd in switch clock ClkBUnder the action of, according to the comparison resultReally
Determine the direction of displacement of output sequence, and passes through N concentration sequences of low level section after the output displacement of sequence output end
Wherein,ExtremelyN concentration sequences of low level section are respectively indicated from low to high direction, the number of 1 to N
Word signal；
Control logic circuit, for keeping clock Clk in samplingSUnder the action of resetted, after the completion of reset, switching
Clock ClkDUnder the action of, comparison result based on the receivedDetermine the switch clock Clk of outputAState and root
According to received comparison resultDetermine the switch clock Clk of outputBState；TS=MTD, and meet N > M > N/2；
Wherein, TSClock Clk is kept for samplingSPeriod, TDFor switch clock ClkDPeriod, M is coefficient.
Preferably, control logic circuit, for keeping clock Clk in samplingSUnder the action of resetted, reset complete
Afterwards, in switch clock ClkDUnder the action of, comparison result based on the receivedDetermine the switch clock Clk of outputAShape
State and based on the received comparison resultDetermine the switch clock Clk of outputBState detailed process are as follows:
Control logic circuit keeps clock Clk in samplingSUnder the action of resetted, after the completion of reset, high-order section sequence
Generative circuit is started to work；
During the work of high-order section sequence generation circuitry, control logic circuit is in switch clock ClkDRising edge time,
MonitoringLogic level, when monitoring two adjacent momentLogic level, be first " 1 ", be afterwards
When " 0 ", the switch clock Clk that outputs itAState set 0, and make switch clock ClkBState with switch clock ClkDIt protects
It holds unanimously, at this point, high-order section sequence generation circuitry stops working, low level section sequence generation circuitry is started to work；
During the work of low level section sequence generation circuitry, control logic circuit is in switch clock ClkDRising edge time,
Continuous monitoringLogic level, when monitoring two adjacent momentLogic level, be first " 1 ",
When being afterwards " 0 ", the switch clock Clk that outputs itBLogic level set 0, at this point, low level section sequence generation circuitry stop work
Make, sequence converts.
Preferably, high-order section sequence generation circuitry include comparator U1, it is bidirectional shift register, N number of constant-current source, N number of
Logic switch, operational amplifier OP1, sampling resistor RAWith the first low-pass filter；
Positive input terminal of the positive input terminal of comparator U1 as high-order section sequence generation circuitry；
Negative input end of the negative input end of comparator U1 as high-order section sequence generation circuitry；
Comparator U1 is by received voltage VSWith voltage VAAfter comparing, by the comparison result of acquisitionIt is sent into simultaneously
Bidirectional shift register and control logic circuit, bidirectional shift register is in switch clock ClkAUnder the action of, it is tied according to comparing
FruitLogic level determine the direction of displacement of output sequence after, the high-order section N concentrations sequence after output displacement
After N number of constant-current source is connected with N number of logic switch respectively, it is connected in parallel on power supply VDDIt is defeated with the reverse phase of operational amplifier OP1
Enter between end；
N number of digital signalExtremelyIt is respectively used to control the control terminal of N number of logic switch；
The inverting input terminal and sampling resistor R of operational amplifier OP1AOne end connection, operational amplifier OP1's is same opposite
Input termination power ground, the output end and sampling resistor R of operational amplifier OP1AThe other end and the first low-pass filter it is defeated
Enter end connection, voltage output end of the voltage output end of the first low-pass filter as high-order section sequence generation circuitry；
Bidirectional shift register receives switch clock ClkASwitch clock of the port as high-order section sequence generation circuitry
Signal input part；
The high-order section N concentrations sequence of bidirectional shift register outputOutput end as high-order section sequence
The sequence output end of column-generation circuit.
Preferably, the bidirectional shift register in high-order section sequence generation circuitry is in switch clock ClkAUnder the action of,
According to comparison resultLogic level determine output sequence direction of displacement detailed process are as follows:
Bidirectional shift register is in switch clock ClkAUnder the action of, work as comparison resultLogic level be ' 1 '
When, the numerical value controlled in bidirectional shift register output sequence lowest order moves to right, and mends ' 1 ' in lowest order, works as comparison resultLogic level when being ' 0 ', the numerical value controlled in bidirectional shift register output sequence highest order moves to left, and most
A high position mends ' 0 '.
Preferably, low level section sequence generation circuitry include comparator U2, it is bidirectional shift register, N number of constant-current source, N number of
Logic switch, operational amplifier OP2, sampling resistor RBWith the second low-pass filter；
Positive input terminal of the positive input terminal of comparator U2 as low level section sequence generation circuitry；
Negative input end of the negative input end of comparator U2 as low level section sequence generation circuitry；
Comparator U2 is by received voltage VSSubtract voltage V 'AAfterwards, by the comparison result of acquisitionIt is sent into simultaneously double
To shift register and control logic circuit, bidirectional shift register is in switch clock ClkBUnder the action of, according to comparison resultLogic level determine the direction of displacement of output sequence after, N concentration sequences of low level section after output displacement
After N number of constant-current source is connected with N number of logic switch respectively, it is connected in parallel on power supply VDDIt is defeated with the reverse phase of operational amplifier OP2
Enter between end；
N number of digital signalExtremelyIt is respectively used to control the control terminal of N number of logic switch；
The inverting input terminal and sampling resistor R of operational amplifier OP2BOne end connection, operational amplifier OP2's is same opposite
Input termination power ground, the output end and sampling resistor R of operational amplifier OP2BThe other end and the second low-pass filter it is defeated
Enter end connection, voltage output end of the voltage output end of the second low-pass filter as low level section sequence generation circuitry；
Bidirectional shift register receives switch clock ClkBSwitch clock of the port as low level section sequence generation circuitry
Signal input part；
N concentration sequences of low level section of bidirectional shift register outputOutput end as low level Duan Xu
The sequence output end of column-generation circuit.
Preferably, the bidirectional shift register in low level section sequence generation circuitry is in switch clock ClkBUnder the action of,
According to comparison resultLogic level determine output sequence direction of displacement detailed process are as follows:
Bidirectional shift register is in switch clock ClkBUnder the action of, work as comparison resultLogic level be ' 1 '
When, the numerical value controlled in bidirectional shift register output sequence lowest order moves to right, and mends ' 1 ' in lowest order, works as comparison resultLogic level when being ' 0 ', the numerical value controlled in bidirectional shift register output sequence highest order moves to left, and most
A high position mends ' 0 '.
Preferably, control logic circuit includes d type flip flopWith door AndA1, NAND gate
AndA2And door AndB1, NAND gate AndB2, NOT gate YA1, NOT gate YA2With NOT gate YB1；
With door AndA1First input end and with door AndB1First input end when being used as the switch of control logic circuit
Clock ClkDReceiving end；
With door AndA1The second input terminal simultaneously with NAND gate AndA2Output end and NOT gate YA2Input terminal connection；
With door AndA1Output end for exporting switch clock ClkA, and simultaneously and d type flip flopClock signal input
End, d type flip flopClock signal input terminal connection；
D type flip flopData input pin, for receiving the comparison result of high-order section sequence generation circuitry outputD type flip flopReset signal input terminal for receive sampling keep clock ClkS, and d type flip flopAnswer
Position signal input part while and d type flip flopReset signal input terminal, d type flip flopReset signal input terminal and D touching
Send out deviceReset signal input terminal connection；
D type flip flopOutput end simultaneously NAND gate YA1Input terminal and d type flip flopData input pin connection, D
TriggerOutput end and NAND gate AndA2First input end connection, NOT gate YA1Output end and NAND gate AndA2
The connection of two input terminals；
With door AndB1The second input terminal NAND gate YA2Output end connection, with door AndB1Third input terminal with it is non-
Door AndB2Output end connection,
With door AndB1Output end for exporting switch clock ClkB, and simultaneously and d type flip flopClock signal input
End, d type flip flopClock signal input terminal connection；
D type flip flopData input pin, for receive low level section sequence generation circuitry output comparison result
D type flip flopOutput end simultaneously NAND gate YB1Input terminal and d type flip flopData input pin connection, D
TriggerOutput end and NAND gate AndB2First input end connection, NOT gate YB1Output end and NAND gate AndB2
The connection of two input terminals.
Preferably, with door AndA1The second input terminal and NAND gate AndA2Output end between be in series with even number
NOT gate, for door AndA1Output end output switch clock ClkAIt is delayed, delay time is less than TD。
Preferably, with door AndB1Third input terminal and NAND gate AndB2Output end between to be in series with even number non-
Door, for door AndB1Output end output switch clock ClkBIt is delayed, delay time is less than TD。
When the traditional random sequence generated with Fig. 1 circuit does multiplying, precision does not ensure that very high.Existing research
Prove that the sequence using determining distribution can effectively improve the accuracy of calculating, basic ideas are by the generation of two sequences
Mode is fixed, and one of sequence is in integrated distribution (1 concentrates at one end), another sequence is evenly distributed, and (1 is in the sequence
Approximation is spacedly distributed), being uniformly distributed can be obtained by centralization distribution.Integrated distribution sequence can be converted by binary numeral
It obtains, but needs by counter, this can be such that the scale of circuit increases, and binary representation can be such that sequence anti-single particle overturns
Degradation, most important is that counter can make conversion process waste a large amount of clock cycle.And sequence disclosed by the invention is raw
Structure of growing up to be a useful person sequence generated inherently integrated distribution, eliminate the process of conversion.
The invention has the beneficial effects that the invention discloses a kind of novel probability calculation sequence generator structure,
Analog signal can be directly generated the two-part that probabilistic operation is capable of handling and concentrate sequence by it, and centre is without using binary form
Show, sequence generation process can be enhanced to the insensitivity of bit reversal, and its resolution ratio of numerical value represented by two-part sequence compared with
General Sequences improve at least 2K–1Times；Furthermore the sequence generated by the sequence generator is conducive to improve in centralization distribution
The precision of multiplying in probability calculation, and the sequence of this integrated distribution enhances the error correction energy that system inverts single-bit
Power.
The suitable Embedded of the sequence generator simultaneously forms probability calculation SOC chip with other circuits, be suitable for speed and
Required precision occasion less high and more demanding to fault-tolerance.
Due to these technical characterstics, present invention is mainly applied to high performance computation unit, number letters based on probability calculation
Number processing unit, communication codec unit etc. can be extensive based on the said units that concentration sequence generator of the present invention is constituted
Applied to neural network, control logic, the fields such as communication system.
Detailed description of the invention
Fig. 1 is conventional sequence generator structural schematic diagram；
Fig. 2 is the structural schematic diagram that a kind of two-part for probability calculation of the present invention concentrates sequence generator；
Fig. 3 is the schematic illustration of control logic circuit 3；
Fig. 4 is the voltage V that control logic circuit 3 is obtained according to samplingSDynamic adjustment two-part concentrates the work of sequence output
Make schematic illustration.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without making creative work it is obtained it is all its
Its embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
Illustrate originally to be embodiment referring to fig. 2, a kind of two-part concentration for probability calculation described in present embodiment
Sequence generator, including sampling holder 1, subtracter 2, control logic circuit 3, high-order section sequence generation circuitry 4 and low level section
Sequence generation circuitry 5；
High-order section sequence generation circuitry 4 is identical with the internal structure of low level section sequence generation circuitry 5, and the two timesharing
Work, high-order section sequence generation circuitry 4 first work, work after low level section sequence generation circuitry 5；
Sampling holder 1, for keeping clock Clk in samplingSUnder the action of, analog voltage signal is acquired, is obtained
The voltage V obtainedSIt is input to the positive input terminal of high-order section sequence generation circuitry 4 and the positive input terminal of subtracter 2 simultaneously；
The negative input end of high-order section sequence generation circuitry 4 is connect simultaneously with the negative input of its voltage output end and subtracter 2,
And the voltage of high-order 4 voltage output end output of section sequence generation circuitry is VA；
Subtracter 2, for received voltage VSWith voltage VAIt carries out making poor, the difference V ' of acquisitionAIt is sent into low level section sequence
The positive input terminal of generative circuit 5；
High-order section sequence generation circuitry 4, for receiving voltage V to its positive input terminalSVoltage V is received with its negative input endAInto
Row compares, and obtains comparison resultAnd in switch clock ClkAUnder the action of, according to the comparison resultReally
Determine the direction of displacement of output sequence, and passes through the high-order section N concentrations sequence after the output displacement of sequence output end
Wherein,ExtremelyHigh-order section N concentrations sequence is respectively indicated from low to high direction, the number of 1 to N
Word signal, N are positive integer；
The negative input end of low level section sequence generation circuitry 5 is connect with its voltage output end, 5 electricity of low level section sequence generation circuitry
The voltage for pressing output end output is VB；
Low level section sequence generation circuitry 5, for receiving voltage V ' to its positive input terminalAVoltage V is received with its negative input endB
It is compared, obtains comparison resultAnd in switch clock ClkBUnder the action of, according to the comparison result
It determines the direction of displacement of output sequence, and passes through N concentration sequences of low level section after the output displacement of sequence output end
Wherein,ExtremelyN concentration sequences of low level section are respectively indicated from low to high direction, the number of 1 to N
Word signal；
Control logic circuit 3, for keeping clock Clk in samplingSUnder the action of resetted, after the completion of reset, opening
Close clock ClkDUnder the action of, comparison result based on the receivedDetermine the switch clock Clk of outputAState and
Comparison result based on the receivedDetermine the switch clock Clk of outputBState；TS=MTD, and meet N > M > N/2；
Wherein, TSClock Clk is kept for samplingSPeriod, TDFor switch clock ClkDPeriod, M is coefficient.
In present embodiment, high-order section and low level section sequence generation circuitry distinguish subject clock signal ClkAAnd ClkBControl,
Work as ClkAOr ClkBWhen showing as rising edge, corresponding shift register carries out shifting function, according to the output level of comparator
To low displacement or to Gao Weiyi；Therefore, " 1 " and/or " 0 " integrated distribution in the sequence of output, works as ClkAOr ClkBFor low electricity
Usually, corresponding bidirectional shift register no longer carries out shifting function, output sequenceOrIt remains unchanged.
When a kind of two-part for probability calculation of the present invention concentrates sequence generator specific works, high-order section sequence
5 timesharing sequential working of column-generation circuit 4 and low level section sequence generation circuitry, such as: if conversion incipient stage high-order section sequence is raw
It works at circuit 4, then low level section sequence generation circuitry 5 does not work, at this point, ClkAWith ClkDState is consistent, ClkBIt shows as
Low level, and continuous two rising edge clocks of 3 real-time detection high position section sequence generation circuitry of control logic circuit 4
Value, when meeting certain condition, makes ClkABecome low level, ClkBWith ClkDState is consistent, it may be assumed that high-order section sequence generates
Circuit 4 stops working, and low level section sequence generation circuitry 5 is started to work, at this point, control logic circuit 3 continues to test low level Duan Xu
5 continuous two rising edge clocks of column-generation circuitValue, Clk is made when meeting certain conditionBBecome low electricity again
It is flat, at this point, entire conversion process terminates, obtain required two-part sequenceWith
Due to TS=MTD, and meet N > M > N/2；Mean to sample hold period TSEnd represent the periodic sampling and arrive
Voltage VSCorresponding Serial No. conversion finishes, and also implies that next sampled voltage will start to convert.
It follows that each exclusive portion of time of the generating process of two sections of sequence each section sequences, that is, when each section works
Between be not overlapped, be sequentially generated by high-order section to low level section, high-order section sequence generation circuitry 4 and low level section sequence generation circuitry 5
Work is controlled with stopping by respective clock signal.
Illustrate this preferred embodiment referring to fig. 2, in this preferred embodiment, control logic circuit 3, for being protected in sampling
Hold clock ClkSUnder the action of resetted, after the completion of reset, in switch clock ClkDUnder the action of, compare knot based on the received
FruitDetermine the switch clock Clk of outputAState and comparison result based on the receivedDetermine output
Switch clock ClkBState detailed process are as follows:
Control logic circuit 3 keeps clock Clk in samplingSUnder the action of resetted, after the completion of reset, high-order section sequence
Generative circuit 4 is started to work；
During the work of high-order section sequence generation circuitry 4, control logic circuit 3 is in switch clock ClkDRising edge when
It carves, monitoringLogic level, when monitoring two adjacent momentLogic level, be first " 1 ",
When being afterwards " 0 ", the switch clock Clk that outputs itAState set 0, and make switch clock ClkBState with and switch clock
ClkDIt is consistent, at this point, high-order section sequence generation circuitry 4 stops working, low level section sequence generation circuitry 5 is started to work；
During low level section sequence generation circuitry 5 works, control logic circuit 3 is in switch clock ClkDRising edge when
It carves, it is continuous to monitorLogic level, when monitoring two adjacent momentLogic level, first for
" 1 ", when being afterwards " 0 ", the switch clock Clk that outputs itBLogic level set 0, at this point, low level section sequence generation circuitry 5 is stopped
It only works, sequence converts.
Illustrate this preferred embodiment referring to fig. 2, in this preferred embodiment, high-order section sequence generation circuitry 4 include than
Compared with device U1, bidirectional shift register, N number of constant-current source, N number of logic switch, operational amplifier OP1, sampling resistor RAIt is low with first
Bandpass filter；
Positive input terminal of the positive input terminal of comparator U1 as high-order section sequence generation circuitry 4；
Negative input end of the negative input end of comparator U1 as high-order section sequence generation circuitry 4；
Comparator U1 is by received voltage VSWith voltage VAAfter comparing, by the comparison result of acquisitionIt is sent into simultaneously
Bidirectional shift register and control logic circuit 3, bidirectional shift register is in switch clock ClkAUnder the action of, it is tied according to comparing
FruitLogic level determine the direction of displacement of output sequence after, the high-order section N concentrations sequence after output displacement
After N number of constant-current source is connected with N number of logic switch respectively, it is connected in parallel on power supply VDDIt is defeated with the reverse phase of operational amplifier OP1
Enter between end；
N number of digital signalExtremelyIt is respectively used to control the control terminal of N number of logic switch；
The inverting input terminal and sampling resistor R of operational amplifier OP1AOne end connection, operational amplifier OP1's is same opposite
Input termination power ground, the output end and sampling resistor R of operational amplifier OP1AThe other end and the first low-pass filter it is defeated
Enter end connection, voltage output end of the voltage output end of the first low-pass filter as high-order section sequence generation circuitry 4；
Bidirectional shift register receives switch clock ClkASwitch clock of the port as high-order section sequence generation circuitry 4
Signal input part；
The high-order section N concentrations sequence of bidirectional shift register outputOutput end as high-order section sequence
The sequence output end of column-generation circuit 4.
Illustrate this preferred embodiment referring to fig. 2, it is double in high-order section sequence generation circuitry 4 in this preferred embodiment
To shift register in switch clock ClkAUnder the action of, according to comparison resultLogic level determine output sequence
Direction of displacement detailed process are as follows:
Bidirectional shift register is in switch clock ClkAUnder the action of, work as comparison resultLogic level be ' 1 '
When, the numerical value controlled in bidirectional shift register output sequence lowest order moves to right, and mends ' 1 ' in lowest order, works as comparison resultLogic level when being ' 0 ', the numerical value controlled in bidirectional shift register output sequence highest order moves to left, and most
A high position mends ' 0 '.
In present embodiment, whenLow (height) level is remained, then in clock signal ClkAUnder the action of shift and post
Storage state is by highest (low) positionGradually become 0 (1), referred to as left (right side), which is moved, mends 0 (1).Therefore, high-order section sequence generation circuitry
(4) high-order section sequence is exportedIt is distributed in centralization, i.e., 1 if it exists, then concentrates on the low level of high-order section sequence, 0 if it exists, then
Concentrate on a high position for high-order section sequence.
Illustrate this preferred embodiment referring to fig. 2, in this preferred embodiment, low level section sequence generation circuitry 5 include than
Compared with device U2, bidirectional shift register, N number of constant-current source, N number of logic switch, operational amplifier OP2, sampling resistor RBIt is low with second
Bandpass filter；
Positive input terminal of the positive input terminal of comparator U2 as low level section sequence generation circuitry 5；
Negative input end of the negative input end of comparator U2 as low level section sequence generation circuitry 5；
Comparator U2 is by received voltage VSSubtract voltage V 'AAfterwards, by the comparison result of acquisitionIt is sent into simultaneously double
To shift register and control logic circuit 3, bidirectional shift register is in switch clock ClkBUnder the action of, according to comparison resultLogic level determine the direction of displacement of output sequence after, N concentration sequences of low level section after output displacement
After N number of constant-current source is connected with N number of logic switch respectively, it is connected in parallel on power supply VDDIt is defeated with the reverse phase of operational amplifier OP2
Enter between end；
N number of digital signalExtremelyIt is respectively used to control the control terminal of N number of logic switch；
The inverting input terminal and sampling resistor R of operational amplifier OP2BOne end connection, operational amplifier OP2's is same opposite
Input termination power ground, the output end and sampling resistor R of operational amplifier OP2BThe other end and the second low-pass filter it is defeated
Enter end connection, voltage output end of the voltage output end of the second low-pass filter as low level section sequence generation circuitry 5；
Bidirectional shift register receives switch clock ClkBSwitch clock of the port as low level section sequence generation circuitry 5
Signal input part；
N concentration sequences of low level section of bidirectional shift register outputOutput end as low level Duan Xu
The sequence output end of column-generation circuit 5.
Preferably, sampling resistor RAResistance value be sampling resistor RBThe 2 of resistance valueKTimes.
Illustrate this preferred embodiment referring to fig. 2, it is double in low level section sequence generation circuitry 5 in this preferred embodiment
To shift register in switch clock ClkBUnder the action of, according to comparison resultLogic level determine output sequence
Direction of displacement detailed process are as follows:
Bidirectional shift register is in switch clock ClkBUnder the action of, work as comparison resultLogic level be ' 1 '
When, the numerical value controlled in bidirectional shift register output sequence lowest order moves to right, and mends ' 1 ' in lowest order, works as comparison resultLogic level when being ' 0 ', the numerical value controlled in bidirectional shift register output sequence highest order moves to left, and most
A high position mends ' 0 '.
In present embodiment, whenLow (height) level is remained, then in clock signal ClkBUnder the action of shift and post
Storage state is by highest (low) positionGradually become 0 (1), referred to as left (right side), which is moved, mends 0 (1).Therefore, low level section sequence is raw
Low level section sequence is exported at circuit 4It is distributed in centralization, i.e., 1 if it exists, then the low level of low level section sequence is concentrated on, if 0 deposits
Then concentrating on a high position for low level section sequence.
Illustrate this preferred embodiment referring to Fig. 3, in this preferred embodiment, control logic circuit 3 includes d type flip flop With door AndA1, NAND gate AndA2And door AndB1, NAND gate AndB2, NOT gate YA1, NOT gate YA2With
NOT gate YB1；
With door AndA1First input end and with door AndB1First input end be used as the switch of control logic circuit 3
Clock ClkDReceiving end；
With door AndA1The second input terminal simultaneously with NAND gate AndA2Output end and NOT gate YA2Input terminal connection；
With door AndA1Output end for exporting switch clock ClkA, and simultaneously and d type flip flopClock signal input
End, d type flip flopClock signal input terminal connection；
D type flip flopData input pin, the comparison result exported for receiving high-order section sequence generation circuitry 4D type flip flopReset signal input terminal for receive sampling keep clock ClkS, and d type flip flopAnswer
Position signal input part while and d type flip flopReset signal input terminal, d type flip flopReset signal input terminal and D touching
Send out deviceReset signal input terminal connection；
D type flip flopOutput end simultaneously NAND gate YA1Input terminal and d type flip flopData input pin connection, D
TriggerOutput end and NAND gate AndA2First input end connection, NOT gate YA1Output end and NAND gate AndA2
The connection of two input terminals；
With door AndB1The second input terminal NAND gate YA2Output end connection, with door AndB1Third input terminal with it is non-
Door AndB2Output end connection,
With door AndB1Output end for exporting switch clock ClkB, and simultaneously and d type flip flopClock signal input
End, d type flip flopClock signal input terminal connection；
D type flip flopData input pin, for receive low level section sequence generation circuitry 5 output comparison result
D type flip flopOutput end simultaneously NAND gate YB1Input terminal and d type flip flopData input pin connection, D
TriggerOutput end and NAND gate AndB2First input end connection, NOT gate YB1Output end and NAND gate AndB2
The connection of two input terminals.
In present embodiment,WithIt is cascaded,WithIt is cascaded.
More preferably embodiment are as follows: with door AndA1The second input terminal and NAND gate AndA2Output end it
Between be in series with even number NOT gate, for door AndA1Output end output switch clock ClkAIt is delayed, delay time
Less than TD。
More preferably embodiment are as follows: with door AndB1Third input terminal and NAND gate AndB2Output end between
Be in series with even number NOT gate, for door AndB1Output end output switch clock ClkBIt is delayed, delay time is small
In TD。
The specific work process of Fig. 3 are as follows:
Initial time, due toWithState be 0, with door AndA1Output ClkASame ClkDIt is consistent, because
This, the bi-directional shift operation of high-order section sequence generation circuitry 4 brings into operation,WithAlso it can receive and save
The state of continuous two clocks；With door AndB1Output ClkBIt is then low level, therefore, pair of low level section sequence generation circuitry 5
To shift register andWithIt does not work.
WhenAndWhen, InA=0, with door AndA1It will make ClkABecome low level, but due to InAPropagate road
The delay of even number NOT gate, Clk on diameterAIt will appear a burst pulse before it will be lower, in the rear high-lying Duan Xu of burst pulse
Column-generation circuit 4 stops working；At the same timeWithState will make and door AndB1Output ClkBStart same ClkDIt protects
It holds unanimously, the bi-directional shift operation of such low level circuit brings into operation,WithAlso it can receive and saveEven
The state of continuous two clocks.
WhenAndWhen, InB=0, with door AndB1It will make ClkBBecome low level, but due to InBPropagate road
The delay of even number NOT gate, Clk on diameterBIt will appear a burst pulse, the low level circuit after burst pulse before it will be lower
It stops working, entire conversion process terminates.
As shown in Fig. 2, VAAnd VSBeing input in 2 subtracter of subtracter and obtaining output is V 'A=VS-VA, V 'AIt is input to low level
The positive input terminal of section 5 comparator of sequence generation circuitry, comparator complete V 'AWith VBVoltage compare, export a logic levelTherefore, V 'AV can be analogous to for the effect of low level section sequence generation circuitry 5SFor high-order section sequence generation circuitry
4。
As the analog voltage V sampledS> VAWhen,For high level, high-order section sequenceIn clock ClkAWork
Benefit 1, V is moved to right underAIt incrementally increases；
Work as VS<VAWhen,For low level,In ClkAUnder the action of move to left benefit 0, VAIt gradually reduces.In high-order section
In the generating process of sequence, when control logic circuit 3 detectsWhen becoming low level by high level, just by ClkABecome
For low level, circuit high-order in this way stops working, and low level circuit is started to work, at this time ClkBClock signal is become from low level.
The course of work of low level section sequence generation circuitry 5 and high-order section sequence generation circuitry 4 are almost the same.
As V 'A>VBWhen,For high level, low level section sequenceIn clock ClkBUnder the action of move to right benefit 1, VBBy
Step increases；
As V 'A<VBWhen,For low level, low level section sequenceIn ClkBUnder the action of move to left benefit 0, VBGradually subtract
It is small.
In the generating process of low level section sequence, when control logic circuit 3 detectsHigh level becomes low level
When, just by ClkBBecome low level, high-order so to stop working with low level circuit, entire conversion process terminates at this time.
In sampling hold period TSDuring continuing, sequence generator is successively dynamically adjustedWithIn 1 number make VA+VB
Gradually approach VS；Detailed process is, for high-order section sequence generation circuitry, to flow through sampling resistor RATotal current be IA, then amplifier
OP1Output through the reversed amplified voltage value of wave filter 1:1
Wherein IDFor the current value of constant-current source；
It can similarly obtain
When conversion process terminates or sample hold period finish time, VA+VBIt should be with VSAs close possible to, it can thus be appreciated that:
So far, sequence generator completes sampling analogue voltage VSThe conversion of Serial No. is concentrated to two-part, thus real
Use is showedWithIn ratio shared by " 1 " characterize VS, and the process eliminates binary representation.
Therefore, work as VSIt is corresponding when being minimized 0WithIn be all 0；Work as VSIt is maximized i.e. full range voltage VDDWhen,
It is correspondingWithIn be all 1, then VDDNeed to meet following relational expression:
VDD≈NRBID(2K+1)≈2KNRBID。
What the present invention obtainedWithThe two-part that the is constituted sampled voltage V that concentrated sequence characterizedS, this two sections
The representation method of decomposition is easy to extend to the situation more than two sections.For example, the case where being decomposed for three-stage, in two-part sequence
On the basis of column-generation device, increase a subtracter and one low level section sequence generation circuitry, aforementioned low level section sequence is raw
At the output V of circuit 5BIt is sent to newly-increased subtracter, obtains output V 'B=VS-VA-VB, by V 'BTime low level section sequence is inputted to generate
The structure of circuit, the secondary low level section sequence generation circuitry and aforementioned low level section sequence generation circuitry 5 is completely the same, and difference only exists
In the sampling resistor R of secondary low level section sequence generation circuitryCMeet RB=2KRC, i.e., adjacent two positions section sequence generation circuitry
Sampling resistor difference 2KTimes；It is generated whether the bidirectional shift register work of secondary low level section sequence generation circuitry by low level section sequence
The clock signal Clk of circuit 5CRhythm control, ClkCAlso it is obtained by control logic circuit 3, at this point, control logic circuit 3 is defeated
Entering also includes time low level section sequence generation circuitry outputSince sequence total length is 2N, three-stage is decomposed
Every partial sequence length be 2N/3.Concentrate the course of work of sequence generator can be with the rest may be inferred other multisection types.
Verification test: be now described in detail step by step by taking Fig. 4 as an example control logic circuit 3 dynamically adjust two-part concentrate sequence with it is defeated
Entering the adaptable working principle of analog signal, (sequence total length is 16 in Fig. 4, high-order section sequenceWith low level section sequenceIt is long
Degree is 8, the analog voltage V sampledS=0.6VDD, take RA/RB=23, it may be assumed that the K=3 in background technique in formula two；Fig. 4
Middle dash area represents this part and wouldn't work or stop working):
1) initial time t=kTS, i.e. at the beginning of k-th of change-over period, d type flip flop is cleared, control logic circuit
3 by ClkABecome normal clock signal, ClkBMaintain low level constant；Assuming thatWithIt is all the sequence for only including 0 at this time,
Due to VS>VA=0, then Start gradually to move to right benefit 1；In the processWithIn store the first two clock
Rising edgeState；
2) work as t=kTS+4TDWhen,Left side half is 1, it is meant that VS>VA=0.5VDD, then It will be after
It is continuous to move to right benefit 1；At this timeWithThe state of latch is 1；
3) work as t=kTS+5TDWhen,In include 51, then have VS<VA=0.625VDD, thenIt will
Move to left benefit 0；At this timeWithIt is depositedPast state be still 1；
4) work as t=kTS+6TDWhen,T=kT will be returned toS+4TDWhen state, at this timeThe first two clock
State will makeAccording to analysis before, high-order section clock ClkAIn t=kTS+6TDMoment will occur one
A burst pulse, then becomes low level, under the action of burst pulseComplete it is last move to left state before a benefit 0 returns to,
So far high-order section sequence generation finishes, and low level circuit is started to work, ClkBNormal clock signal is become from low level；Due to
No longer change, then VAIt is maintained at 0.5VDD, due to VS–VA=0.1VDD>VB=0, thenStart gradually to move to right benefit
1；WithStart to save two rising edge clocksState；
5) work as t=kTS+12TDWhen,In include 61, it is meant that VS–VA=0.1VDD>VB=0.0938VDD, thenIt will continue to move to right benefit 1；WithThe state of latch is 1；
6) work as t=kTS+13TDWhen,In include 71, then have VS–VA=0.1VDD<VB=0.1094VDD, thenBenefit 0 will be moved to left；At this timeWithIt is depositedPast state be still 1；
7) work as t=kTS+14TDWhen,It will be returned to t=kTS+12TDWhen state, at this timeThe first two clock
State will makeAccording to analysis before, high-order section clock ClkBIn t=kTS+14TDMoment will occur
One burst pulse, then becomes low level, under the action of burst pulseIt completes last to move to left shape before a benefit 0 returns to
State, so far low level section sequence is also generated and is finished, and low level circuit stops working, and entire sequence conversion finishes.
Finally obtain VA=(4/8) VDD, VB=(2–3*6/8)VDD, then VA+VB=0.5938VDD≈VS=0.6VDD.Furthermore
It is also seen that if not doing segment processing, the sequence that total length is 16 can achieve closest to VSValue be 10/16=
0.625, absolute error is the 0.025/0.0062 ≈ 2 of two-part sequence2=4 times.
To sum up, the accuracy of the generator formation sequence of multisection type integrated distribution sequence of the invention can be obtained.
Although describing the present invention herein with reference to specific embodiment, it should be understood that, these realities
Apply the example that example is only principles and applications.It should therefore be understood that can be carried out to exemplary embodiment
Many modifications, and can be designed that other arrangements, without departing from spirit of the invention as defined in the appended claims
And range.It should be understood that different appurtenances can be combined by being different from mode described in original claim
Benefit requires and feature described herein.It will also be appreciated that the feature in conjunction with described in separate embodiments can be used
Other embodiments.
Claims (9)
1. a kind of two-part for probability calculation concentrates sequence generator, which is characterized in that including sampling holder (1), subtract
Musical instruments used in a Buddhist or Taoist mass (2), control logic circuit (3), high-order section sequence generation circuitry (4) and low level section sequence generation circuitry (5)；
High-order section sequence generation circuitry (4) is identical with the internal structure of low level section sequence generation circuitry (5), and the two timesharing
Work, high-order section sequence generation circuitry (4) first work, and low level section sequence generation circuitry (5) works afterwards；
Sampling holder (1), for keeping clock Clk in samplingSUnder the action of, analog voltage signal is acquired, acquisition
Voltage VSIt is input to the positive input terminal of high-order section sequence generation circuitry (4) and the positive input terminal of subtracter (2) simultaneously；
The negative input end of high-order section sequence generation circuitry (4) is connect simultaneously with the negative input of its voltage output end and subtracter (2),
And the voltage of high-order section sequence generation circuitry (4) voltage output end output is VA；
Subtracter (2), for received voltage VSWith voltage VAIt carries out making poor, the difference V ' of acquisitionAIt is raw to be sent into low level section sequence
At the positive input terminal of circuit (5)；
High-order section sequence generation circuitry (4), for receiving voltage V to its positive input terminalSVoltage V is received with its negative input endAIt carries out
Compare, obtains comparison resultAnd in switch clock ClkAUnder the action of, according to the comparison resultIt determines
The direction of displacement of output sequence, and pass through the high-order section N concentrations sequence after the output displacement of sequence output end
Wherein,ExtremelyHigh-order section N concentrations sequence is respectively indicated from low to high direction, the 1st to N number letters
Number, N is positive integer；
The negative input end of low level section sequence generation circuitry (5) is connect with its voltage output end, low level section sequence generation circuitry (5) electricity
The voltage for pressing output end output is VB；
Low level section sequence generation circuitry (5), for receiving voltage V ' to its positive input terminalAVoltage V is received with its negative input endBInto
Row compares, and obtains comparison resultAnd in switch clock ClkBUnder the action of, according to the comparison resultReally
Determine the direction of displacement of output sequence, and passes through N concentration sequences of low level section after the output displacement of sequence output end
Wherein,ExtremelyN concentration sequences of low level section are respectively indicated from low to high direction, the 1st to N number letters
Number；
Control logic circuit (3), for keeping clock Clk in samplingSUnder the action of resetted, after the completion of reset, switch when
Clock ClkDUnder the action of, comparison result based on the receivedDetermine the switch clock Clk of outputAState and according to
Received comparison resultDetermine the switch clock Clk of outputBState；TS=MTD, and meet N > M > N/2；
Wherein, TSClock Clk is kept for samplingSPeriod, TDFor switch clock ClkDPeriod, M is coefficient.
2. a kind of two-part for probability calculation according to claim 1 concentrates sequence generator, which is characterized in that control
Logic circuit (3) processed, for keeping clock Clk in samplingSUnder the action of resetted, after the completion of reset, in switch clock ClkD
Under the action of, comparison result based on the receivedDetermine the switch clock Clk of outputAState and based on the received
Comparison resultDetermine the switch clock Clk of outputBState detailed process are as follows:
Control logic circuit (3) keeps clock Clk in samplingSUnder the action of resetted, after the completion of reset, high-order section sequence is raw
It starts to work at circuit (4)；
During the work of high-order section sequence generation circuitry (4), control logic circuit (3) is in switch clock ClkDRising edge time,
MonitoringLogic level, when monitoring two adjacent momentLogic level, be first " 1 ", be afterwards
When " 0 ", the switch clock Clk that outputs itAState set 0, and make switch clock ClkBState with switch clock ClkDIt protects
It holds unanimously, at this point, high-order section sequence generation circuitry (4) stops working, low level section sequence generation circuitry (5) is started to work；
During low level section sequence generation circuitry (5) work, control logic circuit (3) is in switch clock ClkDRising edge time,
Continuous monitoringLogic level, when monitoring two adjacent momentLogic level, be first " 1 ",
When being afterwards " 0 ", the switch clock Clk that outputs itBLogic level set 0, at this point, low level section sequence generation circuitry (5) stop
Work, sequence convert.
3. a kind of two-part for probability calculation according to claim 1 concentrates sequence generator, which is characterized in that high
Position section sequence generation circuitry (4) includes comparator U1, bidirectional shift register, N number of constant-current source, N number of logic switch, operation amplifier
Device OP1, sampling resistor RAWith the first low-pass filter；
Positive input terminal of the positive input terminal of comparator U1 as high-order section sequence generation circuitry (4)；
Negative input end of the negative input end of comparator U1 as high-order section sequence generation circuitry (4)；
Comparator U1 is by received voltage VSWith voltage VAAfter comparing, by the comparison result of acquisitionIt is sent into two-way shifting simultaneously
Bit register and control logic circuit (3), bidirectional shift register is in switch clock ClkAUnder the action of, according to comparison resultLogic level determine the direction of displacement of output sequence after, the high-order section N concentrations sequence after output displacement
After N number of constant-current source is connected with N number of logic switch respectively, it is connected in parallel on power supply VDDWith the inverting input terminal of operational amplifier OP1
Between；
N number of digital signalExtremelyIt is respectively used to control the control terminal of N number of logic switch；
The inverting input terminal and sampling resistor R of operational amplifier OP1AOne end connection, the same opposite input of operational amplifier OP1
Termination power, the output end and sampling resistor R of operational amplifier OP1AThe other end and the first low-pass filter input terminal
Connection, voltage output end of the voltage output end of the first low-pass filter as high-order section sequence generation circuitry (4)；
Bidirectional shift register receives switch clock ClkASwitch clock letter of the port as high-order section sequence generation circuitry (4)
Number input terminal；
The high-order section N concentrations sequence of bidirectional shift register outputOutput end it is raw as high-order section sequence
At the sequence output end of circuit (4).
4. a kind of two-part for probability calculation according to claim 3 concentrates sequence generator, which is characterized in that high
Bidirectional shift register in position section sequence generation circuitry (4) is in switch clock ClkAUnder the action of, according to comparison resultLogic level determine output sequence direction of displacement detailed process are as follows:
Bidirectional shift register is in switch clock ClkAUnder the action of, work as comparison resultLogic level be ' 1 ' when,
Numerical value in control bidirectional shift register output sequence lowest order moves to right, and mends ' 1 ' in lowest order, works as comparison resultLogic level when being ' 0 ', the numerical value controlled in bidirectional shift register output sequence highest order moves to left, and most
A high position mends ' 0 '.
5. a kind of two-part for probability calculation according to claim 1 concentrates sequence generator, which is characterized in that low
Position section sequence generation circuitry (5) includes comparator U2, bidirectional shift register, N number of constant-current source, N number of logic switch, operation amplifier
Device OP2, sampling resistor RBWith the second low-pass filter；
Positive input terminal of the positive input terminal of comparator U2 as low level section sequence generation circuitry (5)；
Negative input end of the negative input end of comparator U2 as low level section sequence generation circuitry (5)；
Comparator U2 is by received voltage VSAfter subtracting voltage V ' A, by the comparison result of acquisitionIt is sent into two-way shifting simultaneously
Bit register and control logic circuit (3), bidirectional shift register is in switch clock ClkBUnder the action of, according to comparison resultLogic level determine the direction of displacement of output sequence after, N concentration sequences of low level section after output displacement
After N number of constant-current source is connected with N number of logic switch respectively, it is connected in parallel on power supply VDDWith the inverting input terminal of operational amplifier OP2
Between；
N number of digital signalExtremelyIt is respectively used to control the control terminal of N number of logic switch；
The inverting input terminal and sampling resistor R of operational amplifier OP2BOne end connection, the same opposite input of operational amplifier OP2
Termination power, the output end and sampling resistor R of operational amplifier OP2BThe other end and the second low-pass filter input terminal
Connection, voltage output end of the voltage output end of the second low-pass filter as low level section sequence generation circuitry (5)；
Bidirectional shift register receives switch clock ClkBPort as low level section sequence generation circuitry (5) switch clock believe
Number input terminal；
N concentration sequences of low level section of bidirectional shift register outputOutput end it is raw as low level section sequence
At the sequence output end of circuit (5).
6. a kind of two-part for probability calculation according to claim 5 concentrates sequence generator, which is characterized in that low
Bidirectional shift register in position section sequence generation circuitry (5) is in switch clock ClkBUnder the action of, according to comparison resultLogic level determine output sequence direction of displacement detailed process are as follows:
Bidirectional shift register is in switch clock ClkBUnder the action of, work as comparison resultLogic level be ' 1 ' when,
Numerical value in control bidirectional shift register output sequence lowest order moves to right, and mends ' 1 ' in lowest order, works as comparison resultLogic level when being ' 0 ', the numerical value controlled in bidirectional shift register output sequence highest order moves to left, and most
A high position mends ' 0 '.
7. a kind of two-part for probability calculation according to claim 1 concentrates sequence generator, which is characterized in that control
Logic circuit (3) processed includes d type flip flopWith door AndA1, NAND gate AndA2And door AndB1, with it is non-
Door AndB2, NOT gate YA1, NOT gate YA2With NOT gate YB1；
With door AndA1First input end and with door AndB1First input end be used as the switch clocks of control logic circuit (3)
ClkDReceiving end；
With door AndA1The second input terminal simultaneously with NAND gate AndA2Output end and NOT gate YA2Input terminal connection；
With door AndA1Output end for exporting switch clock ClkA, and simultaneously and d type flip flopClock signal input terminal, D
TriggerClock signal input terminal connection；
D type flip flopData input pin, for receiving the comparison result of high-order section sequence generation circuitry (4) outputD type flip flopReset signal input terminal for receive sampling keep clock ClkS, and d type flip flopAnswer
Position signal input part while and d type flip flopReset signal input terminal, d type flip flopReset signal input terminal and D touching
Send out deviceReset signal input terminal connection；
D type flip flopOutput end simultaneously NAND gate YA1Input terminal and d type flip flopData input pin connection, D triggering
DeviceOutput end and NAND gate AndA2First input end connection, NOT gate YA1Output end and NAND gate AndA2It is second defeated
Enter end connection；
With door AndB1The second input terminal NAND gate YA2Output end connection, with door AndB1Third input terminal and NAND gate
AndB2Output end connection,
With door AndB1Output end for exporting switch clock ClkB, and simultaneously and d type flip flopClock signal input terminal, D
TriggerClock signal input terminal connection；
D type flip flopData input pin, for receive low level section sequence generation circuitry (5) output comparison result
D type flip flopOutput end simultaneously NAND gate YB1Input terminal and d type flip flopData input pin connection, D triggering
DeviceOutput end and NAND gate AndB2First input end connection, NOT gate YB1Output end and NAND gate AndB2It is second defeated
Enter end connection.
8. a kind of two-part for probability calculation according to claim 7 concentrates sequence generator, which is characterized in that In
With door AndA1The second input terminal and NAND gate AndA2Output end between be in series with even number NOT gate, for door AndA1
Output end output switch clock ClkAIt is delayed, delay time is less than TD。
9. a kind of two-part for probability calculation according to claim 7 concentrates sequence generator, which is characterized in that with
Door AndB1Third input terminal and NAND gate AndB2Output end between be in series with even number NOT gate, for door AndB1's
The switch clock Clk of output end outputBIt is delayed, delay time is less than TD。
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