CN108287682A - A kind of pseudo random sequence generation method and device and integrated circuit - Google Patents
A kind of pseudo random sequence generation method and device and integrated circuit Download PDFInfo
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- CN108287682A CN108287682A CN201810123943.1A CN201810123943A CN108287682A CN 108287682 A CN108287682 A CN 108287682A CN 201810123943 A CN201810123943 A CN 201810123943A CN 108287682 A CN108287682 A CN 108287682A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
- G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
Abstract
The length of a kind of pseudo random sequence generation method and device and integrated circuit, the pseudo-random sequence is N-bit, and N is the positive integer more than 1, and the pseudo-random sequence is divided into multiple segmentations, and the pseudo random sequence generation method includes：Constructor, the function embody 2NThe relationship between total segmentation number for overturning number and pseudo-random sequence and the length being each segmented in a pseudo-random sequence between each adjacent pseudo-random sequence；The length of segmentation number and each segmentation is calculated according to the function；Length based on calculated segmentation number and each segmentation generates multiple clock signals, and each clock signal corresponds to a segmentation；It is utilized respectively multiple segmentations that the multiple clock signal generates pseudo-random sequence.Pseudo-random sequence is generated by way of segmentation, can be reduced and be overturn number between flanking sequence.
Description
Technical field
This disclosure relates to digital signal processing technique field, and in particular to a kind of pseudo random sequence generation method and device with
And integrated circuit.
Background technology
With the continuous diminution of semiconductor processing dimensions, circuit failure that may be present is more and more, it is therefore desirable to huge
Test vector.But the load of test vector when due to test, the switch activity of each node of circuit are higher than normal mode of operation,
It can cause larger dynamic power consumption, generation is seriously affected the reliability of circuit by this.Currently, common test vector generation side
Method includes cumulative and pseudo-random generation method etc..For summation, its advantage is that algorithm is simple.But this method circuit resource consumes
It is more that number is overturn between larger and flanking sequence, it is assumed for example that produce one group of 8 bit cycle tests using summation, then it altogether can
To generate 2 from 00000000 to 111111118A cycle tests, then being for the cycle tests being currently generated
00111111, and in the case that the cycle tests of next generation is 01000000, two neighboring cycle tests occurs 7 times and turns over altogether
Turn.For pseudo-random generation method, its advantage is that algorithm is relatively easy and is consumed less to circuit resource, as long as and having enough
Long test vector just disclosure satisfy that test request.But this method will also result in that test vector is tediously long and sequence overturning number compared with
It is more, cause larger dynamic power consumption.
For this reason, it may be necessary to be generated for pseudo-random sequence, overturning number is excessive between solving the problems, such as flanking sequence.
Invention content
In view of this, present disclose provides a kind of pseudo random sequence generation method and device and integrated circuit, Neng Gouyou
Effect overturns number between reducing flanking sequence.
According to the disclosure in a first aspect, provide a kind of pseudo random sequence generation method, the length of the pseudo-random sequence
Degree is N-bit, and N is the positive integer more than 1, which is characterized in that the pseudo-random sequence is divided into multiple segmentations, the pseudorandom
Sequence generating method includes：Constructor, the function embody 2NEach adjacent pseudorandom sequence in a pseudo-random sequence
The relationship between total segmentation number for overturning number and pseudo-random sequence and the length being each segmented between row；According to described
Function is segmented the length of number and each segmentation to calculate；Length based on calculated segmentation number and each segmentation generates
Multiple clock signals, each clock signal correspond to a segmentation；It is utilized respectively the multiple clock signal and generates pseudo-random sequence
Multiple segmentations.
Preferably, the function includes：Wherein,1
≤ i≤n, 2≤n ＜ N, S indicate total overturning number of the pseudo-random sequence, SiIndicate that the overturning number of segmentation i, n indicate institute
State the segmentation number of pseudo-random sequence, L1,L2,…,LnThe length for indicating the n segmentation respectively, meetsI is indicated
Number-of-fragments.
Preferably, described to include come the length for calculating segmentation number and each segmentation according to the function：According to described
Function calculating makes the n values of S values minimum and corresponding L1,L2,…,LnValue.
Preferably, L(i-1)＜ Li, described also to be wrapped according to the function to calculate the length of segmentation number and each segmentation
It includes：The value range of n is determined based on N values；In the value range, according to the function calculating make the n values of S values minimum with
And corresponding L1,L2,…,LnValue.
Preferably, the pseudo random sequence generation method further includes：Combined circuit design complexities are calculated to adjust
It is segmented number n, and recalculates the corresponding L for making S values minimum according to the function based on the segmentation number n after adjustment1,
L2,…,LnValue.
Preferably, the multiple clock signals of length generation based on calculated segmentation number and each segmentation include：
Generate n clock signal clk1,CLK2,…,CLKn, the n clock signal clk1,CLK2,…,CLKnClock cycle T1,
T2,…,TnBetween relationship meetWherein j indicates the number of clock signal.
Preferably, it is described be utilized respectively the multiple clock signal and generate multiple segmentations of pseudo-random sequence include：For
Each segmentation i, according to length LiTo determine the corresponding L of segmentation iiThe primitive polynomial of position linear feedback shift register；According to
The coefficient of the primitive polynomial is arranged the LiThe feedback tap connection of position linear feedback shift register, so that the Li
Position linear feedback shift register generates the segmentation i.
Preferably, it is described be utilized respectively the multiple clock signal and generate multiple segmentations of pseudo-random sequence include：For
Each segmentation i, according to the length L of segmentation iiTo determine corresponding LiThe primitive polynomial of position linear feedback shift register, and
It is inverted to the primitive polynomial to obtain reversed multinomial；It is set in the flrst mode according to the coefficient of the primitive polynomial
Set the LiThe feedback tap of position linear feedback shift register connects so that the LiPosition linear feedback shift register is defeated
Go out positive segmentation i, the L is arranged according to the reversed polynomial coefficient under the second modeiPosition linear feedback shift
The feedback tap of register connects so that the LiPosition linear feedback shift register exports reversed segmentation i.
According to another aspect of the present disclosure, a kind of pseudo-random sequence generating means, the length of the pseudo-random sequence are provided
Degree is N-bit, and N is the positive integer more than 1, which is characterized in that the pseudo-random sequence is divided into multiple segmentations, the pseudorandom
Sequence generator includes：Multiple linear feedback shift registers, each linear feedback shift register are used for when corresponding
One of the multiple segmentation is generated under the control of clock signal；And clock signal generating circuit, for for the multiple linear
Each in shift register generates clock signal respectively, wherein the number of segmentation and the length of each segmentation are bases
Function setup, the function embodies the function and embodies 2NEach adjacent pseudo-random sequence in a pseudo-random sequence
Between total overturning number and the segmentation number and the length that is each segmented of pseudo-random sequence between relationship；And for every
The clock signal of a linear feedback shift register is that the length based on segmentation number and each segmentation generates.
Preferably, the function includes：Wherein,1
≤ i≤n, 2≤n ＜ N, S indicate total overturning number, SiIndicate that the overturning number of segmentation i, n indicate the pseudo-random sequence
Segmentation number, L1,L2,…,LnThe length for indicating the n segmentation respectively, meetsI indicates number-of-fragments.
Preferably, clock signal generating circuit is used to generate n clock signal for corresponding respectively to n segmentation by dividing
CLK1,CLK2,…,CLKn, the n clock signal clk1,CLK2,…,CLKnClock cycle T1,T2,…,TnBetween pass
System meetsWherein j indicates the number of clock signal.
Preferably, each linear feedback shift register includes：Multiple triggers, the multiple trigger series connection, are used for
Each bit of corresponding segment is generated under the control of corresponding clock signal；Feedback circuit is connected with the multiple trigger
To form linear feedback structure, wherein the output end of one or more triggers specified in the multiple trigger is as anti-
Feedback tap is connected to the input terminal of the linear feedback shift register via the feedback circuit.
Preferably, the feedback circuit includes：Logic gates is connected together to linear feedback with the multiple trigger
Structure, wherein the output end of one or more triggers specified in the multiple trigger as feedback tap via described
Logic gates is connected to the input terminal of the linear feedback shift register；And selection circuit, it is connected to logic gates
Between the multiple trigger, for more according to the basis of linear feedback shift register when receiving first control signal
The feedback tap of linear feedback shift register is connected to the logic gates by the coefficient of item formula according to first mode, is being connect
According to the reversed polynomial coefficient of linear feedback shift register by the linear feedback shift when receiving second control signal
The feedback tap of register is connected to the logic gates according to second mode, and the reversed multinomial is by described
What former multinomial was inverted.
According to another aspect of the present disclosure, a kind of integrated circuit, including above-mentioned pseudo-random sequence generating means are provided.
Description of the drawings
In order to illustrate more clearly of the technical solution of the embodiment of the present disclosure, simple be situated between will be made to the attached drawing of embodiment below
It continues, it should be apparent that, the attached drawing in description below only relates to some embodiments of the present disclosure, rather than the limitation to the disclosure.
Fig. 1 shows the schematic flow diagram of the pseudo random sequence generation method according to the embodiment of the present disclosure.
Fig. 2 shows the schematic diagrames according to the multiple segmentations of the pseudo-random sequence of the embodiment of the present disclosure.
Fig. 3 shows the sequence diagram for being divided to clock signal in the case of two sections according to the embodiment of the present disclosure.
Fig. 4 shows the example block diagram of the pseudo-random sequence generating means according to the embodiment of the present disclosure.
Fig. 5 shows the pseudo random sequence generation method of the embodiment of the present disclosure and the overturning number of device and the prior art pair
Than figure.
Specific implementation mode
To keep the purpose, technical scheme and advantage of the embodiment of the present disclosure clearer, below in conjunction with the embodiment of the present disclosure
Attached drawing, clear, complete description is carried out to the technical solution of the embodiment of the present disclosure.Obvious described embodiment is the disclosure
A part of the embodiment, instead of all the embodiments.Based on described embodiment of the disclosure, ordinary skill people
The every other embodiment that member is obtained under the premise of without creative work belongs to the range of disclosure protection.
Present disclose provides a kind of pseudo random sequence generation method and devices, by the way that pseudo-random sequence to be segmented, and build
The length that the segmentation number of the total overturning number and pseudo-random sequence between adjacent pseudo-random sequence can be embodied and be each segmented
The function of relationship between degree can calculate the segmented mode that total overturning number of sening as an envoy to minimizes, so as to effectively reduce phase
Number is overturn between adjacent sequence.
Fig. 1 shows the schematic flow diagram of the pseudo random sequence generation method according to the embodiment of the present disclosure.
In step S101, the pseudo-random sequence that will be generated is divided into multiple segmentations.For example, it is assumed that generate length is N
The pseudo-random sequence of bit, N is the integer more than 1, then pseudo-random sequence can be divided into n segmentation, 2≤n in this step
＜ N, the length of the n segmentation distinguish L1,L2,…,Ln, as shown in Figure 2.It is segmented number n and each section length at this stage
L1,L2,…,LnValue be unknown.
In step S102, constructor, the function embodies 2NEach adjacent pseudorandom in a pseudo-random sequence
The relationship between total segmentation number for overturning number and pseudo-random sequence and the length being each segmented between sequence.Such as it can
To build with minor function：
Wherein,1≤i≤n, 2≤n ＜ N, S indicate total overturning number, SiIndicate the overturning of segmentation i
Number, n indicate the segmentation number of the pseudo-random sequence, L1,L2,…,LnThe length for indicating the n segmentation respectively, meetsI indicates number-of-fragments.
The structure principle of above-mentioned function is described below in detail.In the present embodiment, design is produced in the form of multiple segmentations
Raw pseudo-random sequence, each segmentation will be produced using the clock signal of different frequency so that often generating a high-order segmentation
Raw certain number of multiple low level segmentations.For example, if to generate N-bit pseudo-random sequence, it is contemplated that by the puppet with
Machine sequence is divided into n segmentation to generate, and each section length is respectively L1,L2,…,Ln.Each segmentation uses a clock signal
It generates, then n segmentation needs n clock signal clk1,CLK2,…,CLKn, the n clock signal clk1,CLK2,…,
CLKnClock cycle T1,T2,…,TnBetween relationship meetWherein j indicates the number of clock signal.
In this case, it is L for length1Segmentation, always overturn number S between flanking sequence1Meet
It is i.e. everyA length is L1Number is always overturn between the flanking sequence of sequence isDue to clock signal clk1And CLK2
Clock cycle meetSo that it is L often to generate a length1High-order segmentation just will produceA length is L2
Low level segmentation, a high position segmentation symbiosis atIt is a, it means that the segmentation of corresponding low level is overturnIt is secondary.It is similar
Ground, due toIt is L often to generate a length2Segmentation just will produceA length is L3Segmentation, length L2
Segmentation symbiosis atIt is a, it means that corresponding length is L3Segmentation overturnIt is secondary.This analogizes
To sum to get to above-mentioned equation (1) to the overturning numbers of all segmentations.
In step S103, the value range of n is determined based on N values.For example, it can be set to the length L of n segmentation1,L2,…,
LnIt is satisfied by L(i-1)＜ Li, since the length of each segmentation is at least 1 bit, then for example for N=20 bits the case where come
It says, 20 bits of+5 bit ＜ of 1 bit+2 bit+4 bit of+3 bit or+6 bit of+5 bit of 2 bit+4 bit of+3 bit=
20 bits, it is possible thereby to which the maximum occurrences for being inferred to n are 5, i.e. the value range of n is between 2 to 5.This certain step is optional
, it can also determine n values range using other modes in some embodiments or directly be determined using above-mentioned function (1)
N values.
In step S104, in the value range of n, the n values of S values minimum and corresponding L are made according to above-mentioned function1,
L2,…LnValue.Theoretically the bigger S values of n values are smaller, however embodiment of the disclosure is without being limited thereto, and the value of n can consider it
He is because usually adjusting.Such as the more conference of the value of n causes complex circuit designs degree higher in some cases, can be set with combined circuit
Count complexity and overturn number reduce degree the two because usually selection n values.In some embodiments, for N≤20
Situation, selection are divided to two sections, i.e. n=2.Such as the case where for N=15, can select n=2, this is not according to for above-mentioned formula
Make the value of Y value minimum, but considers design complexities while reducing Y value and the result weighed.
Below how L is calculated in the case of N=15 n=2 to specifically describe1And L2。
It is S=N × 2 that the pseudo-random sequence of N-bit, which overturns number in the case where not being segmented,N-1, it is L being divided into length1With
L2Two sections come when generating, this two sections overturn number within the respective clock cycle and are respectivelyWithAccording to above-mentioned equation (1), it can be deduced that as n=2, the flanking sequence of entire pseudo-random sequence overturns number
Summation is：
By that can show that S has minimum value when meeting following equation (3) to above-mentioned equation (2) derivation：
Since N is known, it is hereby achieved that L1Value, and then obtain L2Value.In the present embodiment, N=15, by
When above-mentioned equation (3) can calculate L1=12, and then calculate L2=3.So far, the value of division number n and each has been calculated
A section length L1And L2Value.
In step S105, the length L based on calculated segmentation number n and each segmentation1,L2,…LnGenerate multiple clocks
Signal, each clock signal correspond to a segmentation.For example, having calculated that segmentation number n and each section length L1,L2,…Ln's
In the case of, can by divide generate meet it is above-mentionedN clock signal clk1,CLK2,…,CLKn,
It can be generated by carrying out repeatedly frequency dividing based on clock signal of system in some embodiments.
Fig. 3 is shown in above-mentioned N=15, n=2, L1=12, L2The clock signal clk obtained in the case of=31And CLK2
Sequence diagram.As shown in figure 3, clock signal clk1And CLK2Clock cycle meetThat is T1=8T2, in clock
Signal CLK1A clock cycle in can generate length be L1The segmentation of (12 bit), in clock signal clk2One when
It is L that length can be generated in the clock period2The segmentation of (3 bit), and due to clock signal clk1Clock cycle be CLK2Clock
8 times of period, as soon as so often generating the high-order segmentation that length is 12 bits, the low level that will produce 83 bits is segmented.
In step S106, it is utilized respectively multiple segmentations that the multiple clock signal generates pseudo-random sequence.Such as it can be with
For each segmentation i, according to length LiTo determine the corresponding L of segmentation iiThe primitive polynomial of position linear feedback shift register,
And the L is set according to the coefficient of the primitive polynomialiThe feedback tap connection of position linear feedback shift register, so that
The LiPosition linear feedback shift register generates the segmentation i.In some embodiments, the pseudo-random sequence of generation not only may be used
For use as cycle tests, it is also used as test address.Positive and negative two reversed sequences can be preferably set and generate pattern.Example
It such as, can be according to the length L of segmentation iiTo determine corresponding LiThe primitive polynomial of position linear feedback shift register, and to institute
It states primitive polynomial to invert to obtain reversed multinomial, in the flrst mode according to the coefficient of the primitive polynomial to be arranged
State LiThe feedback tap of position linear feedback shift register connects so that the LiPosition linear feedback shift register output is just
To segmentation i, the L is arranged according to the reversed polynomial coefficient under the second modeiPosition linear feedback shift register
The feedback tap of device connects so that the LiPosition linear feedback shift register exports reversed segmentation i.
Fig. 4 shows the structural schematic diagram of the pseudo-random sequence generating means according to the embodiment of the present disclosure.In the present embodiment
In, each pseudo-random sequence is divided into n segmentation to generate by pseudo-random sequence generating means, is segmented number n and each point
The length L of section1And L2Can be calculated by way of described in above method embodiment.It is same in the present embodiment
Sample is with above-mentioned N=15, n=2, L1=12, L2It is described in case of=3, i.e., each pseudo-random sequence is to be divided to two sections of productions
Raw, high-order section length is 12 bits, and the section length of low level is 3 bits.
As shown in figure 4, pseudo-random sequence generating means include 12 linear feedback shift registers 10 and one 3
Linear feedback shift register 20 and clock signal generating circuit 30.Linear feedback shift register 10 is used in clock signal
CLK1Control under generate pseudo-random sequence it is 12 high, linear feedback shift register 20 be used in clock signal clk2Control
Lower generate pseudo-random sequence low 3 of system.
Clock signal generating circuit 30 is for generating clock signal clk as shown in Figure 31And CLK2, the two clock cycle is full
FootThat is T1=8T2, this can be that mode described in above method embodiment is calculated.As showing
Example, clock signal generating circuit 30 may include 1/8 frequency divider (being indicated by DIV (1/8) in figure), clock signal clk2It can
To use system clock, and CLK1It can be obtained by carrying out 1/8th frequency dividings to system clock.
With continued reference to Fig. 4, linear feedback shift register 10 includes 12 triggers FF1, FF2 ..., FF12 and feedback
Circuit, trigger FF1, FF2 ..., FF12 are one another in series, and feedback circuit and trigger FF1, FF2 ..., FF12 are connected together to
The input end of clock of linear feedback structure, trigger FF1, FF2 ..., FF12 receives clock signal clk1, output end carries respectively
For the 12 high of pseudo-random sequence.In the present embodiment, feedback circuit includes logic gates and selection circuit, logic gates
Including multiple logic gate G1, G2, G3, G4 and G5, selection circuit includes multiple selector E.As shown in figure 3, logic gate G1, G2,
G3, G4 and G5 and trigger FF1, FF2 ..., FF12 are connected to form linear feedback structure, wherein logic gate G1, G2, G3, G4 and
Type, number and the connection type of G5 can carry out selection as needed, such as G1 and G5 is XOR gate in the present embodiment,
G2 is nor gate, and G3 and G4 are or door, certain those skilled in the art should understand that embodiment of the disclosure is without being limited thereto.Selection electricity
Road is included in each trigger FF1, FF2 ..., the multiple selectors connected between FF12 and logic gate G1, G2, G3, G4 and G5
E, selector E is alternative type selector in the present embodiment, and there are two input terminal (being indicated respectively by 0 and 1), an outputs for tool
End and a control terminal, control terminal receive control signal updn, selector E and select two according to the control of control signal updn
The signal of one of input terminal is exported in output end.
Continue with the feedback tap connection type for being described with reference to Figure 4 linear feedback shift register 10.For N
For linear feedback shift register, primitive polynomial is represented by：
H (X, N)=M0X0+M1X1+…+MN-1XN-1 (4)
According to the coefficient M of formula equation (4)0、M1、…、MN-1Two input XOR gate feedback of connection can obtain 2N- 1 puppet with
Machine sequence, in output end parallel output.Peer-to-peer (4), which is inverted, can be obtained equation (5)：
G (X, N)=M0XN-1+M1XN-2X1+…+MN-1X0 (5)
The variation sequence of H (X, N) and G (X, N) sequence is just opposite.
Linear feedback shift register 10 is 12 linear feedback shift registers in Fig. 4, and primitive polynomial is：
H (X, 12)=X0+X3+X4+X7+X12 (6)
Peer-to-peer (6), which is inverted, can obtain following reversed multinomial：
G (X, 12)=X12+X9+X8+X5+X0 (7)
The feedback tap of linear feedback shift register 10 can be connected according to the coefficient of equation (6), to export forward direction
Sequence connects the feedback tap of linear feedback shift register 10, to export reverse sequence according to the coefficient of equation (7).And
Specifically positive output or reversed output, can be realized by selector E.In the present embodiment, trigger FF3, FF4,
The output end (being indicated by Q in figure) of FF7 and FF12 is as feedback tap via the first input end of selector E (by 0 table in figure
Show) it is connected to XOR gate G5, correspond to the coefficient of equation (6)；The output end of trigger FF1, FF4, FF5 and FF8 are (by Q in figure
Indicate) it is connected to XOR gate G5 via the second input terminal (being indicated by 1 in figure) of selector E as feedback tap, correspond to etc.
The coefficient of formula (7).When it is 0 to control signal updn, first input end (0 indicates) gating of selector E so that linear feedback is moved
The feedback tap of bit register 10 connects in the way of positive output sequence, when it is 1 to control signal updn, selector E's
Second input terminal (indicates) gating by 1 so that the feedback tap of linear feedback shift register 10 is according to reversed output sequence
Mode connects.The flexible control and switching of positive reinfusion may be implemented in this way.
Linear feedback shift register 20 has similar structure and connection type comprising concatenated three triggers
FF13, FF14 and FF15 and feedback circuit, the feedback circuit include logic gates and selection circuit, logic gates packet
Logic gate G6, G7 and G8 are included, forms linear feedback structure with three triggers FF13, FF14 and FF15, selection circuit includes
The multiple selector C being connected between logic gate logic gate G6, G7 and G8 and trigger FF13, FF14 and FF15.Such as Fig. 3 institutes
Show, be similar to it is above-mentioned, using multiple selector E realize 3 linear feedback shift registers 20 feedback tap it is positive and negative two-way
The switching and control of connection, details are not described herein.
Above-mentioned pseudo-random sequence generating means can be arranged in integrated circuits, to be applied to a variety of different devices
Part, device or equipment realize the function that pseudo-random sequence generates.
Although above-described embodiment is described by taking n=2 as an example, embodiment of the disclosure is without being limited thereto, the value of n
It can calculate and select in any way as needed.According to the difference of segmentation number and each section length, correspondingly it is pseudo- with
The structure and connection relation of machine sequence generator also can be as described above mode be varied from.For example, excellent when calculating
Select segments be n=3 when, substitute into equation (1) by derive can obtain：
Can calculate makes the L of S values minimum1、L2And L3Value as three respective length of segmentation.According to calculated point
Segment length connects to design the number, bit wide, feedback tap of clock signal and linear feedback shift register, the puppet designed
Random sequence generating means can generate pseudo-random sequence according to above-mentioned segmented mode.Here minimum calculation method is not limited to
The mode of differential is stated, but mathematically any feasible mode may be used and obtain each section length for making S values minimum to calculate
Value, such as finding limit method etc., details are not described herein.
Following table 1 shows the corresponding preferably segmented length sum in the case where pseudo-random sequence is divided into two segmentations
Number is overturn, wherein H indicates that the length of high-order segmentation, L indicate the length of low level segmentation, and bit wide refers to the position of pseudo-random sequence
Width, unit are kb.If the pseudo-random sequence generated is used as cycle tests, bit wide refers to the bit wide of cycle tests, if
The pseudo-random sequence of generation is used as test address, then bit wide refers to address bit wide, i.e. address depth.
Table 1
Fig. 5 shows the pseudo random sequence generation method of the embodiment of the present disclosure and the overturning number of device and the prior art pair
Than figure, wherein dotted line shows that the flanking sequence of conventional method generation pseudo-random sequence always overturns number, and realization shows basis
The flanking sequence that the method for the embodiment of the present disclosure generates pseudo-random sequence always overturns number, and abscissa indicates the pseudorandom sequence generated
The bit wide of row, with kb (kilobytes) for unit, ordinate indicates that flanking sequence overturns total degree.
From fig. 5, it can be seen that being generated according to the pseudo-random series producing method of the embodiment of the present disclosure and device by being segmented
Pseudo-random sequence, according between total segmentation number for overturning number and pseudo-random sequence of structure and the length being each segmented
The function of relationship is reasonably segmented number and section length to calculate, and can significantly reduce the overturning number of flanking sequence, to
System power dissipation is reduced, the advantages that area is at low cost, processing speed is fast is provided simultaneously with.
Embodiment of the disclosure weighs segmentation number by other factors such as combined circuit design complexities, can drop
Simplify circuit design while low sequence overturning number, realization method is flexible.
Embodiment of the disclosure in pseudo-random sequence generating means by utilizing logic gates and selection circuit to realize
The sequence generating mode of positive and negative twocouese, the scope of application is wider, using flexible.
The foregoing is merely preferred embodiment of the present disclosure, are not limited to the disclosure, for those skilled in the art
For, the disclosure can have various modifications and changes.It is all within the spirit and principle of the disclosure made by any modification, equivalent
Replace, improve etc., it should be included within the protection domain of the disclosure.
Claims (14)
1. the length of a kind of pseudo random sequence generation method, the pseudo-random sequence is N-bit, N is the positive integer more than 1,
It is characterized in that, the pseudo-random sequence is divided into multiple segmentations, and the pseudo random sequence generation method includes：
Constructor, the function embody 2NTotal overturning in a pseudo-random sequence between each adjacent pseudo-random sequence
Relationship between the segmentation number of number and pseudo-random sequence and the length being each segmented；
The length of segmentation number and each segmentation is calculated according to the function；
Length based on calculated segmentation number and each segmentation generates multiple clock signals, and each clock signal corresponds to one
Segmentation；
It is utilized respectively multiple segmentations that the multiple clock signal generates pseudo-random sequence.
2. pseudo random sequence generation method according to claim 1, which is characterized in that the function includes：
Wherein,1≤i≤n, 2≤n ＜ N, S indicate total overturning number of the pseudo-random sequence, SiIt indicates to divide
The overturning number of section i, n indicate the segmentation number of the pseudo-random sequence, L1,L2,…,LnThe length of the n segmentation is indicated respectively
Degree meetsI indicates number-of-fragments.
3. pseudo random sequence generation method according to claim 2, which is characterized in that described to be calculated according to the function
Segmentation number and the length of each segmentation include：Make the n values of S values minimum and corresponding L according to function calculating1,
L2,…,LnValue.
4. pseudo random sequence generation method according to claim 3, which is characterized in that L(i-1)＜ Li, described in the basis
Function further includes to calculate segmentation number and the length of each segmentation：
The value range of n is determined based on N values；
In the value range, the n values of S values minimum and corresponding L are made according to function calculating1,L2,…,LnValue.
5. pseudo random sequence generation method according to claim 3, which is characterized in that further include that combined circuit design is complicated
Degree adjusts calculated segmentation number n, and is recalculated according to the function based on the segmentation number n after adjustment and make S values most
Small corresponding L1,L2,…,LnValue.
6. pseudo random sequence generation method according to claim 2, which is characterized in that described based on calculated segmentation
Number and the length of each segmentation generate multiple clock signals：Generate n clock signal clk1,CLK2,…,CLKn, the n
A clock signal clk1,CLK2,…,CLKnClock cycle T1,T2,…,TnBetween relationship meetWherein j
Indicate the number of clock signal.
7. pseudo random sequence generation method according to claim 6, which is characterized in that described when being utilized respectively the multiple
Clock signal generate pseudo-random sequence multiple segmentations include：For each segmentation i,
According to length LiTo determine the corresponding L of segmentation iiThe primitive polynomial of position linear feedback shift register；
The L is set according to the coefficient of the primitive polynomialiThe feedback tap connection of position linear feedback shift register, with
Make the LiPosition linear feedback shift register generates the segmentation i.
8. pseudo random sequence generation method according to claim 6, which is characterized in that described when being utilized respectively the multiple
Clock signal generate pseudo-random sequence multiple segmentations include：For each segmentation i,
According to the length L of segmentation iiTo determine corresponding LiThe primitive polynomial of position linear feedback shift register, and to described
Primitive polynomial is inverted to obtain reversed multinomial；
The L is set according to the coefficient of the primitive polynomial in the flrst modeiThe feedback of position linear feedback shift register
Tap connects so that the LiThe positive segmentation i of position linear feedback shift register output, under the second mode according to institute
Reversed polynomial coefficient is stated the L is arrangediThe feedback tap of position linear feedback shift register connects so that the LiBit line
Property feedback shift register exports reversed segmentation i.
9. the length of a kind of pseudo-random sequence generating means, the pseudo-random sequence is N-bit, N is the positive integer more than 1,
It is characterized in that, the pseudo-random sequence is divided into multiple segmentations, and the pseudo-random sequence generating means include：
Multiple linear feedback shift registers, each linear feedback shift register are used under the control of corresponding clock signal
Generate one of the multiple segmentation；And
Clock signal generating circuit, for generating clock letter respectively for each in the multiple linear shift register
Number,
Wherein,
The number of segmentation and the length of each segmentation are according to function setup, and the function embodies the function and embodies
2NThe segmentation number of total overturning number and pseudo-random sequence in a pseudo-random sequence between each adjacent pseudo-random sequence
And the relationship between the length being each segmented；And
Clock signal for each linear feedback shift register is that the length based on segmentation number and each segmentation generates.
10. pseudo-random sequence generating means according to claim 9, which is characterized in that the function includes：
Wherein,1≤i≤n, 2≤n ＜ N, S indicate total overturning number, SiIndicate the overturning time of segmentation i
Number, n indicate the segmentation number of the pseudo-random sequence, L1,L2,…,LnThe length for indicating the n segmentation respectively, meetsI indicates number-of-fragments.
11. pseudo-random sequence generating means according to claim 10, which is characterized in that clock signal generating circuit is used for
N clock signal clk for corresponding respectively to n segmentation is generated by dividing1,CLK2,…,CLKn, the n clock signal
CLK1,CLK2,…,CLKnClock cycle T1,T2,…,TnBetween relationship meetWherein j indicates clock letter
Number number.
12. pseudo-random sequence generating means according to claim 9, which is characterized in that each linear feedback shift register
Device includes：
Multiple triggers, the multiple trigger series connection, for generating corresponding segment under the control of corresponding clock signal
Each bit；
Feedback circuit is connected together to linear feedback structure with the multiple trigger, wherein the multiple trigger works as middle finger
The output end of fixed one or more triggers is connected to the linear feedback via the feedback circuit as feedback tap and moves
The input terminal of bit register.
13. pseudo-random sequence generating means according to claim 12, which is characterized in that the feedback circuit includes：
Logic gates is connected together to linear feedback structure with the multiple trigger, wherein in the multiple trigger
The output end of specified one or more triggers is connected to as feedback tap via the logic gates described linear anti-
Present the input terminal of shift register；And
Selection circuit is connected between logic gates and the multiple trigger, for when receiving first control signal
According to the coefficient of the primitive polynomial of linear feedback shift register by the feedback tap of linear feedback shift register according to
One pattern is connected to the logic gates, when receiving second control signal according to the reversed of linear feedback shift register
The feedback tap of the linear feedback shift register is connected to the logic gate electricity by polynomial coefficient according to second mode
Road, the reversed multinomial to the primitive polynomial by inverting to obtain.
14. a kind of integrated circuit, which is characterized in that including being given birth to according to claim 9 to 13 any one of them pseudo-random sequence
At device.
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