CN108287682B - Pseudo-random sequence generation method and device and integrated circuit - Google Patents
Pseudo-random sequence generation method and device and integrated circuit Download PDFInfo
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- CN108287682B CN108287682B CN201810123943.1A CN201810123943A CN108287682B CN 108287682 B CN108287682 B CN 108287682B CN 201810123943 A CN201810123943 A CN 201810123943A CN 108287682 B CN108287682 B CN 108287682B
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Abstract
A method and a device for generating a pseudo-random sequence and an integrated circuit are provided, the length of the pseudo-random sequence is N bits, N is a positive integer greater than 1, the pseudo-random sequence is divided into a plurality of segments, and the method for generating the pseudo-random sequence comprises the following steps: construction letterNumber, said function embodying 2NThe relation between the total number of turns between each adjacent pseudo-random sequence in the pseudo-random sequences, the number of segments of the pseudo-random sequences and the length of each segment; calculating the number of segments and the length of each segment according to the function; generating a plurality of clock signals based on the calculated number of segments and the length of each segment, each clock signal corresponding to one segment; generating a plurality of segments of a pseudo-random sequence using the plurality of clock signals, respectively. The pseudo-random sequence is generated in a segmentation mode, and the turnover frequency between adjacent sequences can be reduced.
Description
Technical Field
The present disclosure relates to the field of digital signal processing technologies, and in particular, to a method and an apparatus for generating a pseudorandom sequence, and an integrated circuit.
Background
As semiconductor process dimensions continue to shrink, circuits may experience more and more failures, thus requiring large test vectors. However, due to the loading of the test vector during the test, the switching activity of each node of the circuit is higher than that in the normal operating mode, which causes larger dynamic power consumption, which has a serious influence on the reliability of the circuit. Currently, common test vector generation methods include accumulation and pseudorandom generation methods. For the addition method, the advantage is simple algorithm. However, this method consumes more circuit resources and the number of flips between adjacent sequences is large, for example, assuming that a group of 8-bit test sequences is generated by the cumulative addition method, a total of 2 from 00000000 to 11111111 can be generated8Then for the case where the currently generated test sequence is 00111111 and the next generated test sequence is 01000000, a total of 7 flips occur for the two adjacent test sequences. For the pseudo-random generation method, the method has the advantages of relatively simple algorithm and low consumption of circuit resources, and the test requirements can be met only by a long enough test vector. However, this method also results in a lengthy test vector and a large number of sequence flips, which results in a large dynamic power consumption.
Therefore, the problem of excessive number of inversions between adjacent sequences needs to be solved for generating the pseudo-random sequence.
Disclosure of Invention
In view of this, the present disclosure provides a method and an apparatus for generating a pseudo-random sequence, and an integrated circuit, which can effectively reduce the number of times of flipping between adjacent sequences.
According to a first aspect of the present disclosure, there is provided a method for generating a pseudorandom sequence, where the length of the pseudorandom sequence is N bits, and N is a positive integer greater than 1, where the pseudorandom sequence is divided into a plurality of segments, the method comprising: constructing a function embodying 2NThe relation between the total number of turns between each adjacent pseudo-random sequence in the pseudo-random sequences, the number of segments of the pseudo-random sequences and the length of each segment; calculating the number of segments and the length of each segment according to the function; generating a plurality of clock signals based on the calculated number of segments and the length of each segment, each clock signal corresponding to one segment; generating a plurality of segments of a pseudo-random sequence using the plurality of clock signals, respectively.
Preferably, the function comprises:
wherein the content of the first and second substances,
i is more than or equal to 1 and less than or equal to N, N is more than or equal to 2 and less than N, S represents the total turnover number of the pseudorandom sequence, SiRepresenting the number of inversions of segment i, n representing the number of segments of said pseudo-random sequence, L1,L2,…,LnRespectively represent the lengths of the n segments, and satisfy
i denotes a segment number.
Preferably, the calculating the number of segments and the length of each segment according to the function includes: calculating from said function the value of n which minimizes the value of S and the corresponding L1,L2,…,LnThe value is obtained.
Preferably, L(i-1)＜LiSaid calculating the number of segments and the length of each segment according to said function further comprises: determining a value range of N based on the value of N; within the value range according to the letterNumber calculation the value of n which minimizes the value of S and the corresponding L1,L2,…,LnThe value is obtained.
Preferably, the pseudo random sequence generating method further includes: adjusting the calculated number n of segments in combination with the circuit design complexity, and recalculating the corresponding L that minimizes the S value according to the function based on the adjusted number n of segments1,L2,…,LnThe value is obtained.
Preferably, the generating a plurality of clock signals based on the calculated number of segments and the length of each segment includes: generating n clock signals CLK1,CLK2,…,CLKnThe n clock signals CLK1,CLK2,…,CLKnClock period T of1,T2,…,TnSatisfy the relationship between
Where j denotes the number of the clock signal.
Preferably, the generating of the plurality of segments of the pseudo random sequence using the plurality of clock signals, respectively, includes: for each segment i, according to the length LiTo determine the L corresponding to the segment iiA primitive polynomial of a bit line linear feedback shift register; setting the L according to coefficients of the primitive polynomialiFeedback tap connection of bit linear feedback shift register to make LiThe bit linear feedback shift register generates the segment i.
Preferably, the generating of the plurality of segments of the pseudo random sequence using the plurality of clock signals, respectively, includes: for each segment i, according to the length L of the segment iiTo determine the corresponding LiBit line linear feedback shift register primitive polynomial, and invert the primitive polynomial to get the inverse polynomial; setting the L according to coefficients of the primitive polynomial in a first modeiFeedback tap connection of bit linear feedback shift register to connect the LiThe bit-wise linear feedback shift register outputs a positive segment i, and the L is set according to the coefficients of the inverse polynomial in a second modeiBit-linear inverseFeeding feedback taps of a shift register to connect the LiThe bit-linear feedback shift register outputs the inverted segment i.
According to another aspect of the present disclosure, there is provided a pseudo-random sequence generating apparatus, the length of the pseudo-random sequence being N bits, N being a positive integer greater than 1, wherein the pseudo-random sequence is divided into a plurality of segments, the pseudo-random sequence generating apparatus comprising: a plurality of linear feedback shift registers, each for generating one of the plurality of segments under control of a respective clock signal; and a clock signal generation circuit for generating a clock signal for each of the plurality of linear shift registers, respectively, wherein the number of segments and the length of each segment are set according to a function embodying the function 2NThe relation between the total number of turns between each adjacent pseudo-random sequence in the pseudo-random sequences, the number of segments of the pseudo-random sequences and the length of each segment; and the clock signal for each linear feedback shift register is generated based on the number of segments and the length of the respective segments.
Preferably, the function comprises:
wherein the content of the first and second substances,
i is more than or equal to 1 and less than or equal to N, N is more than or equal to 2 and less than N, S represents the total turnover frequency, SiRepresenting the number of inversions of segment i, n representing the number of segments of said pseudo-random sequence, L1,L2,…,LnRespectively represent the lengths of the n segments, and satisfy
i denotes a segment number.
Preferably, the clock signal generation circuit is configured to generate n clock signals CLK respectively corresponding to the n segments by frequency division1,CLK2,…,CLKnThe n clock signals CLK1,CLK2,…,CLKnClock period T of1,T2,…,TnSatisfy the relationship between
Where j denotes the number of the clock signal.
Preferably, each linear feedback shift register comprises: a plurality of flip-flops connected in series for generating respective bits of respective segments under control of respective clock signals; a feedback circuit connected to the plurality of flip-flops to form a linear feedback structure, wherein an output of a designated one or more flip-flops of the plurality of flip-flops is connected as a feedback tap to an input of the linear feedback shift register via the feedback circuit.
Preferably, the feedback circuit includes: a logic gate circuit connected to the plurality of flip-flops to form a linear feedback structure, wherein an output terminal of a designated one or more flip-flops among the plurality of flip-flops is connected as a feedback tap to an input terminal of the linear feedback shift register via the logic gate circuit; and a selection circuit, connected between the logic gate circuit and the plurality of flip-flops, for connecting the feedback tap of the linear feedback shift register to the logic gate circuit according to a first mode according to the coefficient of the primitive polynomial of the linear feedback shift register when receiving a first control signal, and connecting the feedback tap of the linear feedback shift register to the logic gate circuit according to a second mode according to the coefficient of the inverse polynomial of the linear feedback shift register when receiving a second control signal, the inverse polynomial being obtained by inverting the primitive polynomial.
According to another aspect of the present disclosure, there is provided an integrated circuit including the pseudo-random sequence generating apparatus described above.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
Fig. 1 shows a schematic flow diagram of a pseudo-random sequence generation method according to an embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a plurality of segments of a pseudo-random sequence according to an embodiment of the disclosure.
Fig. 3 shows a timing diagram of clock signals in the case of two segments according to an embodiment of the disclosure.
Fig. 4 illustrates an example block diagram of a pseudo-random sequence generation apparatus in accordance with an embodiment of this disclosure.
Fig. 5 is a diagram illustrating a comparison of the number of flips of the pseudo-random sequence generation method and apparatus of the present disclosure with the prior art.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
The invention provides a method and a device for generating a pseudo-random sequence, wherein the pseudo-random sequence is segmented, and a function which can reflect the relation between the total turning times between adjacent pseudo-random sequences, the number of segments of the pseudo-random sequence and the length of each segment is constructed, so that the segmentation mode which minimizes the total turning times can be calculated, and the turning times between adjacent sequences can be effectively reduced.
Fig. 1 shows a schematic flow diagram of a pseudo-random sequence generation method according to an embodiment of the present disclosure.
In step S101, a pseudo random sequence to be generated is divided into a plurality of segments. For example, assuming that a pseudorandom sequence of length N bits is to be generated, N being an integer greater than 1, then at this step the pseudorandom sequence may be divided into N segments, 2 ≦ N < N, the lengths of the N segments L respectively1,L2,…,LnAs shown in fig. 2. At this stage, the number n of segments and the length L of each segment1,L2,…,LnThe value of (a) is unknown.
In step S102, a function is constructed, said function embodying 2NAnd the relation between the total number of times of turning between each two adjacent pseudo-random sequences in the pseudo-random sequences, the number of segments of the pseudo-random sequences and the length of each segment. For example, the following function may be constructed:
wherein the content of the first and second substances,
i is more than or equal to 1 and less than or equal to N, N is more than or equal to 2 and less than N, S represents the total turnover frequency, SiRepresenting the number of inversions of segment i, n representing the number of segments of said pseudo-random sequence, L1,L2,…,LnRespectively represent the lengths of the n segments, and satisfy
i denotes a segment number.
The construction principle of the above function is described in detail below. In this embodiment, it is contemplated that the pseudo-random sequence is generated in a plurality of segments, each segment using a clock signal of a different frequency, such that each time an upper segment is generated, a certain number of lower segments are generated. For example, if an N-bit pseudo-random sequence is to be generated, it is contemplated that the pseudo-random sequence is generated by dividing the pseudo-random sequence into N segments, each segment having a length L1,L2,…,Ln. Each segment is generated using one clock signal, so that n segments require n clock signals CLK1,CLK2,…,CLKnThe n clock signals CLK1,CLK2,…,CLKnClock period T of1,T2,…,TnSatisfy the relationship between
Where j denotes the number of the clock signal.
In this case, for a length L1Segmentation of (1), total number of flips between adjacent sequences S1Satisfy the requirement of
I.e. each time
Each length is L1The total number of flips between adjacent sequences of the sequence is
Due to the clock signal CLK1And CLK2Clock period of
So that each generation has a length L1Will generate high-order segments
Each length is L2Is formed by the lower and upper sections
Then it means that the corresponding lower segment is flipped
Next, the process is carried out. Similarly, since
Each generation of a length L2Will generate a segment of
Each length is L3Is of length L2Segmented co-generation of
Then, it means corresponding toHas a length of L3Is sectionally turned over
Next, the process is carried out. By analogy, the turning times of all the segments are summed to obtain the above equation (1).
In step S103, a value range of N is determined based on the value of N. For example, the length L of n segments can be set1,L2,…,LnAll satisfy L(i-1)＜LiSince each segment has a length of at least 1 bit, for example, for the case of N ═ 20 bits, 1 bit +2 bits +3 bits +4 bits +5 bits < 20 bits, or 2 bits +3 bits +4 bits +5 bits +6 bits + 20 bits, it can be inferred that the maximum value of N is 5, i.e., N ranges from 2 to 5. Of course, this step is optional, and in some embodiments, the n value range may be determined in other manners or directly by using the above function (1).
In step S104, in the value range of n, the n value and the corresponding L value which minimize the S value according to the function1,L2,…LnThe value is obtained. Theoretically, the larger the value of n, the smaller the value of S, however, the embodiments of the present disclosure are not limited thereto, and the value of n may be adjusted by comprehensively considering other factors. For example, in some cases, a larger value of n may result in a higher circuit design complexity, and the value of n may be selected in combination with both the circuit design complexity and the degree of reduction in the number of flips. In some embodiments, for N ≦ 20, two segmentation is chosen, i.e., N ≦ 2. For example, N-2 may be selected for N-15, which is a trade-off result obtained by combining design complexity while reducing the Y value, rather than minimizing the Y value according to the above formula.
How to calculate L in the case where N is 15 and N is 2 is specifically described below1And L2。
The number of inversions of the pseudo-random sequence with N bits is S-N × 2 without segmentationN-1Is divided into a length L1And L2When two segments of (2) are generated, the two segments are respectively inverted within respective clock cycles by the number of times
And
according to the above equation (1), it can be derived that the sum of the number of adjacent sequence flips of the entire pseudo random sequence when n is 2 is:
by deriving the above equation (2), it can be derived that S has a minimum value when the following equation (3) is satisfied:
since N is known, L can be obtained therefrom1To obtain L2The value of (c). In this embodiment, N is 15, and L can be calculated by equation (3) above1Then, L is calculated as 1223. To this end, the value of the number n of segments and the length L of each segment are calculated1And L2The value of (c).
In step S105, the number n of segments and the length L of each segment are calculated1,L2,…LnA plurality of clock signals is generated, one for each segment. For example, after the number n of segments and the length L of each segment have been calculated1,L2,…LnIn the case of (2), a frequency division can be used to generate a frequency division signal satisfying the above
N clock signals CLK1,CLK2,…,CLKnIn some embodiments, this may be generated by dividing a frequency multiple times based on the system clock signal.
Fig. 3 shows the results when N is 15, N is 2, L1＝12，L2Clock signal CLK obtained in case of 31And CLK2Timing diagram of (2). As shown in fig. 3, whenClock signal CLK1And CLK2Clock period of
Namely T1＝8T2At the clock signal CLK1Can generate a length L of one clock cycle1(12 bit) segment in clock signal CLK2Can generate a length L of one clock cycle2(3 bits) of the clock signal CLK1Has a clock period of CLK2Is 8 times, so that for each generation of a 12-bit long high-order segment, 8 3-bit low-order segments are generated.
In step S106, a plurality of segments of a pseudo random sequence are generated using the plurality of clock signals, respectively. For example, it is possible to determine the length L for each segment iiTo determine the L corresponding to the segment iiA primitive polynomial of a bit linear feedback shift register, and setting the L according to coefficients of the primitive polynomialiFeedback tap connection of bit linear feedback shift register to make LiThe bit linear feedback shift register generates the segment i. In some embodiments, the generated pseudo-random sequence may be used not only as a test sequence, but also as a test address. Preferably, a sequence generation mode of forward and backward reversal can be set. For example, the length L of segment i can be determinediTo determine the corresponding LiA primitive polynomial of a linear feedback shift register of bit lines and inverting the primitive polynomial to obtain an inverse polynomial, the L being set in a first mode according to coefficients of the primitive polynomialiFeedback tap connection of bit linear feedback shift register to connect the LiThe bit-wise linear feedback shift register outputs a positive segment i, and the L is set according to the coefficients of the inverse polynomial in a second modeiFeedback tap connection of bit linear feedback shift register to make LiThe bit-linear feedback shift register outputs the inverted segment i.
Fig. 4 shows a schematic structural diagram of a pseudo-random sequence generation apparatus according to an embodiment of the present disclosure. In this implementationIn this example, the pseudo-random sequence generating means divides each pseudo-random sequence into n segments, the number of segments n and the length L of each segment1And L2May be calculated in the manner described in the above method embodiment. In this embodiment, N is 15, N is 2, and L is also used as the above1＝12，L2The case of 3 is described as an example, that is, each pseudorandom sequence is generated in two segments, the segment length of the upper bit is 12 bits, and the segment length of the lower bit is 3 bits.
As shown in fig. 4, the pseudo random sequence generating apparatus includes a 12-bit linear feedback shift register 10 and a 3-bit linear feedback shift register 20 and a clock signal generating circuit 30. Linear feedback shift register 10 for use in clocking signal CLK1For generating a pseudo-random sequence of upper 12 bits, a linear feedback shift register 20 for generating a pseudo-random sequence of upper 12 bits on a clock signal CLK2The lower 3 bits of the pseudo-random sequence are generated under control of (1).
The clock signal generating circuit 30 is used for generating the clock signal CLK as shown in FIG. 31And CLK2Both clock cycles satisfy
Namely T1＝8T2This may be calculated in the manner described in the above method embodiments. As an example, the clock signal generation circuit 30 may include an 1/8 frequency divider (shown as DIV (1/8)), the clock signal CLK2The system clock can be adopted, and CLK1May be obtained by dividing the system clock by one-eighth.
With continued reference to fig. 4, the linear feedback shift register 10 includes 12 flip-flops FF1, FF2, …, FF12, and a feedback circuit, the flip-flops FF1, FF2, …, FF12 are connected in series with each other, the feedback circuit is connected to the flip-flops FF1, FF2, …, FF12 to form a linear feedback structure, clock inputs of the flip-flops FF1, FF2, …, FF12 all receive a clock signal CLK1The outputs provide the upper 12 bits of the pseudo-random sequence, respectively. In the present embodiment, the feedback circuit includes a logic gate circuit including a plurality of logic gates G1, G2, G3, and a selection circuit,G4 and G5, the selection circuit includes a plurality of selectors E. As shown in fig. 3, the logic gates G1, G2, G3, G4 and G5 are connected with the flip-flops FF1, FF2, … and FF12 to form a linear feedback structure, wherein the types, numbers and connection manners of the logic gates G1, G2, G3, G4 and G5 can be selected according to the needs, for example, in the embodiment, G1 and G5 are exclusive or gates, G2 is a nor gate, and G3 and G4 are or gates, but it should be clear to those skilled in the art that the embodiments of the present disclosure are not limited thereto. The selection circuit comprises a plurality of selectors E connected among the flip-flops FF1, FF2, …, FF12 and logic gates G1, G2, G3, G4 and G5, wherein the selectors E are two-selection one-type selectors in the embodiment and are provided with two input ends (respectively represented by 0 and 1), one output end and one control end, the control end receives a control signal updn, and the selector E selects a signal of one of the two input ends to be output at the output end according to the control of the control signal updn.
The feedback tap connection of the linear feedback shift register 10 is described with continued reference to fig. 4. For an N-bit linear feedback shift register, the primitive polynomial can be expressed as:
H(X,N)＝M0X0+M1X1+…+MN-1XN-1(4)
coefficient M according to equation (4)0、M1、…、MN-1Connecting two input xor gate feedback can result in 2N-1 pseudo-random sequences, output in parallel at the output. Inverting equation (4) yields equation (5):
G(X,N)＝M0XN-1+M1XN-2X1+…+MN-1X0(5)
the sequences of H (X, N) and G (X, N) are reversed.
In fig. 4, the linear feedback shift register 10 is a 12-bit linear feedback shift register, and its primitive polynomial is:
H(X,12)＝X0+X3+X4+X7+X12(6)
inverting equation (6) can result in the following inverse polynomial:
G(X,12)＝X12+X9+X8+X5+X0(7)
the feedback taps of the linear feedback shift register 10 may be connected by the coefficients of equation (6) to output a forward sequence and the feedback taps of the linear feedback shift register 10 may be connected by the coefficients of equation (7) to output a reverse sequence. And in particular a forward output or a reverse output, can be realized by the selector E. In the present embodiment, the output terminals (denoted by Q in the figure) of the flip-flops FF3, FF4, FF7 and FF12 are connected as feedback taps to the xor gate G5 via the first input terminal (denoted by 0 in the figure) of the selector E, corresponding to the coefficient of equation (6); the outputs (denoted Q in the figure) of flip-flops FF1, FF4, FF5 and FF8 are connected as feedback taps via a second input (denoted 1 in the figure) of selector E to an xor gate G5, corresponding to the coefficient of equation (7). When the control signal updn is 0, the first input terminal (denoted by 0) of the selector E is gated such that the feedback taps of the linear feedback shift register 10 are connected in a forward output sequence, and when the control signal updn is 1, the second input terminal (denoted by 1) of the selector E is gated such that the feedback taps of the linear feedback shift register 10 are connected in a reverse output sequence. In this way, flexible control and switching of positive and negative outputs can be achieved.
The linear feedback shift register 20 has a similar structure and connection, and includes three flip-flops FF13, FF14, and FF15 connected in series, and a feedback circuit including a logic gate circuit including logic gates G6, G7, and G8 forming a linear feedback structure with the three flip-flops FF13, FF14, and FF15, and a selection circuit including a plurality of selectors C connected between the logic gate logic gates G6, G7, and G8 and the flip-flops FF13, FF14, and FF 15. As shown in fig. 3, the switching and control of the positive and negative bidirectional connections of the feedback taps of the 3-bit linear feedback shift register 20 are realized by a plurality of selectors E, similar to the above description, and will not be described again.
The pseudo-random sequence generating device can be arranged in an integrated circuit, so that the pseudo-random sequence generating device can be applied to various devices, apparatuses or equipment to realize the function of generating the pseudo-random sequence.
Although the above embodiments are all described by taking n-2 as an example, the embodiments of the present disclosure are not limited thereto, and the value of n may be calculated and selected in any manner as needed. The structure and connection relationship of the pseudo-random sequence generating apparatus may be changed according to the number of segments and the length of each segment, accordingly, in the manner described above. For example, when the preferred number of segments is calculated to be n — 3, substituting equation (1) can be derived by derivation:
l can be calculated to minimize the S value1、L2And L3The value of (c) is taken as the respective lengths of the three segments. And designing a clock signal, the number and bit width of the linear feedback shift register and feedback tap connection according to the calculated segment length, wherein the designed pseudo-random sequence generating device can generate a pseudo-random sequence according to the segment mode. Here, the minimum value calculation method is not limited to the above differentiation, but any mathematically feasible method may be used to calculate the segment length values that minimize the S value, such as a limit calculation method, and so on, which will not be described herein again.
Table 1 below shows the corresponding preferred segment length and the number of flips in the case of dividing the pseudorandom sequence into two segments, where H denotes the length of the upper segment, L denotes the length of the lower segment, and the bit width refers to the bit width of the pseudorandom sequence in kb. The bit width refers to a bit width of the test sequence if the generated pseudo random sequence is used as the test sequence, and to an address bit width, i.e., an address depth, if the generated pseudo random sequence is used as the test address.
TABLE 1
Fig. 5 is a diagram illustrating comparison of the number of inversions of the pseudo-random sequence generation method and apparatus of the present disclosure with the prior art, where a dotted line illustrates the total number of inversions of the adjacent sequence of the pseudo-random sequence generated by the conventional method, and an implementation illustrates the total number of inversions of the adjacent sequence of the pseudo-random sequence generated by the method of the present disclosure, where an abscissa represents a bit width of the generated pseudo-random sequence, and a kb (kilobyte) is taken as a unit, and an ordinate represents the total number of inversions of the adjacent sequence.
As can be seen from fig. 5, the method and apparatus for generating a pseudorandom sequence according to the embodiments of the present disclosure generate a pseudorandom sequence by segmentation, calculate a reasonable number of segments and segment length according to a function of a relationship between a total number of constructed flips and the number of segments of the pseudorandom sequence and the length of each segment, and can significantly reduce the number of flips of adjacent sequences, thereby reducing system power consumption, and meanwhile, have the advantages of low area cost, high processing speed, and the like.
The embodiment of the disclosure balances the number of the segments by combining other factors such as circuit design complexity, can simplify the circuit design while reducing the sequence turning times, and has flexible implementation mode.
The embodiment of the disclosure realizes a positive and negative bidirectional sequence generation mode by using a logic gate circuit and a selection circuit in a pseudo-random sequence generation device, and has wider application range and flexible use.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims (14)
1. A method for generating a pseudo-random sequence, wherein the length of the pseudo-random sequence is N bits, and N is a positive integer greater than 1, the method is characterized in that the pseudo-random sequence is divided into a plurality of segments, and the method comprises the following steps:
constructing a function embodying 2NEach of said pseudo-random sequencesThe relation between the total number of turns between each two adjacent pseudo-random sequences, the number of segments of the pseudo-random sequences and the length of each segment;
calculating the number of segments and the length of each segment according to the function;
generating a plurality of clock signals based on the calculated number of segments and the length of each segment, each clock signal corresponding to one segment;
generating a plurality of segments of a pseudo-random sequence using the plurality of clock signals, respectively.
2. The pseudo-random sequence generation method of claim 1, wherein the function comprises:
wherein the content of the first and second substances,
i is more than or equal to 1 and less than or equal to N, N is more than or equal to 2 and less than N, S represents the total turnover number of the pseudorandom sequence, SiRepresenting the number of inversions of segment i, n representing the number of segments of said pseudo-random sequence, L1,L2,…,LnRespectively represent the lengths of the n segments, and satisfy
i denotes a segment number.
3. The method of claim 2, wherein calculating the number of segments and the length of each segment according to the function comprises: calculating from said function the value of n which minimizes the value of S and the corresponding L1,L2,…,LnThe value is obtained.
4. The pseudo-random sequence generation method of claim 3, wherein L is(i-1)＜LiSaid function being based onCalculating the number of the segments and the length of each segment further comprises:
determining a value range of N based on the value of N;
in the value range, calculating the n value and the corresponding L which enable the S value to be minimum according to the function1,L2,…,LnThe value is obtained.
5. The pseudo-random sequence generation method of claim 3, further comprising adjusting the calculated number of segments n in conjunction with circuit design complexity, and recalculating the corresponding L that minimizes the S value according to the function based on the adjusted number of segments n1,L2,…,LnThe value is obtained.
6. The pseudo-random sequence generation method of claim 2, wherein said generating a plurality of clock signals based on the calculated number of segments and the length of each segment comprises: generating n clock signals CLK1,CLK2,…,CLKnThe n clock signals CLK1,CLK2,…,CLKnClock period T of1,T2,…,TnSatisfy the relationship between
Where j denotes the number of the clock signal.
7. The pseudo-random sequence generation method of claim 6, wherein said generating a plurality of segments of a pseudo-random sequence using said plurality of clock signals, respectively, comprises: for each of the segments i, there is a segment i,
according to the length LiTo determine the L corresponding to the segment iiA primitive polynomial of a bit line linear feedback shift register;
setting the L according to coefficients of the primitive polynomialiFeedback tap connection of bit linear feedback shift register to make LiThe bit linear feedback shift register generates the segment i.
8. The pseudo-random sequence generation method of claim 6, wherein said generating a plurality of segments of a pseudo-random sequence using said plurality of clock signals, respectively, comprises: for each of the segments i, there is a segment i,
according to the length L of the segment iiTo determine the corresponding LiBit line linear feedback shift register primitive polynomial, and invert the primitive polynomial to get the inverse polynomial;
setting the L according to coefficients of the primitive polynomial in a first modeiFeedback tap connection of bit linear feedback shift register to connect the LiThe bit-wise linear feedback shift register outputs a positive segment i, and the L is set according to the coefficients of the inverse polynomial in a second modeiFeedback tap connection of bit linear feedback shift register to make LiThe bit-linear feedback shift register outputs the inverted segment i.
9. A pseudo-random sequence generating apparatus, the length of the pseudo-random sequence being N bits, N being a positive integer greater than 1, wherein the pseudo-random sequence is divided into a plurality of segments, the pseudo-random sequence generating apparatus comprising:
a plurality of linear feedback shift registers, each for generating one of the plurality of segments under control of a respective clock signal; and
a clock signal generation circuit for generating a clock signal separately for each of the plurality of linear feedback shift registers,
wherein the content of the first and second substances,
the number of segments and the length of each segment are set according to a function, said function embodying 2NThe relation between the total number of turns between each adjacent pseudo-random sequence in the pseudo-random sequences, the number of segments of the pseudo-random sequences and the length of each segment; and is
The clock signal for each linear feedback shift register is generated based on the number of segments and the length of each segment.
10. The pseudo-random sequence generating apparatus of claim 9, wherein the function comprises:
wherein the content of the first and second substances,
i is more than or equal to 1 and less than or equal to N, N is more than or equal to 2 and less than N, S represents the total turnover frequency, SiRepresenting the number of inversions of segment i, n representing the number of segments of said pseudo-random sequence, L1,L2,…,LnRespectively represent the lengths of the n segments, and satisfy
i denotes a segment number.
11. The pseudo-random sequence generating apparatus according to claim 10, wherein the clock signal generating circuit is configured to generate n clock signals CLK respectively corresponding to the n segments by frequency division1,CLK2,…,CLKnThe n clock signals CLK1,CLK2,…,CLKnClock period T of1,T2,…,TnSatisfy the relationship between
Where j denotes the number of the clock signal.
12. The pseudo-random sequence generating apparatus of claim 9, wherein each linear feedback shift register comprises:
a plurality of flip-flops connected in series for generating respective bits of respective segments under control of respective clock signals;
a feedback circuit connected to the plurality of flip-flops to form a linear feedback structure, wherein an output of a designated one or more flip-flops of the plurality of flip-flops is connected as a feedback tap to an input of the linear feedback shift register via the feedback circuit.
13. The pseudo-random sequence generating apparatus of claim 12, wherein the feedback circuit comprises:
a logic gate circuit connected to the plurality of flip-flops to form a linear feedback structure, wherein an output terminal of a designated one or more flip-flops among the plurality of flip-flops is connected as a feedback tap to an input terminal of the linear feedback shift register via the logic gate circuit; and
and the selection circuit is connected between the logic gate circuit and the plurality of triggers and is used for connecting the feedback tap of the linear feedback shift register to the logic gate circuit according to a first mode according to the coefficient of the primitive polynomial of the linear feedback shift register when receiving a first control signal, and connecting the feedback tap of the linear feedback shift register to the logic gate circuit according to a second mode according to the coefficient of the inverse polynomial of the linear feedback shift register when receiving a second control signal, wherein the inverse polynomial is obtained by inverting the primitive polynomial.
14. An integrated circuit comprising the pseudo-random sequence generating apparatus of any one of claims 9 to 13.
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