CN110391300B - Schottky field effect transistor and manufacturing method thereof - Google Patents
Schottky field effect transistor and manufacturing method thereof Download PDFInfo
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- CN110391300B CN110391300B CN201910743008.XA CN201910743008A CN110391300B CN 110391300 B CN110391300 B CN 110391300B CN 201910743008 A CN201910743008 A CN 201910743008A CN 110391300 B CN110391300 B CN 110391300B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 230000005669 field effect Effects 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- SCURPRRYUOUTJX-UHFFFAOYSA-N [Si].[Eu] Chemical compound [Si].[Eu] SCURPRRYUOUTJX-UHFFFAOYSA-N 0.000 claims description 6
- AABGKKDTOXGNDF-UHFFFAOYSA-N [Si].[Gd] Chemical compound [Si].[Gd] AABGKKDTOXGNDF-UHFFFAOYSA-N 0.000 claims description 6
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 claims description 6
- TVGGZXXPVMJCCL-UHFFFAOYSA-N [Si].[La] Chemical compound [Si].[La] TVGGZXXPVMJCCL-UHFFFAOYSA-N 0.000 claims description 6
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 6
- UVGLBOPDEUYYCS-UHFFFAOYSA-N silicon zirconium Chemical compound [Si].[Zr] UVGLBOPDEUYYCS-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 abstract description 9
- 230000005641 tunneling Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
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Abstract
The application discloses a schottky field effect transistor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The schottky field effect transistor includes: a substrate, wherein the first end part of the substrate is a step-shaped groove; a drain structure disposed on the second end of the substrate and a source structure disposed on the first end, the source structure comprising a metal silicide; a channel structure disposed over the substrate between the source structure and the drain structure; and a gate structure disposed on the channel structure. According to the Schottky field effect transistor, the first end of the substrate is set to be the step-shaped groove, the source electrode structure is arranged on the step-shaped groove, the drain electrode structure is arranged on the second end of the substrate, the grid electrode structure is arranged on the channel structure between the source electrode structure and the drain electrode structure, and the barrier width at the source electrode structure is reduced when the Schottky field effect transistor is conducted due to the fact that the source electrode structure is arranged on the step-shaped groove of the substrate, so that tunneling current of the device is increased, and channel current of the device in an on state is increased.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a schottky field effect transistor and a manufacturing method thereof.
Background
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), also known as a schottky field effect transistor, uses a schottky barrier Metal silicide instead of the source and drain regions formed by N-type ion implantation or P-type ion implantation in conventional MOSFET devices.
The operating characteristics of schottky field effect transistors are based on the direct tunneling effect of the schottky barrier formed by the carriers between the source region and the channel, the width of the barrier being controlled by the gate voltage. When the barrier is sufficiently thin, carriers are injected from the source region into the channel through the schottky barrier of the metal silicide interface under appropriate source-drain bias, and pass through the channel into the drain region to effect device conduction. However, the schottky field effect transistor provided in the related art has a defect that leakage current and parasitic current are large in an off state.
Disclosure of Invention
The embodiment of the application provides a Schottky field effect transistor and a manufacturing method thereof, which can solve the problem that the Schottky field effect transistor provided in the related art has larger leakage current and parasitic current in the off state.
In one aspect, an embodiment of the present application provides a schottky field effect transistor, including:
a substrate, a first end of the substrate comprising a stepped recess;
a drain structure disposed on the second end of the substrate and a source structure disposed on the first end, the source structure comprising a metal silicide;
a channel structure disposed over the substrate between the source structure and the drain structure;
and the grid structure is arranged on the channel structure.
In an alternative embodiment, the metal silicide includes any one of hafnium silicon, zirconium silicon, lanthanum silicon, titanium silicon, europium silicon, and gadolinium silicon.
In an alternative embodiment, the channel structure comprises silicon oxide.
In an alternative embodiment, the substrate is a silicon-on-insulator SOI structure, the SOI structure includes a bottom layer, an isolation layer and a pattern layer in sequence from bottom to top, and the first end of the pattern layer is the stepped recess.
In an alternative embodiment, the gate is provided with sidewalls on its periphery.
In an alternative embodiment, the sidewalls comprise an oxide or nitride.
In one aspect, an embodiment of the present application provides a method for manufacturing a schottky field effect transistor, where the method includes:
providing a substrate;
generating a channel layer on the substrate;
removing the channel layer above the first active region of the substrate by a dry etching process, and forming a step-shaped groove by etching;
removing a channel layer above a second active region of the substrate by the dry etching process, wherein the channel layer between the first active region and the second active region forms a channel structure;
generating a drain structure on the second active region;
generating a source structure on the first active region, wherein the source structure comprises metal silicide;
a gate structure is formed over the channel structure.
In an alternative embodiment, the generating a source structure on the first active area includes:
and depositing the metal silicide on the first active region through a photoetching process to form the source electrode structure.
In an alternative embodiment, the metal silicide includes any one of hafnium silicon, zirconium silicon, lanthanum silicon, titanium silicon, europium silicon, and gadolinium silicon.
In an alternative embodiment, the channel layer comprises a silicon oxide layer;
the generating a channel layer on the substrate includes:
and forming a silicon oxide layer on the substrate through a furnace tube oxidation process.
In an alternative embodiment, forming a gate structure over the channel structure includes:
depositing polysilicon on the channel structure through a photoetching process to form a grid electrode;
and depositing a side wall on the periphery of the grid electrode through a photoetching process to form the grid electrode structure.
In an alternative embodiment, the sidewalls comprise an oxide or nitride.
The technical scheme of the application at least comprises the following advantages:
by arranging the first end part of the substrate into the step-shaped groove, arranging the source electrode structure on the step-shaped groove, arranging the drain electrode structure on the second end part of the substrate, and arranging the grid electrode structure on the channel structure between the source electrode structure and the drain electrode structure, the barrier width at the source electrode structure is reduced when the Schottky field effect transistor is conducted due to the fact that the source electrode structure is arranged on the step-shaped groove of the substrate, tunneling current of the device is increased, and channel current of the device in an on state is increased.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a cross-sectional view of a schottky field effect transistor provided in an exemplary embodiment of the present application;
fig. 2 is a flowchart of a method for manufacturing a schottky field effect transistor according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Fig. 1 illustrates a cross-sectional view of a schottky field effect transistor provided in an exemplary embodiment of the present application. Referring to fig. 1, a schottky field effect transistor 100 provided in the present embodiment includes:
a substrate 110, a first end of the substrate 110 comprising a stepped recess 101.
Wherein the substrate 110 is a silicon (Si) substrate. Alternatively, the substrate 110 may be a Silicon-On-Insulator (SOI) structure On an insulating substrate, which includes, from bottom to top, a bottom layer 111, an isolation layer 112, and a pattern layer 113, where a first end of the pattern layer 113 is a stepped recess 101. Illustratively, underlayer 111 and patterned layer 113 comprise silicon, and/or germanium; the isolation layer 112 includes an oxide or nitride, for example, silicon oxide, silicon nitride, or the like.
A drain structure 120 disposed on a second end of the substrate 110, and a source structure 130 disposed on the stepped recess 101.
The source structure 130 includes a metal silicide. Optionally, the metal silicide includes any one of hafnium silicon, zirconium silicon, lanthanum silicon, titanium silicon, europium silicon and gadolinium silicon. Optionally, the drain structure 120 is also a metal silicide, which may be any of the metal silicides described above.
A channel structure 140 disposed over the substrate 110 between the source structure 130 and the drain structure 120. Optionally, the channel structure 140 comprises silicon oxide. The channel structure 140 and the source structure 130 contact to form a schottky barrier.
A gate structure 150 disposed over the channel structure 140. Optionally, the gate structure 150 comprises polysilicon; alternatively, the gate structure 150 is formed with a sidewall 151 on a peripheral side thereof, and the sidewall 151 includes an oxide or nitride, for example, silicon oxide or silicon nitride.
In summary, in this embodiment of the present application, by setting the first end of the substrate to be a stepped groove, setting the source structure on the stepped groove, setting the drain structure on the second end of the substrate, and setting the gate structure on the channel structure between the source structure and the drain structure, since the source structure is set on the stepped groove of the substrate, the barrier width at the source structure becomes smaller when the schottky field effect transistor is turned on, so as to increase the tunneling current of the device, and further increase the channel current of the device when it is turned on.
Fig. 2 is a flowchart illustrating a method for manufacturing a schottky field effect transistor according to an exemplary embodiment of the present application. The manufacturing method may manufacture the schottky field effect transistor 100 in the embodiment of fig. 1, which includes:
in step 201, a substrate is provided.
The substrate may be the substrate 110 in the embodiment of fig. 1.
Illustratively, a silicon oxide layer may be formed on a substrate by a furnace tube oxidation process.
For example, a first end of the substrate may be defined as a first active region and a second end of the substrate as a second active region, wherein the first active region is used to form a source structure and the second active region is used to form a drain structure. The photoresist can be covered on the first active area through a photoetching process, and a channel layer above the first active area of the substrate is removed through a dry etching process; and covering the photoresist on the upper step area of the step-shaped groove, continuing etching, forming the first end part into the step-shaped groove, and cleaning the photoresist. The stepped recess may be referred to in the embodiment of fig. 1.
And 204, removing the channel layer above the second active region of the substrate through a dry etching process, wherein the channel layer between the first active region and the second active region forms a channel structure.
Illustratively, the photoresist may be covered on the second active region by a photolithography process, the channel layer over the second active region of the substrate may be removed by a dry etching process, and the photoresist may be cleaned.
A drain structure is generated over the second active region, step 205.
For example, photoresist may be coated in other regions except the second active region by a photolithography process, a metal silicide is deposited in the second active region to form a drain structure, and the photoresist is cleaned.
At step 206, a source structure is formed on the first active region, the source structure comprising a metal silicide.
For example, the photoresist may be coated in other regions except the first active region by a photolithography process, a metal silicide is deposited on the first active region to form a source structure, and the photoresist is cleaned.
It should be noted that, the metal silicide in the embodiments of the present application includes any one of hafnium silicon, zirconium silicon, lanthanum silicon, titanium silicon, europium silicon, and gadolinium silicon.
In step 207, a gate structure is formed over the channel structure.
Illustratively, the gate electrode may be formed by depositing polysilicon over the channel structure by a photolithographic process; and depositing a side wall on the periphery of the grid electrode through a photoetching process to form a grid electrode structure. The sidewall comprises an oxide or nitride.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (3)
1. A schottky field effect transistor comprising:
a substrate, a first end of the substrate comprising a stepped recess;
a drain structure disposed on the second end of the substrate and a source structure disposed on the first end, the source structure comprising a metal silicide comprising any one of hafnium silicon, zirconium silicon, lanthanum silicon, titanium silicon, europium silicon and gadolinium silicon;
a channel structure disposed over the substrate between the source structure and the drain structure, the channel structure comprising silicon oxide;
and the gate structure is arranged on the channel structure, and the side wall is arranged on the periphery of the gate and comprises oxide or nitride.
2. The schottky field effect transistor of claim 1 wherein the substrate is a silicon-on-insulator SOI structure comprising, in order from bottom to top, a bottom layer, an isolation layer, and a pattern layer, the first end of the pattern layer being the stepped recess.
3. A method of manufacturing a schottky field effect transistor, the method comprising:
providing a substrate;
forming a silicon oxide layer on the substrate through a furnace tube oxidation process to form a channel layer;
removing the channel layer above the first active region of the substrate by a dry etching process, and forming a step-shaped groove by etching;
removing a channel layer above a second active region of the substrate by the dry etching process, wherein the channel layer between the first active region and the second active region forms a channel structure;
generating a drain structure on the second active region;
depositing metal silicide on the first active region through a photoetching process to form a source electrode structure, wherein the metal silicide comprises any one of hafnium silicon, zirconium silicon, lanthanum silicon, titanium silicon, europium silicon and gadolinium silicon;
depositing polysilicon on the channel structure through a photoetching process to form a grid electrode;
and depositing a side wall on the periphery of the grid through a photoetching process to form the grid structure, wherein the side wall comprises oxide or nitride.
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| CN112614890A (en) * | 2020-12-16 | 2021-04-06 | 西安电子科技大学 | All-vertical field effect transistor based on transverse Schottky source tunneling junction and method |
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| JP4996390B2 (en) * | 2007-08-28 | 2012-08-08 | 株式会社東芝 | Spin FET and magnetoresistance effect element |
| CN103606563B (en) * | 2013-10-22 | 2016-06-01 | 清华大学 | Without knot type tunneling field-effect transistor and forming method thereof |
| US11107908B2 (en) * | 2016-07-01 | 2021-08-31 | Intel Corporation | Transistors with metal source and drain contacts including a Heusler alloy |
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