KR100777101B1 - Manufacturing Schottky-Barrier MOSFETs with low barrier height and manufacturing method thereof - Google Patents

Abstract

The present invention forms a Schottky junction on a silicon (111) surface (Miller index indicating its crystal direction in a semiconductor having a crystalline structure) produced through anisotropic etching, which is stable and high performance having a low Schottky barrier to electrons. To fabricate an N-type Schottky barrier through transistor. To this end, a Schottky barrier through transistor according to an embodiment of the present invention, a substrate; A source and a drain formed on the substrate; A channel formed between the source and the drain; A gate insulating film and a gate electrode sequentially formed on the channel; and a sidewall insulating film formed on both sidewalls of the gate insulating film and the gate electrode, wherein an interface between the source and drain and the channel has a silicon (111) plane, and the silicon On the (111) plane, the source and the drain are silicided with a metal material to be a Schottky junction.

Schottky Barrier Penetration, Anisotropic Etching

Description

Manufacturing Schottky-Barrier MOSFETs with low barrier height and manufacturing method

1 is a view showing the configuration of a Schottky barrier through transistor according to the prior art

2 is a diagram illustrating the configuration of a Schottky barrier through transistor according to the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a schottky barrier through transistor according to an embodiment of the present invention.

4 is a view showing the electrical characteristics measurement results of the erbium silicide Schottky diode fabricated on the silicon (100) surface and the silicon (111) surface, respectively

<Explanation of symbols for the main parts of the drawings>

10: substrate 20: insulating layer

30: SOI layer 30a: source region

30b: drain region 40: gate insulating film

50 sidewall insulating film 60 gate electrode

70 nitride film 80 channel region
90: metal material

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TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a Schottky barrier through transistor and a method of manufacturing the same.

Semiconductor manufacturing technology has been advanced in the direction of low power, high integration, and high speed operation, and MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) has been miniaturized to satisfy these conditions. Integration over the last three decades has been well illustrated by Gordon Moore's law that the number of transistors on a chip doubles every 18 months. Thus, the current transistor has a gate length of less than 100 nm.

The International Technology Roadmap for Semiconductors (ITRS), published in 2003, predicts that the gate length of transistors will be 30 nm in 2005 and 10 nm in 2015.

However, when the transistor is small in size, it exhibits different characteristics from those of the conventional device. First, as the gate insulating layer becomes thinner, the thickness of the gate insulating layer is reduced, the leakage current due to the tunneling of electrons through the insulating layer, and the short channel effect. Increase, punch-through and the like occur. In addition, there are problems such as fluctuations in threshold voltage due to uneven distribution of impurities in the channel portion, and deterioration of the insulating film due to charge trapped in the insulating film due to the hot-carrier effect. The reliability is lowered.

Therefore, there are many problems to overcome such as nanolithography technology in order to manufacture and operate transistors in the size predicted by the ITRS data.

To reduce the short channel effects described above, shallow junctions of the source and drain are required. However, doping by ion implantation, which is generally used for source and drain formation, is not only difficult to control uniformly and shallowly, but also has a large sheet resistance corresponding to channel resistance.

In order to overcome these problems, researches are being conducted to replace insulating films, gates, sources and drains with new materials, and structural changes have been attempted.

One of them is a Schottky barrier through transistor, which makes the source and drain a silicide, a metal compound of silicon rather than doping, forming a Schottky barrier between the source, drain and channel.

1 is a view showing the configuration of a Schottky barrier through transistor according to the prior art.

As shown in FIG. 1, the insulating layer 20 formed on the substrate 10 and the channel region 80 and the source / drain regions 30a and 30b having a predetermined impurity concentration on the insulating layer 20 are low. The source / drain regions 30a and 30b are silicided with a predetermined metal to be schottky bonded to the channel region 80 and sequentially formed on the channel region 80. ) And the gate electrode 60 and the sidewall insulating film 50 formed on both sidewalls of the gate insulating film 40 and the gate electrode 60.

In this case, when the SOI layer uses a substrate having the most commonly used silicon (100) direction and forms an erbium silicide / silicon schottky junction to realize a low barrier height, the barrier height for electrons is about 0.4 V. Obtained.

Schottky-barrier through-transistor technology, which is configured as described above, maintains a constant barrier height to control leakage current even in the case of short-channel MOS transistors having a gate length of 100 nm or less. It can be manufactured to have a small sheet resistance. As such, the small sheet resistance of the source and drain of the Schottky barrier through transistor is a parasitic resistance of the transistor and affects the characteristics of the transistor including the operating speed. Therefore, the Schottky barrier through transistor is an element that is advantageous for miniaturization and integration as well as high speed.

In addition, as the size of the transistor becomes smaller, the thickness of the gate insulating layer 40 must be thinner to effectively lower the electric field of the channel due to the drain. However, as the gate insulating layer 40 becomes thinner, the leakage current from the gate electrode 60 increases, and therefore, researches to replace the conventional silicon oxide film with ferroelectric rare earth oxide film materials have been actively conducted.

In addition, the polycrystalline silicon gate has the advantage that the channel can control the work function according to the n-type or p-type, and the process itself is well known, and the yield can be increased. However, a depletion layer is formed at the interface of the polycrystalline silicon to thicken the insulating film and have a high resistance. Because of its shortcomings, it is being studied to be replaced by nitride gate or silicide gate.

Accordingly, since the Schottky barrier through transistor configured as shown in FIG. 1 makes the source / drain regions 30a and 30b into silicide, unlike the process of the conventional MOS field effect transistor, since the heat treatment is not necessary after the injection of impurities, 600 The process is performed at a low temperature of less than or equal to ℃, so it is also suitable to use a ferroelectric material as a silicide metal gate or an insulating film.

In this characteristic of the Schottky barrier through transistor, the Schottky junction of the metal silicide and the silicon interface is an important factor in the performance of the device. In other words, transistors with low Schottky barriers have good off-state characteristics, but on the other hand, high Schottky barriers have large resistances resulting in lower operating currents and inflow of negative charges (holes for electrons in the N-type). The off current is high, which deteriorates the characteristics of the transistor.

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Thus, silicides are made from metals such as erbium, ytterbium, yttrium and samarium with low work functions in N-type Schottky barrier through transistors to form low Schottky barriers. However, the Schottky barrier height during Schottky bonding depends not only on the work function of the interface silicide and the electron affinity of silicon, but also on the impurities and interface state of silicon and the microstructure of the interface.

Thus, despite the use of such low-working metals, the actual Schottky barrier height is not easily controlled because it is affected by the other conditions listed above.

Accordingly, the present invention has been made to solve the above problems, by forming a Schottky junction on the silicon (111) surface (Miller index indicating the crystal direction in a semiconductor having a crystal structure) produced through anisotropic etching, The purpose is to fabricate a high performance N-type Schottky barrier through transistor having a low Schottky barrier for.

Schottky barrier through transistor according to the present invention for achieving the above object, the substrate; A source and a drain formed on the substrate; A channel formed between the source and the drain; A gate insulating film and a gate electrode sequentially formed on the channel; And a sidewall insulating film formed on both sidewalls of the gate insulating film and the gate electrode, wherein an interface between the source and the drain and the channel has a silicon 111 surface, and the silicon 111 surface, the source and the drain silicide with a metal material. And the Schottky splice.

According to another aspect of the present invention, there is provided a method of manufacturing a Schottky barrier through transistor, including: defining a channel region, a source region, and a drain region by patterning an SOI layer of a silicon on insulator (SOI) substrate; Sequentially forming a gate insulating film, a gate electrode, and a nitride film on the channel region; Forming a sidewall insulating film on sidewalls of the gate insulating film, the gate electrode and the nitride film; Removing the nitride layer after forming a silicon (111) surface by performing anisotropic etching on the interface between the channel region, the source region and the drain region; Forming a Schottky junction interface in the channel region including the silicon 111 surface by depositing a metal material on the source region, the drain region and the silicon 111 surface, and then silicidating the metal material.

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Preferably, the impurity concentration of the semiconductor layer is characterized in that less than 10 ¹⁷ cm ^-3 .

Preferably, the gate insulating film is formed of any one of a silicon oxide film (SiO ₂ ), an aluminum oxide film (Al ₂ O ₃ ), and a hafnium oxide film (HfO ₂ ).

Preferably, the gate electrode is made of one of polysilicon, aluminum, and titanium (Ti).

Preferably, the sidewall insulating film is formed of a silicon oxide film (SiO ₂ ).

Preferably, the gate electrode size and the width of the channel region are 10 nm or less.

Preferably, the anisotropic etching is characterized in that the wet etching isotropically using KOH or TMAH (tetra-methyl ammonium hydroxide).

Preferably, forming the Schottky junction interface comprises removing a metal material that is not reacted with the silicide.

Preferably, the metal material is formed of one of erbium, ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium (Ce). .

Preferably the silicide is characterized in that the heat treatment in the temperature range of 400 ℃ to 600 ℃.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

A preferred embodiment of a Schottky barrier through transistor and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings. In the following description, the silicidation of the silicon 111 refers to silicidation of the silicon 111 by penetrating a metal material into the silicon 111.

2 is a diagram illustrating the configuration of a Schottky barrier through transistor according to the present invention.

As shown in FIG. 2, between the substrate 10 on which the insulating layer 20 is deposited, between the source / drain 30a and 30b formed on the insulating layer 20, and the source / drain 30a and 30b. A channel 80 formed in the gate insulating layer, the gate insulating film 40 and the gate electrode 60 sequentially formed on the channel 80, and a sidewall insulating film formed on both sidewalls of the gate insulating film 40 and the gate electrode 60. It consists of 50. In this case, an interface between the source and drain 30a and 30b and the channel 80 has a silicon 111 surface, and a source and drain 30a and 30b bonded to the silicon 111 surface are predetermined. It is silicided with a metal material of to form a Schottky junction.

The height of the channel is formed to be higher than the height of the source and drain, so that the interface has an inclined surface. And silicon 111 silicide at the inclined surface.

At this time, it is preferable to use an SOI substrate as the substrate, but it is not limited to the SOI substrate, and the bulk silicon substrate may be manufactured in the same manner by applying the technical details described later.

A method of manufacturing a Schottky barrier through transistor according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing a schottky barrier through transistor according to an embodiment of the present invention.

First, as illustrated in FIG. 3A, a silicon on insulator (SOI) substrate has a silicon substrate 10 at a lowermost portion thereof, and an SOI layer 30 having an insulating layer 20 and a silicon layer thereon. The SOI layer 30 is patterned by leaving an active region in which a channel, a source, and a drain are to be formed using a predetermined etching mask (not shown).

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The impurity concentration of the SOI layer 30 uses a lightly doped substrate of 10 ¹⁷ cm ⁻³ or less.

Subsequently, as shown in FIG. 3B, the gate insulating film 40 and the polysilicon or metal are deposited on a predetermined region of the SOI layer 30 to form the gate electrode 60, and the gate electrode 60 is protected thereon. A nitride film (silicon nitride) 70 is formed sequentially. After the patterning is performed using an etching mask such as a photoresist, dry etching is performed to etch the gate insulating layer 40, the gate electrode 60, and the nitride layer 70.
In this case, the gate insulating layer 40 may use a silicon oxide film (SiO ₂ ) formed by thermally oxidizing silicon in a general case, and in order to use a higher gate electric field effect, an aluminum oxide film (Al ₂ O ₃ ) or hafnium may be used. It is also possible to use a high dielectric constant thin film such as an oxide film (HfO ₂ ). In addition, polysilicon, which is widely used as a material used as the gate electrode 60, may be used. For the performance of the Schottky Barrier Transistor Transistor (SB-SET), a metal material such as aluminum and titanium (Ti) may be used. It is also possible to use.

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3C, sidewalls formed on sidewalls of the gate insulating layer 40, the gate electrode 60, and the nitride layer 70 to prevent electrical connection when the silicide is formed on the source and drain and the gate electrode 60. After depositing a sidewall spacer, the sidewall insulating film 50 is formed on sidewalls of the gate insulating film 40, the gate electrode 60, and the nitride film 70 by etching through a dry etching method.

At this time, the material used as the sidewall insulating film 50 is preferably a material having a low dielectric constant, a typical one is an insulating film composed of a silicon oxide (SiO ₂ ) material.

Next, as shown in FIG. 3D, an interface between a source / drain region 30a (see FIG. 2) (30b, FIG. 2) and a channel region 80 (see FIG. 2) using KOH or THAM (tetramethyl-ammonium-hydroxide) Is anisotropically wet-etched to prepare a silicon (111) side. At this time, it may be produced using suitable conditions of dry etching.

Through such etching, the source / drain region has a height lower than that of the channel region, and thus the interface has an inclined slope.

3E, the nitride film (silicon nitride) 70 left to protect the gate electrode 60 is removed through wet etching or dry etching, and the entire surface of the resultant including the silicon 111 surface is removed. A metal material 90 having a predetermined thickness is deposited on the upper surface.

In this case, the solution used in the wet etching may use a solution having a higher selectivity than the sidewall insulating film 50, thereby minimizing damage to the sidewall insulating film 50 due to the wet etching. In addition, it is preferable to use erbium, ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium (Ce) as the metal material 90. Do.

Finally, as shown in FIG. 3F, the resultant including the silicon 111 surface on which the metal material 90 having a predetermined thickness is deposited is heat-treated by a rapid thermal treatment (RTA) device to form silicide. Accordingly, the source / drain regions 30a and 30b are silicided with the metal material 90 to be schottky junctioned with the channel region 80.

In this case, the silicide is formed only in the source / drain regions 30a and 30b and the gate electrode 60, which are silicon exposed regions, and are deposited on the insulating layer 20 and the sidewall insulating layer 50 region where silicon is not present. The unreacted metal material 90 is removed by wet etching. As a solution used for wet etching to remove the unreacted metal material 90, a solution in which sulfuric acid and peroxide is mixed at a ratio of 1: 1 is preferably used.

The silicide is preferably heat-treated in the temperature range of 400 ℃ to 600 ℃.
When the gate electrode 60 uses metal instead of polysilicon, the nitride layer (silicon nitride) 70 is left, and the metal material is deposited thereon to form silicide. Thereafter, the unreacted metal material 90 is removed and the nitride film (silicon nitride) 70 is removed.

4 is a view showing the electrical characteristics measurement results of the erbium silicide Schottky diode fabricated on the silicon (100) surface and the silicon (111) surface, respectively.

Referring to Figure 4, the erbium silicide / silicon Schottky Barrier Height (SBH) is 0.39 V for the silicon (100) face and 0.31 V for the silicon (111) face. That is, the silicon 111 plane is lower by 0.08 V. If applied to the Schottky barrier transistor, it is expected that the characteristics of the transistor will be improved by increasing the ratio of the operating current and the off current.

In addition, the diode abnormality index (n) is 1.06 for the silicon (100) plane, and 1.03 for the silicon (111) plane, which is also closer to the ideal index of 1, which is also the silicon (111) plane.

As can be seen from the experimental results, it can be seen that the present invention can produce a more reliable and high-performance Schottky barrier through transistor.

As described above, the preferred embodiment of the present invention has been disclosed through the detailed description and the drawings. The terms are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the Schottky barrier through transistor and the manufacturing method thereof according to the present invention are a manufacturing process method that solves the problem of the N-type Schottky barrier through transistor having a low saturation current, which has been a problem in the past, By enabling the fabrication of high performance Schottky barrier through transistors, it is possible to present devices applicable in the future nano domain.

Claims (15)

Board; A source and a drain formed on the substrate; A channel formed between the source and the drain; A gate insulating film and a gate electrode sequentially formed on the channel; Sidewall insulating films formed on both sidewalls of the gate insulating film and the gate electrode Including, The interface between the source and the drain and the channel has a silicon (111) plane, and the silicon (111) plane, the source and the drain are silicided with a metal material to be a Schottky junction. Schottky Barrier Through Transistor. The method of claim 1, The height of the channel is formed higher than the height of the source and drain, the schottky barrier through transistor, characterized in that the interface has an inclined slope. delete The method of claim 1, And a insulating layer formed between the substrate and the source and drain. Patterning a SOI layer of a silicon on insulator (SOI) substrate to define a channel region, a source region and a drain region; Sequentially forming a gate insulating film, a gate electrode, and a nitride film on the channel region; Forming a sidewall insulating film on sidewalls of the gate insulating film, the gate electrode and the nitride film; Removing the nitride layer after forming a silicon (111) surface by performing anisotropic etching on the interface between the channel region, the source region and the drain region; Forming a Schottky junction interface in the channel region including the silicon (111) surface by depositing a metal material on the source region, the drain region, and the silicon (111) surface, and then suicide Schottky barrier through transistor comprising a. delete The method of claim 5, The impurity concentration of the semiconductor layer is 10 ¹⁷ cm ^-3 or less. The method of claim 5, And the gate insulating film is one of a silicon oxide film (SiO ₂ ), an aluminum oxide film (Al ₂ O ₃ ), and a hafnium oxide film (HfO ₂ ). The method of claim 5, And the gate electrode is made of any one of polysilicon, aluminum, and titanium (Ti). The method of claim 5, And the sidewall insulating film is a silicon oxide film (SiO ₂ ). delete The method of claim 5, The anisotropic etching is an anisotropic wet etching method using a KOH or tetra-methyl ammonium hydroxide (TMAH) Schottky barrier penetrating transistor manufacturing method. The method of claim 5, Forming the schottky junction interface further comprises removing a metal material that has not reacted to the silicide. The method of claim 5, The metal material may include a Schottky barrier through transistor made of one of erbium (Eb), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium (Ce). Way. The method of claim 5,  The silicide is a Schottky barrier through transistor manufacturing method characterized in that the heat treatment in the temperature range of 400 ℃ to 600 ℃.

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