KR20070059900A - Manufacturing schottky barrier mosfets with the schottky contact and manufacturing method thereof - Google Patents

Abstract

A schottky barrier tunnel transistor is provided to form a stable high-performance N-type schottky barrier tunnel transistor with a low schottky barrier with respect to electrons by forming a schottky junction on the (111) surface of a silicon by an anisotropic etch process. An insulation layer(20) is deposited on a substrate(10). A source/drain(30a,30b) is formed on the insulation layer. A channel(90) is formed between the source and the drain. A gate insulation layer(40) and a gate electrode(60) are sequentially formed on the channel. A sidewall insulation layer(50) is formed on both sidewalls of the gate insulation layer and the gate electrode. The interface of one of the source or drain and the channel has a (111) surface of silicon, and at least a part of the source/drain including the silicon (111) surface is silicidized by a predetermined metal material to be a schottky junction. The channel can be higher than the source/drain so that the interface has a slope.

Description

Schottky barrier MOSFETs and the method for manufacturing same Schottky barrier MOSFETs with the Schottky contact and manufacturing method

1 is a view showing the configuration of a Schottky barrier through transistor according to the prior art

2 is a diagram illustrating the configuration of a Schottky barrier through transistor according to the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a schottky barrier penetrating single electron transistor according to an embodiment of the present invention.

4 is a view showing the electrical characteristics measurement results of the erbium silicide Schottky diode fabricated on the silicon 100 surface and the silicon 111 surface, respectively

<Explanation of symbols for the main parts of the drawings>

10: substrate 20: insulating layer

30 semiconductor layer 30a source region

30b: drain region 40: gate insulating film

50 sidewall insulating film 60 gate electrode

70 polysilicon 80 nitride film

90 channel region 100 metal material

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a Schottky barrier through transistor and a method of manufacturing the same.

Semiconductor manufacturing technology has been advanced in the direction of low power, high integration, and high speed operation, and MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) has been miniaturized to satisfy these conditions. Integration over the last three decades has been well illustrated by Gordon Moore's law that the number of transistors on a chip doubles every 18 months. Thus, the current transistor has a gate length of less than 100 nm.

The International Technology Roadmap for Semiconductors (ITRS), published in 2003, predicts that the gate length of transistors will be 30 nm in 2005 and 10 nm in 2015.

However, when the transistor is small in size, it exhibits different characteristics from those of the conventional device. First, as the gate insulating layer becomes thinner, the thickness of the gate insulating layer is reduced, the leakage current due to the tunneling of electrons through the insulating layer, and the short channel effect. Increase, punch-through and the like occur. In addition, there are problems such as fluctuations in threshold voltage due to uneven distribution of impurities in the channel portion, and deterioration of the insulating film due to charge trapped in the insulating film due to the hot-carrier effect. The reliability is lowered.

Therefore, in order to fabricate and operate a transistor at a size predicted by the ITRS data, there are many problems to overcome in addition to the manufacturing technology.

One of these problems requires a shallow junction of source and drain to reduce the short channel effects described above. However, doping by ion implantation, which is generally used for source and drain formation, is not only difficult to control uniformly and shallowly, but also has a large sheet resistance corresponding to channel resistance.

In order to overcome these problems, researches are being conducted to replace insulating films, gates, sources and drains with new materials, and structural changes have been attempted.

One of them is a Schottky barrier through transistor, which makes the source and drain a silicide, a metal compound of silicon rather than doping, forming a Schottky barrier between the source, drain and channel.

1 is a view showing the configuration of a Schottky barrier through transistor according to the prior art.

As shown in FIG. 1, the insulating layer 20 formed on the substrate 10 and a predetermined region on the insulating layer 20 are separated into a channel region 90 and source / drain regions 30a and 30b. At least a portion of the source / drain regions 30a and 30b is formed of a semiconductor layer silicided with a predetermined metal to be schottky bonded to the channel region 90 and sequentially formed on the channel region 90. The gate insulating film 40 and the gate electrode 60, and the sidewall insulating film 60 formed on both sidewalls of the gate insulating film 40 and the gate electrode 60 are configured.

In this case, the semiconductor layer has a Schottky junction on the silicon 100 surface (which refers to silicon having an orientation index of 100 represented by the arrangement of atoms on the semiconductor surface depending on how the substrate is cut), and its barrier height to electrons is 0.4. V or less is obtained.

The Schottky barrier through-transistor is configured to control the leakage current by maintaining the height of the barrier. Since the source and the drain are metal, the Schottky barrier through transistor can be manufactured to have a small sheet resistance at a shallow junction. As such, the small sheet resistance of the source and drain of the Schottky barrier through transistor is a parasitic resistance of the transistor and affects the characteristics of the transistor including the operating speed. Therefore, the Schottky barrier through transistor is an element that is advantageous for miniaturization and integration as well as high speed.

In addition, as the size of the transistor becomes smaller, the thickness of the gate insulating layer 40 must be thinner to effectively lower the electric field of the channel due to the drain. However, as the gate insulating layer 40 becomes thinner, the leakage current of the gate electrode 60 increases, and thus research into replacing the conventional silicon oxide layer with a ferroelectric rare earth oxide material has been actively conducted.

In addition, the polycrystalline silicon gate has the advantage that the channel can control the work function according to the n-type or p-type, and the process itself is well known, and the yield can be increased. However, a depletion layer is formed at the interface of the polycrystalline silicon to thicken the insulating film and have a high resistance. Because of its shortcomings, it is being studied to be replaced by nitride gate or silicide gate.

Accordingly, since the Schottky barrier through transistor configured as shown in FIG. 1 makes the source / drain regions 30a and 30b into silicide, unlike the process of the conventional MOS field effect transistor, since the heat treatment is not necessary after the injection of impurities, 600 The process is performed at a low temperature of less than or equal to ℃, so it is also suitable to use a ferroelectric material as a silicide metal gate or an insulating film.

In this Schottky barrier through transistor, the Schottky junction of the metal silicide and the silicon interface occurs as an important factor depending on the performance. In other words, the Schottky barrier height during Schottky bonding depends on the impurities and interfacial states of interfacial silicon, the work function of silicides, the electron affinity of silicon, the metal-induced gap states, and the degree of lattice mismatch between metals and silicides.

Thus, transistors with low Schottky barriers have good operating or off-current characteristics, but on the contrary, high Schottky barriers increase resistance, resulting in lower operating currents and inflow of negative charges (holes for electrons in the N-type). As a result, the off current increases, which deteriorates the transistor characteristics.

As a result, forming a Schottky junction with a low Schottky barrier is an important part of Schottky transistor fabrication. Thus, to form such low Schottky barriers, silicides are made from metals such as erbium, ytterbium, yttrium, and samarium with low work functions in N-type Schottky barrier through transistors.

However, despite the use of materials with such low work functions, the actual Schottky barrier height is not easily controlled because it is affected by the other conditions listed above.

Accordingly, the present invention has been made to solve the above problems, and refers to the silicon 111 plane produced by anisotropic etching (the silicon having the direction index 111 represented by the arrangement of atoms on the semiconductor surface depending on how the silicon substrate was cut). The purpose is to fabricate a high performance N-type Schottky barrier through transistor having a Schottky junction in.) And having a low Schottky barrier for electrons.

A schottky barrier through transistor according to the present invention for achieving the above object is separated into a channel region and a source / drain region in a predetermined region on the substrate, the insulating layer is deposited, the channel region and At least a portion of the source / drain region, including the silicon 111 surface formed at the interface of the source / drain region, is formed of a semiconductor layer which is silicided with a predetermined metal to be schottky bonded to the channel region; And a sidewall insulating film formed on both sidewalls of the gate insulating film and the gate electrode.

In order to achieve the above object, a Schottky barrier through transistor manufacturing method according to the present invention is characterized in that the step of sequentially forming an insulating layer and a semiconductor layer on the substrate, and by patterning the semiconductor layer channel region, source / Defining a drain region, generating an silicon 111 plane through anisotropic etching of the interface between the channel region and the source / drain region, and forming a gate insulating film, a gate electrode, and a nitride film on the channel region having the silicon 111 surface. Forming a sidewall insulating film on both sidewalls of the gate insulating film, the gate electrode and the nitride film, removing the nitride film, and forming a metal material having a predetermined thickness on the entire upper surface of the resultant, Forming a Schottky junction interface in a channel region comprising a silicon 111 surface.

Preferably, the SOI substrate has a thickness of several nm to several tens of nm or less, and the semiconductor layer is formed in a thickness range of 1 nm to 20 nm.

Preferably the impurity concentration in the SOI substrate is 10 ¹⁷ cm ^- characterized by using a low concentration doping of the substrate ³ or less.

Preferably, the gate insulating film is formed of any one of a silicon oxide film (SiO ₂ ), an aluminum oxide film (Al ₂ O ₃ ), and a hafnium oxide film (HfO ₂ ).

Preferably, the gate electrode is made of one of polysilicon, aluminum, and titanium (Ti).

Preferably, the sidewall insulating film is formed of a silicon oxide film (SiO ₂ ).

Preferably, the gate electrode size and the width of the channel region are 10 nm or less.

Preferably, the anisotropic etching is characterized in that the wet etching isotropically using KOH or THAM (tetramethyl-ammonium-hydroxide).

Preferably, the forming of the Schottky junction interface further includes removing a metal material not reacted with the silicide.

Preferably, the metal material is formed of one of erbium, ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium (Ce). .

Preferably the silicide is characterized in that the heat treatment in the temperature range of 400 ℃ to 600 ℃.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

A preferred embodiment of a Schottky barrier through transistor and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings. Herein, silicon 111 refers to silicon having a direction index of 111 represented by the arrangement of atoms on the semiconductor surface depending on how the silicon substrate is cut. In the following specification, silicidation of silicon 111 refers to silicidation of silicon 111 by infiltrating a metal material into silicon 111.

2 is a diagram illustrating the configuration of a Schottky barrier through transistor according to the present invention.

As shown in FIG. 2, between the substrate 10 on which the insulating layer 20 is deposited, between the source / drain 30a and 30b formed on the insulating layer 20, and the source / drain 30a and 30b. A channel 90 formed on the sidewalls, the gate insulating film 40 and the gate electrode 60 sequentially formed on the channel 90, and sidewall insulating films formed on both sidewalls of the gate insulating film 40 and the gate electrode 60. It consists of 50. At this time, the interface between at least one of the source and drain 30a and 30b and the channel 90 has a silicon 111 surface, and includes at least one of the source and drain 30a and 30b including the silicon 111 surface. A portion is silicided with a predetermined metal material to be a Schottky junction.

The height of the channel is formed to be higher than the height of the source and drain, so that the interface has an inclined surface. And silicon 111 silicide at the inclined surface.

In addition, the substrate 10 preferably has a thickness of about 50 nm or less so that the gate electrode 60 efficiently controls the electric field of the channel region 90 to suppress leakage current. It is preferable to use an SOI substrate, but it is not limited to an SOI substrate, and the bulk silicon substrate can be produced in the same manner by applying the technical details described later. On the other hand, if a Schottky barrier through transistor is fabricated vertically using a silicon 111 substrate, a Schottky junction is formed directly on the silicon 111 surface and thus can be directly applied.

A method of manufacturing a Schottky barrier through transistor according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing a schottky barrier penetrating single electron transistor according to an embodiment of the present invention.

First, as shown in FIG. 3A, a silicon substrate 10 for mechanical support is formed at a lowermost portion of the SOI substrate, and an insulating layer 20 and a semiconductor layer 30 are sequentially formed thereon. The semiconductor layer 30 is patterned by leaving an active region in which a channel, a source, and a drain are to be formed using a predetermined etching mask (not shown).

At this time, the SOI substrate is preferably manufactured in a thickness range of several nm to several tens nm or less so that the gate electrode 60 can efficiently control the electric field of the channel region 90 to suppress leakage current. In addition, the semiconductor layer 30 is preferably formed in a thickness range of about 20 nm or less (preferably about 1 nm to 20 nm) to reduce the capacitance of the channel region 90 to be used as the quantum dot of the single-electron transistor.

And the impurity concentration of the SOI substrate is 10 ¹⁷ cm ^- uses a low-concentration doped substrate of ³ or less.

Next, as shown in FIG. 3B, a nitride film (silicon nitride) for depositing a gate insulating film 40 and a polysilicon 70 in a predetermined region on the semiconductor layer 30 and protecting the polysilicon 70 thereon ( 80) form sequentially. After the patterning is performed using an etching mask such as a photoresist, dry etching is performed to etch the gate insulating film 40, the polysilicon 70, and the nitride film 80.

In this case, the gate insulating layer 40 may use a silicon oxide film (SiO ₂ ) formed by thermally oxidizing silicon in a general case, and in order to use a higher gate electric field effect, an aluminum oxide film (Al ₂ O ₃ ) or hafnium may be used. It is also possible to use a high dielectric constant thin film such as an oxide film (HfO ₂ ). In addition, polysilicon, which is currently widely used as the material used as the polysilicon 70, may be used, and metals such as aluminum and titanium (Ti) may be used to further improve the performance of the Schottky barrier penetrating single-electron transistor (SB-SET). It is also possible to use substances.

3C, sidewalls formed on sidewalls of the gate insulating layer 40, the polysilicon 70, and the nitride layer 80 to prevent electrical connection when the silicide is formed on the source and drain and the polysilicon 70. After depositing a sidewall spacer, the sidewall insulating film 50 is formed on sidewalls of the gate insulating film 40, the polysilicon 70, and the nitride film 80 by etching by dry etching.

At this time, the material used as the sidewall insulating film 50 is preferably a material having a low dielectric constant, a typical one is an insulating film composed of a silicon oxide (SiO ₂ ) material. In addition, in order to manufacture a single-electron transistor having good characteristics, it is preferable to manufacture both the gate electrode size and the channel width to about 10 nm or less.

Next, as shown in FIG. 3D, an interface between the source / drain region 30a (see FIG. 2) (30b, FIG. 2) and the channel region 90 (see FIG. 2) using KOH or THAM (tetramethyl-ammonium-hydroxide) is used. Was anisotropically wet etched to produce a silicon 111 side. At this time, it may be produced using suitable conditions of dry etching.

Through such etching, the source / drain region has a height lower than that of the channel region, and thus the interface has an inclined slope.

3E, the nitride film (silicon nitride) 80 left to protect the polysilicon 70 is removed through wet etching or dry etching, and the entire upper surface of the resultant including the silicon 111 surface is removed. A metal material 100 of a predetermined thickness is deposited on the substrate.

In this case, the solution used in the wet etching may use a solution having a higher selectivity than the sidewall insulating film 50, thereby minimizing damage to the sidewall insulating film 50 due to the wet etching. In addition, it is preferable to use erbium, ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium (Ce) as the metal material 100. Do.

Finally, as shown in FIG. 3F, the resultant including the silicon 111 surface on which the metal material 100 having a predetermined thickness is deposited is heat-treated by a rapid thermal treatment (RTA) device to form silicide. Accordingly, the semiconductor layer 30 is divided into a channel region 90 and a source / drain regions 30a and 30b having a silicon 111 surface at an interface, and at least of the source / drain regions 30a and 30b. A portion is silicided with a predetermined metal material 100 to be in Schottky junction with the channel region 90.

In this case, the silicide reacts with the silicon only to the source / drain regions 30a and 30b and the polysilicon 70, which are the regions where the silicon is exposed, to have a Schottky junction interface, and the insulating layer 20 where the silicon is not present. The unreacted metal material 100 deposited on the sidewall insulating film 50 region is removed by wet etching. As a solution used for wet etching to remove the unreacted metal material 100, it is preferable to use a solution in which sulfuric acid and peroxide are mixed at a ratio of 1: 1.

 The silicide is preferably heat-treated in the temperature range of 400 ℃ to 600 ℃.

4 is a view showing the electrical characteristics measurement results of the erbium silicide Schottky diode fabricated on the silicon 100 surface and the silicon 111 surface, respectively.

Referring to FIG. 4, the Schottky Barrier Height (SBH) is 0.39 V for the 100 silicon side and 0.31 V for the 111 silicon side. In other words, the silicon 111 plane is as low as 0.08V. If applied to a Schottky barrier transistor, it is expected that the characteristics of the transistor will be improved by increasing the ratio of the operating current to the off current.

In addition, the diode anomaly index (n) is 1.06 for the silicon 100 surface, and 1.03 for the silicon 111 surface, which is also closer to the ideal index 1 of the silicon 111 surface.

As can be seen from the experimental results, it can be seen that the present invention can produce a more reliable and high-performance Schottky barrier through transistor.

As described above, the preferred embodiment of the present invention has been disclosed through the detailed description and the drawings. The terms are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the Schottky barrier through transistor and the manufacturing method thereof according to the present invention are a manufacturing process method that solves the problem of the N-type Schottky barrier through transistor having a low saturation current, which has been a problem in the past, By enabling the fabrication of high performance Schottky barrier through transistors, it is possible to present devices applicable in the future nano domain.

Claims (15)

A substrate on which an insulating layer is deposited, A source / drain formed on the insulating layer; A channel formed between the source / drain, A gate insulating film and a gate electrode sequentially formed on the channel; And a sidewall insulating film formed on both sidewalls of the gate insulating film and the gate electrode, The interface between at least one of the source and the drain and the channel has a silicon 111 surface, and at least a portion of the source and the drain, including the silicon 111 surface, are silicided with a predetermined metal material to be a Schottky junction. Schottky barrier through transistors. The method of claim 1, The height of the channel is formed higher than the height of the source and drain, the schottky barrier through transistor, characterized in that the interface has an inclined slope. The method of claim 1, And the substrate is configured to have a thickness of 50 nm or less. The method of claim 1, And the substrate is one of an SOI substrate and a bulk silicon substrate. Sequentially forming an insulating layer and a semiconductor layer on the substrate, Patterning the semiconductor layer to define a channel region and a source / drain region; Anisotropic etching the interface between the channel region and the source / drain region to form a silicon 111 surface; Forming a gate insulating film, a gate electrode and a nitride film on the channel region having the silicon 111 surface; Forming a sidewall insulating film on both sidewalls of the gate insulating film, the gate electrode and the nitride film, and removing the nitride film; Forming a schottky junction interface in a channel region including a silicon 111 surface by forming a metal material having a predetermined thickness on the entire upper surface of the resultant, and then suicided. The method of claim 5, And the SOI substrate has a thickness of several nm to several tens of nm or less, and the semiconductor layer is formed in a thickness range of 1 nm to 20 nm. The method of claim 6, Schottky barrier through transistor manufacturing method using a low concentration doping of the substrate ^{3 under-impurity} concentration of the SOI substrate is 10 ¹⁷ cm. The method of claim 5, And the gate insulating film is one of a silicon oxide film (SiO ₂ ), an aluminum oxide film (Al ₂ O ₃ ), and a hafnium oxide film (HfO ₂ ). The method of claim 5, And the gate electrode is made of any one of polysilicon, aluminum, and titanium (Ti). The method of claim 5, And the sidewall insulating film is a silicon oxide film (SiO ₂ ). The method of claim 5, And a gate electrode size and a width of a channel region of 10 nm or less. The method of claim 5, The anisotropic etching is an anisotropic wet etching method using KOH or THAM (tetramethyl-ammonium-hydroxide) Schottky barrier penetrating transistor manufacturing method. The method of claim 5, Forming the schottky junction interface further comprises removing a metal material that has not reacted to the silicide. The method of claim 5, The metal material may include a Schottky barrier through transistor made of one of erbium, ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium (Ce). Way. The method of claim 5,  The silicide is a Schottky barrier through transistor manufacturing method characterized in that the heat treatment in the temperature range of 400 ℃ to 600 ℃.

Images