CN1868045A - Schottky-barrier MOSFET manufacturing method using isotropic etch process - Google Patents

Schottky-barrier MOSFET manufacturing method using isotropic etch process Download PDF

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Publication number
CN1868045A
CN1868045A CNA200480028742XA CN200480028742A CN1868045A CN 1868045 A CN1868045 A CN 1868045A CN A200480028742X A CNA200480028742X A CN A200480028742XA CN 200480028742 A CN200480028742 A CN 200480028742A CN 1868045 A CN1868045 A CN 1868045A
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semiconductor substrate
etch rate
schottky
vertical
gate electrode
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J·P·斯奈德
J·M·拉森
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Spinnaker Semiconductor Inc
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Spinnaker Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the metal source-drain contacts to provide better control of the Schottky-barrier junction location to a charmel region. The improvements from the controllability of the placement of the Schottky-barrier 10 junction enables additional drive current and optimizes device performance, thereby significantly improving manufacturability.

Description

Use the Schottky-barrier MOSFET manufacturing method of isotropic etching
The cross reference of related application
The application requires the priority of the 60/509th, No. 142 U.S. Provisional Patent Application of proposition on October 3rd, 2003, and is included in this by reference.
Technical field
The present invention relates to be applicable to the semiconductor device of adjusting current flow, and the manufacturing of these devices in the category of integrated circuit (IC) is had specific application.The invention particularly relates to and be applicable to the transistor of adjusting current flow, this transistor has metal source and/or the drain electrode that forms Schottky or class Schottky contacts with channel region.
Background technology
A kind of well-known transistor is Schottky barrier metal oxide semiconductor field effect transistor (" Schottky-barrier MOSFET (Schottky-barrier MOSFET) " or SB-MOS) in this area.As shown in Figure 1, SB-MOS device 100 comprises Semiconductor substrate 110, has formed source electrode 120 and drain electrode 125 on this substrate, and the channel region 140 that both are had a channel dopant separately.Channel region 140 is electric current process zones of substrate 110.For the purposes of the present invention, the channel region in Semiconductor substrate 110 140 extends to the border of aiming at substantially with the bottom margin of the bottom margin of source electrode 120 and drain electrode 125 from the vertical lower of gate insulator 150.Channel dopant generally all has maximum impurity concentration 115, and therefore this be the outside at channel region 140 normally below source electrode 120 and drain electrode 125 electrodes.
For the SB-MOS device, source electrode 120 is with at least one some or all ofly is made of metal silicide during drain electrode 125 contacts.At least one is made of part metals in contacting because source electrode 120 is with drain electrode 125, so just formed contacting of Schottky or class Schottky with substrate 110 and channel region 140.Schottky contacts can be defined as the formed contact of tight contact between metal and semiconductor, and the class Schottky contacts can be defined as formed contact of close contact of semiconductor and metal.Schottky contacts or class Schottky contacts just can be provided or tie 130 and 135 with drain electrode 125 by form source electrode 120 by metal silicide.The length of raceway groove can be defined as touching drain electrode 125 contact, laterally cross over the distance of channel region 140 from source electrode 120.
Schottky contacts or class Schottky contacts or tie 130 and 135 and be in source electrode 120 and drain between 125 in formed channel region 140 adjacent areas.Insulating barrier 150 is in the top of channel region 140.Insulating barrier 150 is made of the material such as silicon dioxide.Channel region 140 extends perpendicularly to the bottom of source electrode 120 and drain electrode 125 electrodes from insulating barrier 150.Gate electrode 160 is positioned at the top of insulating barrier 150, and thin insulating barrier 170 is around gate electrode 160.Thin insulating barrier 170 is also referred to as insulation spacer.Gate electrode 160 can be the polysilicon that mixes up.Source electrode 120 and drain electrode 125 electrodes can be in insulation spacer 170 and 160 times horizontal expansions of gate electrode.Field oxide 190 can be with the mutual electrical property insulation of device.In the 6th, 303,479 United States Patent (USP)s of Spinnaker, disclosed a kind of typical schottky barrier device.
Therefore, need to be applicable to the manufacture method of SB-MOS in industry, this method can provide to be had improved performance, is convenient to make and SB-MOS with low cost.
Summary of the invention
On the one hand, the invention provides the method for a kind of manufacturing Schottky-barrier MOSFET (" SB-MOS ") device, wherein, at least one is made of metal source electrode in contacting with drain electrode, thereby the method that can a kind ofly make is controlled the setting of metal source and/or drain region.In another aspect of this invention, adopt the setting of local isotropic etching control metal source and/or drain region.
Though disclosed a plurality of embodiment, for the skilled artisan of this area, from following demonstration with discussed the detailed description of explanation embodiment illustrated in the present invention, other embodiments of the invention will become apparent.As recognizing, under the situation that does not break away from the spirit and scope of the present invention, the present invention can improve in all many-sides.Therefore, accompanying drawing and detailed description can think only just unrestricted from describing in essence.
Description of drawings
Fig. 1 shows the profile of existing Schottky barrier metal oxide semiconductor field effect transistor (" Schottky-barrier MOSFET " or " SB-MOS ");
Fig. 2 shows the exemplary embodiment of the present invention of using Semiconductor substrate to realize technology;
Fig. 3 shows the exemplary embodiment of the present invention of the patterned silicon film technology of use on thin gate insulator;
Fig. 4 shows and uses the exemplary embodiment of the present that forms thin insulator sidewall and be exposed to the technology of the silicon in grid, source electrode and the drain region;
Fig. 5 shows the exemplary embodiment of the present invention of using local isotropic etching; And,
Fig. 6 shows the exemplary embodiment of the present invention of using metal deposition, silicidation anneal and removing unreacted metal technology.
Embodiment
In general, the invention provides the method for making the SB-MOS device.In one embodiment of the invention, the method for manufacturing SB-MOS device comprises provides Semiconductor substrate and doped semiconductor substrate and channel region.This method also comprises provides the electrical property that contacts with Semiconductor substrate insulating barrier.This method also comprises the gate electrode that is provided on the insulating barrier, the thin insulating barrier around gate electrode is provided, and exposes substrate near the one or more zones the gate electrode.This method also comprises uses local isotropic etching with near the institute's area exposed etching grid electrode.This method also comprises the deposit film metal and metal and the substrate that is exposed is reacted, thereby form metal silicide on substrate.This method also comprises removes any unreacted metal.
One of advantage of the present invention is that the metal source that provided and drain electrode can significantly reduce parasitic series resistance (~ 10 Ω-μ m) and contact resistance (less than 10 -8Ω-cm 2).Embedded Schottky barrier on Schottky contacts provides the good control to off-state leakage current.This device has been eliminated parasitic bipolar action basically, makes it can unconditionally exempt locking, rebound effect in memory and logic and the soft error of multiple unit.Eliminate the generation that bipolar action has also reduced other adverse effect relevant with parasitic bipolar action significantly, for example, the soft error of the upset of single incident and single unit.Device of the present invention is made easily, only needs to be used for the less mask of two covers that source/drain forms, and does not need shallow-layer diffusion or deep layer source/drain to inject, and only adopts the low temperature source/drain to form technology.Owing to adopt low temperature process, thus just can novel, the potential critical materials of easier formation such as high-K gate insulator, Silicon-rich and metal gates integrated.
Fig. 2 has shown that silicon substrate 210 and it have the means that are applicable to the mutual electrical property insulation of transistor.By the discussion of this paper, provide a kind of example that is considered to make the Semiconductor substrate of SB-MOS device in the above.The present invention is not limited to any special type with Semiconductor substrate.The person skilled in the art recognizes that easily many Semiconductor substrate can be applied to the SB-MOS device, comprises, for example, silicon, germanium silicon, GaAs, indium phosphide, rich Semiconductor substrate and silicon-on-insulator (SOI).These backing materials and any other Semiconductor substrate can be used and all in technical scope of the present invention.
As shown in Figure 2, the thin screen oxide 220 of growth on substrate 210 is as the mask that injects.In one embodiment, oxide growth is to the thickness that is about 200 .Subsequently, suitable channel dopant species 230 is injected by the screen oxide ion, thereby provides maximum impurity concentration 240 to desired depth D1 250 in the silicon.In one embodiment, for P type device, channel dopant species is an arsenic, and for N type device, then channel dopant species is an indium.Yet, should be understood that, according to the principle of the invention,, can use any channel dopant species that other is fit to commonly used in transistor to P type or N type device.In another embodiment, the profile of channel doping density has obvious variation in vertical direction, and all is constant usually in a lateral direction.In another embodiment, the depth D 1 250 of maximum impurity concentration is about 20 to 200nm.
As shown in Figure 3, subsequently, adopt the mode of chemical etching to remove screen oxide, and the thin gate insulator 310 of growth such as silicon dioxide.In one embodiment, the screen oxide etching comprises hydrofluoric acid.Yet, according to the principle of the invention, also can use any other to be usually used in the chemical method that etching oxide is suitable for, comprise wet method and dry-etching.In another embodiment, Bao gate insulator comprises the silicon dioxide of about 6 to 50  thickness.In another embodiment, provide the have high-k material of (high K).The example of hafnium is the materials of those dielectric constants greater than the dielectric constant of silicon dioxide, comprises, for example, silicon oxynitride (nitrided silicon dioxide), silicon nitride and such as TiO 2, Al 2O 3, La 2O 3, HfO 2, ZrO 2, CeO 2, Ta 2O 5, WO 3, Y 2O 3And LaAlO 3Metal oxide or the like.Begin growth immediately by gate insulator after the silicon thin film that original position mixes up is provided.This film is heavily to mix up, and for example, N type device is adopted phosphorus, and P type device is adopted boron.Use photoetching technique and etch techniques, the figure that gate electrode 320 constitutes shown in the processing step among Fig. 3 300.In one embodiment, after gate electrode is graphical, provide other channel dopant, make the channel doping density profile on vertical and horizontal both direction, obvious variation take place all.
As shown in Figure 4, on the upper surface 425 of silicon gate electrode 320 and sidewall 410, provide thin insulator.In one embodiment, Bao insulator is the thermal growth oxide that thickness is approximately 50 to 500 .In another embodiment, by adopting rapid thermal oxidation (RTO) technology, its have the duration be 0.0 to 60 second 900 degree Celsius to the maximum temperatures of 1200 degree, provide the heat growth thin oxide.Those skilled in the art recognize have many manufacture methods can be used to the insulating barrier that provides thin easily, for example, and deposition process.Those skilled in the art also will recognize, can use other material as thin insulator, for example, and nitride, and insulating barrier can comprise multiple insulating material.Subsequently, can use the insulating barrier (and expose silicon 420 and 425) of isotropic etching removal on horizontal surface, thereby expose horizontal surface, be retained in the insulating barrier on the vertical surface simultaneously.Like this, just formed side wall insulator 410.Those skilled in the art will be understood that 410 pairs of isotropic etchings of gate electrode 320 and side wall insulator have the function of mask, make on silicon substrate work in the thin insulating barrier and gate electrode 320 operation class seemingly.In one embodiment, Bao insulator is approximately 50 to 500 .Work in thin insulating barrier will with to the operation class of gate electrode 320 seemingly, and in the scope of about 50 to 500  of the lateral separation that departs from gate electrode 320.In one exemplary embodiment, the recessed 1nm that is approximately to the bottom of gate insulator of silicon face 420 is to the about depth D 2 430 of 5nm.In one exemplary embodiment, adopt RTO technology, side wall insulator is provided, can when side wall insulator forms, activate by electrical property at device grids electrode and the impurity in channel region, shown in the processing step among Fig. 4 400.
As shown in Figure 5, the horizontal and vertical etching Semiconductor substrate of the second etch process step.This etching is referred to as local isotropic etching.In one embodiment, use lateral etch rate to be at least the local isotropic etching of vertical etch rate 10%.In another embodiment, use vertical etch rate to be at least the local isotropic etching of lateral etch rate 10%.Second etched depth is D3510.The vertical sidewall that lateral etches is exposed Semiconductor substrate 520 from the edge of side wall oxide 410 with the lower position of distance L 1 530 transverse shifts to gate electrode 320.Because etching is local isotropic, so L1 can be less than or equal to ten times of D3, or D3 can be less than or equal to ten times of L1.In another embodiment, use lateral etch rate to approximate the etching of vertical etch rate greatly.In this embodiment, D3 can approximate L1 greatly.In also having an embodiment, adopt SF6 dry-etching, HF:HNO 3Any or its combination in the wet etching or be applicable to that any wet method or dry-etching that the etching semiconductor material is used always provide local isotropic etching.
As shown in Figure 6, next step comprises that the deposition proper metal is as the cover film on all exposed surfaces.Can adopt sputter or evaporation technology or other any film shaped technology commonly used that deposition is provided.In one embodiment, in the process of metal deposition, substrate heats, and the metallic atom that is clashed into to impel is diffused in institute's exposed silicon surface 520 under the gate insulator.In one embodiment, about 250  are thick for this metal, but it is thick to be typically about 50 to 1000 .Though discuss here, also can provide more example with the class Schottky barrier with contacting in fact with reference to relevant Schottky in IC makes.The present invention does not approve in any restriction that influences spendable schottky interface type aspect the scope of the invention.So the present invention expects to adopt any type of electric conducting material or alloy to create this class contact especially.For example, for P type device, metal source and drain electrode 610 and 620 electrodes can be made by any or its combination in platinum silicide, palladium silicide, the silication iridium.For N type device, metal source and drain electrode 610 and 620 can be made by being selected from the rare earth silicide family material that comprises such as silication erbium, silication dysprosium or ytterbium silicide or its combination.It should be understood that and also can use at transistor level any metal that other is suitable for commonly used, for example, titanium, cobalt or the like, and more external metal and other alloy.In another embodiment, silicided source/drain electrode can adopt the multiple layer metal silicide to make, and in this case, can use other the typical silicide such as titanium silicide or tungsten silicide.
Subsequently, wafer is continued special time anneal under specific temperature, make that metal all directly contacts with silicon on all positions, produce chemical reaction metallic transition is become metal silicide 610,620 and 630.In one embodiment, for example, wafer can continue about 45 minutes annealing under 400 degree approximately Celsius, perhaps continue about 1 to 120 minute annealing usually under 300 to 700 degree Celsius.Still keep unreacted with the metal that non-silicon face such as gate lateral wall spacer 410 directly contacts, and therefore and not influence.
Subsequently, use wet chemical etch,, keep untouchable metal silicide simultaneously to remove unreacted metal.In one embodiment, use chloroazotic acid to remove platinum, use HNO 3Remove erbium.It should be understood that within the scope of the invention, be applicable to any etch chemistry that other is suitable for that etching platinum or erbium are used always or be applicable to that formation Schottky or employed any other suitable metal system of class Schottky contacts can use.Now, just finished raceway groove injection, short channel SB-MOS device, and prepared to be used for grid 320, source electrode 610 and 620 the electrical property of draining is connected, shown in the processing step among Fig. 6 600.
The result of this illustrative processes has formed Schottky or class Schottky contacts respectively to channel region 540 and substrate 210, and wherein, Schottky contacts is positioned on the position that local isotropic etching controls.In one embodiment, source electrode 610 and drain electrode 620 electrodes laterally are positioned at the below of spacer 410 with the interface 520 of channel region 540 and aim at the edge on gate electrode 640 each limit.In another embodiment, the interface 520 of source electrode 610 and drain electrode 620 electrodes and channel region 540 laterally is positioned at the below of spacer 410 and part below gate electrode 320.In also having an embodiment, between each edge, limit of the interface 520 of source electrode 610 and drain 620 electrodes and channel region 540 and gate electrode 620, formed the gap.
Though the traditional schottky contact is precipitous, the special expectation of the present invention can be used boundary layer under certain conditions between silicon substrate and metal.These boundary layers can be ultra-thin, and the thickness that is had is approximately 10nm or less than 10nm.So the present invention is desirably in especially and realizes in the process of the present invention that class Schottky contacts and equivalent thereof are very useful.In addition, boundary layer can be made of the material with conduction, semiconductive and/or class insulation characterisitic.For example, can use oxide or nitride insulator ultra-thin interfacial layer, can use by mix up the formed ultra-thin doped layer of isolation technology or, can be used between them, form the class Schottky contacts such as the semi-conductive ultra-thin interfacial layer of germanium.
An important performance characteristic of SB-MOS device is drive current (I d), that is, and as the source voltage (V that is applied s) ground connection and grid voltage (V g) and drain voltage (V d) with supply voltage (V Dd) during bias voltage, flow to the electric current of drain electrode from source electrode.Another important feature of SB-MOS device is total grid capacitance (C g), that is, and by such as determined total electric capacity of various electric capacity such as gate insulator 310, fringing field electric capacity and overlap capacitances.Drive current and total grid capacitance are two key parameters of decision-making circuit performance.For example, transistorized switching speed can be demarcated and is I d/ C g, that is, the big and total more grid capacitance of drive current is more little, and then the switching speed of device is just fast more, thereby has more high performance integrated circuit.Have many variablees can influence the drive current of SB-MOS device and total grid capacitance, comprise, for example, as shown in Figure 6, Schottky or class Schottky contacts 520 are with respect to the lateral attitude of gate electrode 640.
In the SB-MOS device, drive current is normally by the tunnel current density (J by Schottky barrier intake duct raceway groove SB) determined, it is subjected at source electrode and the grid induction electric field (E of channel region interface place s) strong control.Along with the voltage (V that is applied to grid g) increase, E sAlso increase thereupon.The E that is increased sChange Schottky barrier, made J SBRoughly increase according to formula (1), this has shown J SBWith E sBecome the power exponent sensitivity, A and B are constants in the formula, and J SBAnd E sUnit be respectively (A/cm 2) and (V/M).
J SB = Ae ( - B E S )
Except V g, E sAlso be subjected to approaching the strong influence of the schottky barrier-channel region interface 520 at gate electrode 640 edges.When interface 520 is not below gate electrode 320, E sAnd J SBAnd I dObviously descend and laterally continue to descend away from the edge 640 of gate electrode along with the interface.Therefore, the invention provides a kind of method of the SB-MOS of manufacturing device, this method allows to adopt local isotropic etching technology accurately to control Schottky or class schottky source and the drain region position with respect to gate electrode.Technology of the present invention provides a kind of maximization electric field E sWith drive current I dAnd the method for optimized device performance.
With regard to total grid capacitance C g, interface 520 is the function of designs and the demand of performance with respect to the optimum position at gate electrode edge 640.Particularly, total grid capacitance C gAlong with the distance between interface 520 and gate electrode edge 640 increases and reduces, simultaneously, also it should be noted that drive current I dAlso reduce simultaneously.Optimization in Properties need be at drive current I dWith total grid capacitance C gBetween carry out tradeoffs, this just makes technology of the present invention can provide better controlled.For example, use local isotropic etching technology of the present invention, the position of interface 520 with respect to gate electrode edge 640 can be provided, make grid capacitance C gWith drive current I dThe tradeoffs optimization.
Use technology of the present invention, can produce following benefits thereupon, but not limit therewith.The first, local isotropic etch step provides the additional production control of the exact position that Schottky under gate electrode or class Schottky contacts be provided with.Therefore Schottky that is produced or class Schottky contacts position can controllably be placed on the lateral attitude of gate electrode below, so that drive current maximum, total grid capacitance minimum and device performance optimum.Second benefit is the below by the etching grid electrode, can reduce the length of effective raceway groove.Be understandable that channel length is short more just further to increase drive current.
The present invention is particularly useful for using under the situation of the MOSFET that makes short channel length, particularly, uses under the situation of channel length less than 100nm.Yet restriction is not applied to short channel length devices with instruction of the present invention in instruction of the present invention.Instruction of the present invention has obtained good application in the channel length of virtually any size.
Although with reference to preferred embodiment the present invention has been discussed, those skilled in the art will appreciate that, can carry out various variations under the conditions without departing from the spirit and scope of the present invention in form and details.The present invention can be applied to multiple raceway groove, substrate and trap and inject profile.The present invention is applicable to any use of metal source and drain technology, no matter is to adopt SOI substrate, strained silicon substrate, SiGe substrate, FinFET technology, high-K gate insulator and metal gates.This enumerates not restriction.Any device that flows that adopts metal source-drain electrode contact to adjust electric current all will have the benefit that this paper teaches.
Yet the present invention is specially adapted to the SB-MOS semiconductor device and uses, and it also can be used for other semiconductor device.Therefore, although this specification has been described the employed manufacturing process of SB-MOS, but these contents also should be broadly understood and comprise any device, if this device be used to adjust have the contact of 2 or multiple spot electrical property and wherein at least one electrical property contact be that the electric current of the conducting channel of Schottky or class Schottky contacts flows.

Claims (25)

1. a manufacturing is used to adjust the method for the device of the magnitude of current, and this method comprises:
The preparation Semiconductor substrate;
On described Semiconductor substrate, prepare gate electrode;
In approaching the zone of described gate electrode, expose described Semiconductor substrate;
Use local isotropic etching that described Semiconductor substrate is etched on the described exposed region;
Depositing metal films in the etching area of described Semiconductor substrate; And,
Metal and the reaction of described substrate are to form Schottky or class schottky source electrode or drain electrode.
2. the method for claim 1 is characterized in that, described Semiconductor substrate is made of silicon, Silicon-rich, silicon-on-insulator, SiGe, GaAs or indium phosphide.
3. the method for claim 1 is characterized in that, it approximately is that 1/10 to 10 times etching of vertical etch rate is carried out that described etching step is to use lateral etch rate.
4. the method for claim 1 is characterized in that, described local isotropic etching comprises the vertical etch rate of Semiconductor substrate and the lateral etch rate of Semiconductor substrate, and wherein, vertical etch rate approximately is 10 times of lateral etch rate.
5. the method for claim 1 is characterized in that, described local isotropic etching comprises the lateral etch rate of Semiconductor substrate and the vertical etch rate of Semiconductor substrate, and wherein, lateral etch rate approximately is 10 times of vertical etch rate.
6. the method for claim 1 is characterized in that, described local isotropic etching comprises the lateral etch rate of Semiconductor substrate and the vertical etch rate of Semiconductor substrate, and wherein, lateral etch rate and vertical etch rate are roughly the same.
7. the method for claim 1 is characterized in that, described gate electrode can adopt the following step preparation:
The thin insulating barrier of preparation on described Semiconductor substrate;
The conducting film of deposition of thin on described insulating barrier;
Described conductive film is carried out graphical and etching, to form gate electrode; And,
On one or more sidewalls of described gate electrode, form one or more thin insulating barriers.
8. the method for claim 1 is characterized in that, also is included in formation Schottky or class schottky source and drain electrode and removes unreacted metal from device afterwards.
9. the method for claim 1 is characterized in that, described reactions steps is undertaken by thermal annealing.
10. the method for claim 1 is characterized in that, described source electrode and drain electrode are formed by any or its combination in platinum silicide, palladium silicide, the silication iridium.
11. the method for claim 1 is characterized in that, described source electrode and drain electrode are formed by the rare earth silicon Chemistry and Physics Institute.
12. the method for claim 1 is characterized in that, described Schottky or class Schottky contacts are formed in the zone of the channel region vicinity under the gate electrode at least.
13. the method for claim 1 is characterized in that, at least one whole surface of described source electrode and drain electrode forms Schottky or the class Schottky contacts with described Semiconductor substrate.
14. the method for claim 1 is characterized in that, before the described gate electrode step of preparation, described Semiconductor substrate is introduced impurity, wherein the impurity in the channel region is made up of arsenic, phosphorus or antimony between source electrode and drain electrode.
15. the method for claim 1 is characterized in that, before the described gate electrode step of preparation, described Semiconductor substrate is introduced impurity, wherein the impurity in the channel region is made up of boron, indium or gallium between source electrode and drain electrode.
16. method as claimed in claim 14 is characterized in that, described Semiconductor substrate has marked change in vertical direction and at the substantially invariable channel doping density of horizontal direction.
17. method as claimed in claim 14 is characterized in that, described Semiconductor substrate has in vertical direction and channel doping density of marked change all in a lateral direction.
18. method as claimed in claim 15 is characterized in that, described Semiconductor substrate has marked change in vertical direction and at the substantially invariable channel doping density of horizontal direction.
19. method as claimed in claim 15 is characterized in that, described Semiconductor substrate has in vertical direction and channel doping density of marked change all in a lateral direction.
20. a manufacturing is used to adjust the method for the device of the magnitude of current, this method comprises:
In the gate electrode near zone, expose Semiconductor substrate;
Use local isotropic etching that described Semiconductor substrate is etched on the exposed region; And,
Deposition and thermal annealing film metal and described Semiconductor substrate are to form Schottky or class schottky source electrode or drain electrode.
21. method as claimed in claim 20 is characterized in that, described local isotropic etching comprises the vertical etch rate of Semiconductor substrate and the lateral etch rate of Semiconductor substrate, and wherein, vertical etch rate approximately is 10 times of lateral etch rate.
22. method as claimed in claim 20 is characterized in that, described local isotropic etching comprises the lateral etch rate of Semiconductor substrate and the vertical etch rate of Semiconductor substrate, and wherein, lateral etch rate approximately is 10 times of vertical etch rate.
23. method as claimed in claim 20 is characterized in that, described local isotropic etching comprises the lateral etch rate of Semiconductor substrate and the vertical etch rate of Semiconductor substrate, and wherein, lateral etch rate and vertical etch rate are roughly the same.
24. method as claimed in claim 20 is characterized in that, it approximately is that 1/10 to 10 times etching of vertical etching speed is carried out that described etching step is to use lateral etch rate.
25. method as claimed in claim 20 is characterized in that, described Semiconductor substrate is heated in the process of described deposition step, to promote that metallic atom diffuses into described Semiconductor substrate.
CNA200480028742XA 2003-10-03 2004-10-04 Schottky-barrier MOSFET manufacturing method using isotropic etch process Pending CN1868045A (en)

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