CN1868045A - Schottky-barrier MOSFET manufacturing method using isotropic etch process - Google Patents

Schottky-barrier MOSFET manufacturing method using isotropic etch process Download PDF

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CN1868045A
CN1868045A CN 200480028742 CN200480028742A CN1868045A CN 1868045 A CN1868045 A CN 1868045A CN 200480028742 CN200480028742 CN 200480028742 CN 200480028742 A CN200480028742 A CN 200480028742A CN 1868045 A CN1868045 A CN 1868045A
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semiconductor substrate
method according
etch rate
schottky
etching
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J·P·斯奈德
J·M·拉森
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斯平内克半导体股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66643Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact

Abstract

A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the metal source-drain contacts to provide better control of the Schottky-barrier junction location to a charmel region. The improvements from the controllability of the placement of the Schottky-barrier 10 junction enables additional drive current and optimizes device performance, thereby significantly improving manufacturability.

Description

使用各向同性蚀刻工艺的肖特基势垒MOSFET制造方法 Using an isotropic etching process of the manufacturing method of the Schottky barrier MOSFET

相关申请的交叉引用本申请要求2003年10月3日提出的第60/509,142号美国临时专利申请的优先权,并通过引用包括在此。 Cross-Reference to Related Applications This application claims priority to US Provisional Patent Application No. 60 / 509,142 October 3, 2003 proposed, and by reference herein.

技术领域 FIELD

本发明涉及适用于调整电流流量的半导体器件,并且对在集成电路(IC)的范畴内的这些器件的制造具有特定的应用。 The present invention relates to a semiconductor device suitable for adjusting the current flow, and has particular application in the context of manufacturing an integrated circuit (IC) of these devices. 本发明尤其涉及适用于调整电流流量的晶体管,该晶体管具有与沟道区域形成肖特基或者类肖特基接触的金属源极和/或漏极。 The invention relates especially adapted to adjust the flow of electrical current a transistor having a metal source and / or drain region and the channel forming the Schottky or Schottky-like contact.

背景技术 Background technique

本领域中一种众所周知的晶体管是肖特基势垒金属氧化物半导体场效应晶体管(“肖特基势垒MOSFET(Schottky-barrier MOSFET)”或者SB-MOS)。 One well known in the art a Schottky barrier transistor is a metal-oxide semiconductor field effect transistor ( "a Schottky barrier MOSFET (Schottky-barrier MOSFET)" or SB-MOS). 如图1所示,SB-MOS器件100包括半导体衬底110,在该衬底上形成了源极电极120和漏极电极125,并且两者被具有沟道杂质的沟道区域140分开。 As shown in FIG. 1, SB-MOS device 100 includes a semiconductor substrate 110, forming a source electrode and a drain electrode 120 on the substrate 125, and both are having a channel region of the channel 140 to separate impurities. 沟道区域140是衬底110的电流经过区域。 The channel region 110 of the substrate 140 is a current passing area. 为了本发明的目的,在半导体衬底110中的沟道区域140从栅极绝缘体150的垂直下方延伸至与源极电极120的底部边缘和漏极电极125的底部边缘基本对准的边界。 For purposes of the present invention, the channel region in the semiconductor substrate 110 to the boundary 140 extending bottom edge of the source electrode and the drain electrode 120 of the bottom edge 125 is substantially aligned vertically below the gate insulator 150. 沟道杂质一般都具有最大的杂质浓度115,这通常是在源极120和漏极125电极的下方,因此是在沟道区域140的外面。 Channel impurity generally have a maximum impurity concentration 115, which is typically below the source 120 and the drain electrode 125, and therefore is outside the channel region 140.

对于SB-MOS器件而言,源极120和漏极125接触中至少一个是部分或者全部由金属硅化物所构成的。 For the SB-MOS device, the source 120 and drain 125 contacts at least a partially or entirely of metal silicide is formed. 因为源极120和漏极125接触中至少一个是由部分金属所构成的,所以就与衬底110和沟道区域140形成了肖特基或者类肖特基的接触。 Since the source 120 and the drain electrode 125 contacts at least a portion of the metal is formed, it is formed a Schottky or Schottky-like contacts with the substrate 110 and the channel region 140. 肖特基接触可以定义成在金属和半导体之间的紧密接触所形成的接触,而类肖特基接触可以定义成半导体和金属的近距离接触所形成的接触。 Schottky contact can be defined in close contact with a contact formed between the metal and the semiconductor, and a Schottky contact may be defined in close contact to contact a metal and a semiconductor to be formed. 通过由金属硅化物形成源极120和漏极125就能提供肖特基接触或者类肖特基接触或者结130和135。 Formed by the metal silicide source 120 and drain 125 can provide a Schottky contact or Schottky-like contacts or junctions 130 and 135. 沟道的长度可以定义成从源极120的接触到漏极125的接触、横向跨越沟道区域140的距离。 The channel length can be defined as contact with the contact electrode 120 from the source to the drain 125, the lateral distance across the channel region 140.

肖特基接触或者类肖特基接触或者结130和135处于在源极120和漏极125之间所形成的沟道区域140相邻的区域内。 The area of ​​Schottky contact or Schottky-like contacts or junctions 130 and 135 in the channel region between the source electrode 120 and drain electrode 125 formed adjacent to 140. 绝缘层150处于沟道区域140的上方。 The insulating layer 150 located above the channel region 140. 绝缘层150是由诸如二氧化硅之类的材料所构成的。 Insulating layer 150 is a material such as silicon dioxide is formed. 沟道区域140从绝缘层150垂直延伸至源极120和漏极125电极的底部。 The channel region 140 extends vertically from the insulating layer 150 to the bottom of the source 120 and drain 125 electrodes. 栅极电极160定位在绝缘层150的上部,并且薄的绝缘层170环绕着栅极电极160。 160 is positioned in the upper portion 150 of the gate electrode insulating layer, and a thin insulating layer 170 surrounds the gate electrode 160. 薄的绝缘层170也称为绝缘隔离片。 A thin insulating layer 170 is also referred to as an insulating spacer. 栅极电极160可以是搀杂的多晶硅。 The gate electrode 160 may be doped polysilicon. 源极120和漏极125电极可以在绝缘隔离片170和栅极电极160下横向延伸。 The source 120 and drain 125 electrodes may extend laterally at the insulating spacer 170 and the gate electrode 160. 场氧化物190可以将器件相互电性能绝缘。 Field oxide 190 may be electrically insulating properties of the device. 在Spinnaker的第6,303,479美国专利中披露了一种典型的肖特基势垒器件。 It discloses a typical Schottky barrier devices of U.S. Patent No. 6,303,479 in Spinnaker.

因此,在产业中需要适用于SB-MOS的制造方法,该方法可提供具有改良性能、便于制造以及成本低廉的SB-MOS。 Thus, the industry needed a method for the manufacture of SB-MOS, the method may provide an improved performance, ease of manufacturing and low costs of the SB-MOS.

发明内容 SUMMARY

一方面,本发明提供一种制造肖特基势垒MOSFET(“SB-MOS”)器件的方法,其中,源极和漏极接触中至少一个是由金属所构成的,从而可以一种可制造的方法来控制金属源极和/或漏极区域的设置。 In one aspect, the present invention provides a method of manufacturing a Schottky barrier MOSFET ( "SB-MOS") device, wherein the source and drain contacts at least one of a metal composed, thereby producing an the method for controlling the metal source is provided and / or the drain region. 在本发明的另一方面,采用局部各向同性蚀刻控制金属源极和/或漏极区域的设置。 In another aspect of the present invention, an isotropic etching using a local source of metal and control settings / or drain region.

虽然披露了多个实施例,但是对于本领域的熟练技术人士来说,从以下显示和讨论了本发明所图示说明实施例的详细描述中,本发明的其它实施例将变得显而易见。 Although a plurality of embodiments are disclosed embodiment, but for those skilled in the art that from the following discussion and the illustrated display of the present invention described in the detailed description of embodiments, other embodiments of the present invention will become apparent. 正如所能认识到的那样,在没有脱离本发明的精神和范围的情况下,本发明可以在诸多方面进行改进。 As it can be appreciated that, without departing from the spirit and scope of the present invention, the present invention can be modified in many aspects. 因此,附图和详细描述可以认为仅仅只是从本质上进行说明而非限制。 Accordingly, the drawings and detailed description be considered merely illustrative and not restrictive in nature.

附图说明 BRIEF DESCRIPTION

图1示出了现有肖特基势垒金属氧化物半导体场效应晶体管(“肖特基势垒MOSFET”或者“SB-MOS”)的剖面图;图2示出了使用半导体衬底实现工艺的本发明的示例性实施例;图3示出了使用在薄的栅极绝缘体上的图形化硅薄膜工艺的本发明的示例性实施例;图4示出了使用形成薄的绝缘体侧壁,和暴露在栅极、源极和漏极区域中的硅的工艺的本发明示例性实施例;图5示出了使用局部各向同性蚀刻工艺的本发明的示例性实施例;以及,图6示出了使用金属沉积、硅化退火以及去除未反应的金属工艺的本发明的示例性实施例。 1 shows a cross-sectional view of a conventional Schottky barrier metal oxide semiconductor field effect transistor ( "the MOSFET Schottky Barrier" or "SB-MOS"); Figure 2 illustrates a process implemented using a semiconductor substrate exemplary embodiments of the present invention; FIG. 3 shows a patterning process using a silicon thin film on a thin gate insulator of an exemplary embodiment of the present invention; Figure 4 illustrates the use of a thin insulator sidewalls, and exemplary embodiments of the present invention in the process of exposing the gate, source and drain regions of the silicon; FIG. 5 illustrates an exemplary embodiment of the present invention using a local isotropic etch process; and, FIG. 6 It illustrates an exemplary embodiment of the present invention using a metal deposition, silicidation anneal, and removal of unreacted metal process.

具体实施方式 Detailed ways

一般来说,本发明提供了制造SB-MOS器件的方法。 In general, the present invention provides a method of manufacturing a SB-MOS device. 在本发明的一个实施例中,制造SB-MOS器件的方法包括提供半导体衬底和搀杂半导体衬底及沟道区域。 In one embodiment of the present invention, a method of manufacturing a SB-MOS device includes providing a semiconductor substrate and doping the semiconductor substrate and the channel region. 该方法还包括提供与半导体衬底接触的电性能绝缘层。 The method further comprises providing the electrical properties of the insulating layer in contact with the semiconductor substrate. 该方法还包括提供在绝缘层上的栅极电极,提供环绕着栅极电极的薄的绝缘层,以及在栅极电极附近的一个或多个区域上暴露衬底。 The method further includes providing a gate electrode on the insulating layer, providing a gate electrode surrounded by a thin insulating layer, and exposing the substrate on one or more regions near the gate electrode. 该方法还包括使用局部各向同性蚀刻工艺将蚀刻栅极电极附近所暴露的区域。 The method further comprises using an isotropic etching process locally etching the gate electrode to the vicinity of the exposed region. 该方法还包括沉积薄膜金属以及将金属与所暴露的衬底进行反应,从而在衬底上形成金属硅化物。 The method further includes depositing a metal thin film and the metal substrate is exposed with the reaction to form a metal silicide on a substrate. 该方法还包括去除任何未反应的金属。 The method further includes removing any unreacted metal.

本发明的优点之一是所提供的金属源极和漏极电极可显著减小寄生串联电阻(~10Ω-μm)和接触电阻(小于10-8Ω-cm2)。 One of the advantages of the present invention is a metal source and drain electrodes provide significantly reduced parasitic series resistance (~ 10Ω-μm) and a contact resistance (less than 10-8Ω-cm2). 在肖特基接触上的内嵌肖特基势垒提供了对截止状态泄漏电流的优良控制。 Embedded in the Schottky contact of the Schottky barrier provides superior control of off-state leakage current. 该器件基本上消除了寄生双极性作用,使得它能够无条件地免除在存储器和逻辑中的闭锁、反弹效应,以及多单元软误差。 The device substantially eliminates parasitic bipolar action, making it possible to dispense latch in the memory and logic, rebound effect, and multi-cell soft errors unconditionally. 消除双极性作用也显著地减小了与寄生双极性作用相关的其它不利效应的发生,例如,单一事件的翻转和单一单元的软误差。 Elimination of bipolar action also significantly reduces the occurrence of other adverse effects related to parasitic bipolar action, e.g., the soft error flip and a single unit of a single event. 本发明的器件容易制造,仅仅只需要用于源极/漏极形成的两套较少的掩模,不需要浅层扩散或者深层源极/漏极注入,并且只采用低温源极/漏极形成工艺。 Device of the present invention is easy to manufacture, it only requires two fewer masks for source / drain formation, no shallow or deep diffusion source / drain implant, and only a low temperature source / drain forming process. 由于采用低温工艺,所以就可以更容易形成诸如高K栅极绝缘体、富硅和金属栅极之类的新型、潜在的临界材料的集成。 As a result of low-temperature process, so it can be more easily form the novel, integrated potentially critical materials such as high K gate insulators, silicon-rich and a metal gate or the like.

图2显示了硅衬底210且它具有适用于晶体管相互电性能绝缘的手段。 Figure 2 shows the means suitable for electrically insulating properties and a transistor 210 having a silicon substrate. 通过本文的讨论,提供了一种被认为可以在上面制成SB-MOS器件的半导体衬底的实例。 By this discussion, it is considered to provide an example of a SB-MOS device can be made in the above semiconductor substrate. 本发明并没有将半导体衬底限制于任何特殊的类型。 The present invention is not limited to the semiconductor substrate to any particular type. 本领域熟练的技术人员容易意识到,许多半导体衬底都可以应用于SB-MOS器件,包括,例如,硅、锗硅、砷化镓、磷化铟、富半导体衬底和绝缘体上硅(SOI)。 Those skilled in the art will readily recognize that many may be applied to the semiconductor substrate SB-MOS device, including, for example, silicon, silicon germanium, gallium arsenide, indium phosphide, silicon-rich semiconductor substrate and the insulator (SOI ). 这些衬底材料和任何其它半导体衬底都可以使用并且都在本发明的技术范围内。 These substrate materials and any other semiconductor substrate may be used and are within the scope of the invention.

如图2所示,在衬底210上生长薄的屏蔽氧化物220,作为注入的掩模。 As shown, in growing a thin screen oxide 210 on the substrate 2202, as an implantation mask. 在一个实施例中,氧化物生长到约为200的厚度。 In one embodiment, the oxide is grown to a thickness of about 200. 随后,适当的沟道杂质种类230是通过屏蔽氧化物离子注入的,从而对硅中预定深度D1 250提供最大杂质浓度240。 Subsequently, suitable type channel impurity ion 230 is implanted through the screen oxide to provide the maximum impurity concentration D1 250 240 pairs of predetermined depth in the silicon. 在一个实施例中,对于P型器件来说,沟道杂质种类是砷,而对于N型器件来说,则沟道杂质种类是铟。 In one embodiment, for the P-type device, a channel impurity is arsenic species, and for N-type devices, the kind of the channel impurity is indium. 然而,应当理解的是,根据本发明原理,对P型或N型器件,可以使用在晶体管中常用的任何其它适合的沟道杂质种类。 However, it should be appreciated that, in accordance with the principles of the present invention, a P-type or N-type device, any kind commonly used in channel impurity other suitable transistors. 在另一实施例中,沟道杂质浓度的轮廓在垂直方向上有明显的变化,而在横向方向上通常都是恒定的。 In another embodiment, the impurity concentration of the channel profile there are significant changes in the vertical direction, and is generally in the transverse direction is constant. 在另一实施例中,最大杂质浓度的深度D1 250为大约20至200nm。 In another embodiment, the maximum impurity concentration in the depth D1 250 of about 20 to 200nm.

如图3所示,随后,采用化学蚀刻的方式去除屏蔽氧化物,并且生长诸如二氧化硅之类的薄的栅极绝缘体310。 3, followed by chemical etching manner screen oxide is removed, and the growth such as a thin silicon dioxide gate insulator 310. 在一个实施例中,屏蔽氧化物蚀刻包括氢氟酸。 In one embodiment, the screen oxide etch comprising hydrofluoric acid. 然而,根据本发明原理,也可以使用任何其它常用于蚀刻氧化物所适用的化学方法,包括湿法和干式蚀刻。 However, according to the principles of the present invention may be used in any other suitable oxide etch chemistry, including wet and dry etching. 在另一实施例中,薄的栅极绝缘体包括大约6至50厚度的二氧化硅。 In another embodiment, the thin silicon dioxide gate insulator comprises a thickness of about 6 to 50. 在另一实施例中,提供具有高介电常数(高K)的材料。 In another embodiment, there is provided a material having a high dielectric constant (high K),. 高K材料的实例是那些介电常数大于二氧化硅的介电常数的材料,包括,例如,氮氧化硅(nitrided silicon dioxide)、氮化硅、和诸如TiO2、Al2O3、La2O3、HfO2、ZrO2、CeO2、Ta2O5、WO3、Y2O3和LaAlO3的金属氧化物等等。 Examples of high K materials are those dielectric constant greater than silicon dioxide dielectric material, including, for example, silicon oxynitride (nitrided silicon dioxide), silicon nitride, and such as TiO2, Al2O3, La2O3, HfO2, ZrO2, CeO2, Ta2O5, WO3, Y2O3, and LaAlO3 metal oxides and the like. 通过提供原位搀杂的硅薄膜后栅极绝缘体立即开始生长。 A gate insulator provided immediately after the start to grow a silicon film by in-situ doped. 该薄膜是重搀杂,例如,对N型器件采用磷,而对P型器件采用硼。 The film is heavily doped, e.g., the N-type device using phosphorus, and boron for P-type devices. 使用光刻技术和硅蚀刻技术,栅极电极320构成如图3中的工艺步骤300所示的图形。 Using photolithography and silicon etching techniques, the gate electrode 320 constituting the pattern 300 shown in FIG. 3 process steps. 在一个实施例中,在栅极电极图形化之后,提供其它沟道杂质,使得沟道杂质浓度轮廓在垂直和横向两个方向上都发生明显的变化。 In one embodiment, after patterning the gate electrode, the channel providing the other impurities, such that the channel impurity concentration profile changed significantly in both the vertical and transverse directions.

如图4所示,在硅栅极电极320的上表面425和侧壁410上提供薄的绝缘体。 As shown, a thin insulator 4 on the upper surface 320 of the silicon gate electrode 425 and sidewall 410. 在一个实施例中,薄的绝缘体是厚度大约为50至500的热生长氧化物。 In one embodiment, the thin insulator is a thermally grown oxide thickness of approximately 50 to the 500. 在另一实施例中,通过采用快速热氧化(RTO)工艺,其具有持续时间为0.0至60秒的摄氏900度至1200度的最高温度,来提供热生长薄的氧化物。 In another embodiment, the rapid thermal oxidation (RTO) process, which has a duration of 0.0 to 60 seconds maximum temperature of 900 degrees Celsius to 1200 degrees, to provide a thermally grown thin oxide. 本领域熟练技术人员容易认识到,有许多制造方法可以用于提供薄的绝缘层,例如,沉积方法。 Those skilled in the art will readily recognize, there are many manufacturing methods may be used to provide a thin insulating layer, for example, a deposition method. 本领域熟练技术人员还将意识到,可以使用其它材料作为薄的绝缘体,例如,氮化物,以及绝缘层可以包括多种绝缘体材料。 Those skilled in the art will appreciate that other materials may be used as a thin insulator, e.g., a nitride, and the insulating layer may include a plurality of insulator material. 随后,可以使用各向同性蚀刻去除在水平表面上的绝缘层(以及暴露出硅420和425),从而暴露出水平表面,同时保留在垂直表面上的绝缘层。 It may then be removed using an isotropic etch the insulating layer (420 and 425, and the silicon is exposed) on the horizontal surface, thereby exposing the horizontal surface, while leaving the insulating layer on the vertical surfaces. 这样,就形成了侧壁绝缘体410。 In this way, a sidewall insulator 410 is formed. 本领域熟练技术人员将会理解,栅极电极320和侧壁绝缘体410对各向同性蚀刻具有掩模的功能,使得在硅衬底上薄的绝缘层中的工作与栅极电极320的工作类似。 Those skilled in the art will appreciate, the gate electrode 320 and the sidewall insulator 410 pairs isotropic etching mask having features such work on a silicon substrate a thin insulating layer with the gate electrode 320 work similar . 在一个实施例中,薄的绝缘体大约为50至500。 In one embodiment, the thin insulator is approximately 50 to 500. 在薄的绝缘层中的工作将与对栅极电极320的工作类似,并且在偏离栅极电极320的横向距离大约50至500的范围内。 Working a thin insulating layer will be similar to the working of the gate electrode 320, and deviates from the range of about 50 to 500 lateral distance of the gate electrode 320. 在一个示例性实施例中,硅表面420下凹至栅极绝缘体的底部下大约为1nm至大约5nm的深度D2 430。 In one exemplary embodiment, the silicon surface 420 to the lower concave bottom gate insulator is about 1nm to about 5nm depth D2 430. 在一个示例性实施例中,采用RTO工艺,提供侧壁绝缘体,在器件栅极电极和在沟道区域中的杂质可以在侧壁绝缘体形成的同时电性能激活,正如图4中的工艺步骤400所示。 In one exemplary embodiment, the RTO process is employed to provide the sidewall insulator, the electrical properties of the device while the gate electrode and the impurity in the channel region may be formed in the side wall insulator activation, as in process step 400 of FIG. 4 Fig.

如图5所示,第二蚀刻工艺步骤横向和垂直蚀刻半导体衬底。 5, a second etch process step laterally and vertically etching the semiconductor substrate. 这种蚀刻称之为局部各向同性蚀刻。 This etching is called locally isotropic etching. 在一个实施例中,使用横向蚀刻速率至少为垂直蚀刻速率10%的局部各向同性蚀刻。 In one embodiment, a lateral etch rate of at least 10% of a vertical etch rate of an isotropic etch partially. 在另一实施例中,使用垂直蚀刻速率至少为横向蚀刻速率10%的局部各向同性蚀刻。 In another embodiment, a vertical etch rate is at least 10% of the lateral etch rate of an isotropic etch partially. 第二蚀刻的深度为D3510。 The depth of the second etching is D3510. 横向蚀刻将半导体衬底520所暴露的垂直侧壁从侧壁氧化物410的边缘以距离L1 530横向移位到栅极电极320的下方位置。 Laterally etching the semiconductor substrate 520 exposed from the vertical sidewall edge of the sidewall oxide 410 to a distance L1 530 laterally displaced to a position under the gate electrode 320. 因为蚀刻是局部各向同性的,所以L1可以小于或者等于D3的十倍,或D3可以小于或者等于L1的十倍。 Because the etch is partially isotropic, so that L1 may be less than or equal to ten times D3 or D3 may be less than or equal to ten times L1. 在另一实施例中,使用横向蚀刻速率大约等于垂直蚀刻速率的蚀刻。 In another embodiment, a lateral etch rate approximately equal to the vertical etch rate etch. 在该实施例中,D3可以大约等于L1。 In this embodiment, D3 may be approximately equal to L1. 在还有一个实施例中,采用SF6干式蚀刻、HF:HNO3湿法蚀刻中的任何一种或其组合或者适用于蚀刻半导体材料所常用的任何湿法或干式蚀刻来提供局部各向同性蚀刻。 In yet another embodiment, dry etching using SF6, HF: HNO3 any one of or a combination of wet etching, or any suitable wet etching or dry etching of the semiconductor material used to provide a local isotropy etching.

如图6所示,下一步骤包括沉积适当的金属作为在所有暴露表面上的覆盖薄膜。 6, the next step includes depositing an appropriate metal as a cover film on all exposed surfaces. 可以采用溅射或蒸发工艺或者其它常用的任何薄膜成形工艺来提供沉积。 Sputtering or evaporation process may be employed, or any other conventional film forming process providing a deposition. 在一个实施例中,在金属沉积的过程中,衬底是加热的,以促使所撞击的金属原子扩散在栅极绝缘体下所暴露的硅表面520。 In one embodiment, the metal deposition process, the substrate is heated to cause diffusion of the impinging metal atoms in the gate insulator 520 exposed silicon surface. 在一个实施例中,该金属大约250厚,但是通常为大约50至1000厚。 In one embodiment, the thickness of the metal around 250, but is generally from about 50 to 1000 thick. 虽然这里进行了讨论,其实还可参考在IC制造中有关的肖特基和类肖特基势垒和接触提供更多的实例。 Although discussed, in fact, also with reference to Schottky and Schottky-like barriers and contacts in the related IC fabrication more examples. 本发明并不认可在影响本发明范围方面可使用的肖特基界面类型的任何限制。 The present invention is not recognized by any limitation of the Schottky interface type in the scope of the present invention may be used. 于是,本发明特别期望采用任何形式的导电材料或合金来创建这类接触。 Accordingly, the present invention is particularly desirable conductive material or alloy to create any form of such contacts. 例如,对于P型器件而言,金属源极和漏极610和620电极可以由硅化铂、硅化钯、硅化铱中的任何一种或者其组合所制成。 For example, for a P-type device, the metal source and drain electrodes 610 and 620 may be made from any of a silicide, platinum silicide, palladium silicide, iridium, or a combination thereof. 对于N型器件而言,金属源极和漏极610和620可以由选自包含诸如硅化铒、硅化镝或硅化镱或其组合之类的稀土硅化物族材料制成。 For the N-type device, the metal source and drain electrodes 610 and 620 may be made of a material selected from the group of rare earth silicide such as a silicide comprises erbium silicide, ytterbium, dysprosium silicide, or combinations thereof, or the like. 应理解的是,也可以使用在晶体管级常用任何其它适用的金属,例如,钛、钴等等,以及更多的外来金属和其它合金。 It should be understood, may also be used any other suitable metals commonly used at the transistor level, e.g., titanium, cobalt, etc., as well as more exotic metals and other alloys. 在另一实施例中,硅化物源极/漏极可以采用多层金属硅化物制成,在这种情况下,可以使用诸如硅化钛或硅化钨的其它典型的硅化物。 In another embodiment, the silicide source / drain can be made of multiple layers of metal silicide, in this case, may be used such as other typical silicide, titanium silicide or tungsten silicide.

随后,将晶圆在特定的温度下持续特定时间进行退火,使得在所有位置上金属都与硅直接接触,产生化学反应将金属转变成金属硅化物610、620和630。 Subsequently, the wafer is annealed at a certain time at a specific temperature, such that the metal is in direct contact with the silicon in all positions, the chemical reaction is converted into metal silicide 610, 620 and 630. 在一个实施例中,例如,晶圆可在大约摄氏400度下进行持续约45分钟的退火,或者通常在摄氏300至700度下进行持续大约1至120分钟的退火。 In one embodiment, for example, the wafer may be annealed for about 45 minutes at about 400 degrees Celsius, or is generally carried out for approximately 1 to 120 minutes annealing at 300 to 700 degrees Celsius. 与诸如栅极侧壁隔离片410的非硅表面直接接触的金属仍保持未反应,并且因此而没有影响。 In direct contact with the metal surface, such as a non-silicon gate sidewall spacer 410 remains unreacted, and therefore has no effect.

随后,使用湿法化学蚀刻,以去除未反应金属,同时保留不可触及的金属硅化物。 Subsequently, wet chemical etching, to remove the unreacted metal while leaving the metal silicide inaccessible. 在一个实施例中,使用王水去除铂,使用HNO3去除铒。 In one embodiment, platinum is removed using aqua regia, HNO3 removed using erbium. 应理解的是,在本发明的范围内,适用于蚀刻铂或铒所常用的任何其它适用的蚀刻化学方法或者适用于形成肖特基或类肖特基接触所使用的任何其它适用金属系统都可以使用。 It should be understood that, within the scope of the present invention is applicable to any other suitable chemical etching method for etching platinum or erbium are commonly used in or applied to any other suitable metal forming a Schottky or Schottky-like contact with the system used by all can use. 现在,就完成了沟道注入、短沟道SB-MOS器件,并且准备用于栅极320、源极610和漏极620的电性能连接,如图6中的工艺步骤600所示。 Now, to complete the channel implant, short channel SB-MOS device, and prepares for the gate 320, source 610 and drain 620 connected to electrical performance, process step 6600 shown in FIG.

该示例性工艺的结果,对沟道区域540和衬底210分别形成了肖特基或类肖特基接触,其中,肖特基接触位于局部各向同性蚀刻工艺所控制的位置上。 The result of this exemplary process, the channel region 540 and the substrate 210 are formed a Schottky or Schottky-like contacts, wherein the Schottky contact is positioned partially controlled by an isotropic etching process on. 在一个实施例中,源极610和漏极620电极与沟道区域540的界面520横向位于隔离片410的下方并且对准栅极电极640各边的边缘。 In one embodiment, the source electrode 610 and drain region 620 of the channel interface 540 below the spacer 520 is laterally aligned with the edges 640 and 410 of the respective sides of the gate electrode. 在另一实施例中,源极610和漏极620电极与沟道区域540的界面520横向位于隔离片410的下方和局部在栅极电极320的下方。 In another embodiment, the interface 520 and the lateral source 610 and the drain electrode 620 is located below the channel region 540 below the spacer 410 and partially in the gate electrode 320. 在还有一个实施例中,在源极610和漏极620电极与沟道区域540的界面520和栅极电极620的各边边缘之间形成了间隙。 In yet another embodiment, between each side edge of the source electrode 610 and drain electrode 620 and the channel region 540 of the interface 520 and the gate electrode 620 is formed a gap.

虽然传统肖特基接触是陡峭的,但是本发明特别期望在某些条件下可以在硅衬底和金属之间使用界面层。 While traditional Schottky contacts are abrupt, the present invention is particularly desirable to use an interface layer between the silicon substrate and the metal under certain conditions. 这些界面层可以是超薄的,所具有的厚度大约为10nm或小于10nm。 The interfacial layer may be thin, having a thickness of about 10nm or less than 10nm. 于是,本发明特别期望在实现本发明的过程中类肖特基接触及其等效物十分有用。 Accordingly, the present invention is particularly desirable in Schottky contact and equivalents thereof useful class implementation of the present invention. 此外,界面层可以由具有导电、半导电和/或类绝缘特性的材料构成。 In addition, the interface layer may be formed of a material having conducting, semiconducting and / or insulating property class. 例如,可以使用氧化物或氮化物绝缘体的超薄界面层、可以使用通过搀杂隔离技术所形成的超薄搀杂层、或者,诸如锗的半导体的超薄界面层可用来在它们之间形成类肖特基接触。 For example, ultra-thin interfacial layer of oxide or nitride insulator can be used thin doped layer formed by doping isolation technology, or ultra-thin interfacial layer such as germanium semiconductor is used to form therebetween class Shaw Schottky contacts.

SB-MOS器件的一项重要的性能特征是驱动电流(Id),即,当所施加的源极电压(Vs)接地以及栅极电压(Vg)和漏极电压(Vd)以电源电压(Vdd)偏压时,从源极流向漏极的电流。 An important performance feature of SB-MOS devices is the drive current (Id), i.e., when the source voltage (Vs) is applied to a ground and the gate voltage (Vg) and drain voltage (Vd) to the power supply voltage (Vdd) when the bias voltage, the drain electrode of the current flowing from the source. SB-MOS器件的另一项重要的特征是总的栅极电容(Cg),即,由诸如栅极绝缘体310、边缘场电容以及叠加电容等各种电容所确定的总的电容。 Another important feature of SB-MOS devices is the total gate capacitance (Cg), i.e., various capacitance such as the gate insulator 310, and the fringe field capacitance is superimposed on the determined total capacitance of the capacitor. 驱动电流和总的栅极电容是决定电路性能的两项关键性参数。 Drive current and total gate capacitance are two key parameters determine circuit performance. 例如,晶体管的开关速度可标定为Id/Cg,即,驱动电流越大和总的栅极电容越小,则器件的开关速度就越快,从而具有更高性能的集成电路。 For example, the switching speed of the transistor may be calibrated to Id / Cg, i.e., the larger the driving current, and the smaller total gate capacitance, the faster the switching speed of the device, so as to have higher performance integrated circuits. 有许多变量会影响SB-MOS器件的驱动电流和总的栅极电容,包括,例如,如图6所示,肖特基或类肖特基接触520相对于栅极电极640的横向位置。 Many variables affect the SB-MOS device drive current and total gate capacitance, including, for example, as shown in FIG 6, a Schottky or Schottky-like contacts 520 with respect to the lateral position of the gate electrode 640.

在SB-MOS器件中,驱动电流,通常是由通过肖特基势垒进入道沟道的隧道电流密度(JSB)所确定的,它受到在源极和沟道区域界面处栅极感应电场(Es)的强烈控制。 The SB-MOS device, the drive current, typically by a Schottky barrier inlet channel through the channel tunneling current density (JSB) is determined, it is subjected to the source and the channel region of the interface of the gate induced electric field ( es) strong control. 随着施加到栅极的电压(Vg)的增加,Es也随之增加。 With the increase is applied to the gate voltage (Vg) of, Es also increases. 所增加的Es改变了肖特基势垒,使得JSB大致根据公式(1)而增加,这显示了JSB与Es成幂指数敏感,式中A和B都是常数,并且JSB和Es的单位分别为(A/cm2)和(V/M)。 The increased Es changed Schottky barrier, such that JSB substantially according to the formula (1) is increased, which shows the JSB and Es sensitive to the exponent, wherein A and B are constants, and the units of JSB and Es, respectively, It is (A / cm2), and (V / M).

JSB=Ae(-BES)]]>除了Vg,Es也受到接近于栅极电极640边缘的肖特基势垒沟道区域界面520的强烈影响。 JSB = Ae (-BES)]]> In addition to Vg, Es is also strongly affected by the gate electrode 640 closer to the edge of the Schottky barrier interface 520 of the channel region. 当界面520不是在栅极电极320的下方时,Es以及JSB和Id明显下降并且随着界面横向远离栅极电极的边缘640而持续下降。 When not at the interface 520 under the gate electrode 320, Es and JSB and Id decrease significantly as the interfacial and laterally away from the edges of the gate electrode 640 and continued to decline. 因此,本发明提供了一种制造SB-MOS器件的方法,该方法允许采用局部各向同性蚀刻技术精确控制肖特基或类肖特基源极和漏极区域相对于栅极电极的位置。 Accordingly, the present invention provides a method of manufacturing a SB-MOS device, the method allows an isotropic etching technique using local Schottky or Schottky-precise control of source and drain regions relative to the gate electrode. 本发明的工艺提供一种最大化电场Es和驱动电流Id以及优化器件性能的方法。 The present invention provides a process to maximize the electric field Es and drive current Id and a method for optimizing device performance.

就总的栅极电容Cg而言,界面520相对于栅极电极边缘640的最佳位置是器件设计的一项功能和性能的需求。 To total gate capacitance Cg, the optimal location of the interface 520 with respect to the edge of the gate electrode 640 is a function of the needs of device design and performance. 特别是,总的栅极电容Cg随着在界面520和栅极电极边缘640之间的距离增加而减小,同时,还值得注意的是,驱动电流Id也同时减小。 In particular, the total gate capacitance Cg increases as the distance between the interface 520 and the edge 640 of the gate electrode is reduced, it is also worth noting that, while the drive current Id is also reduced. 性能的优化将需要在驱动电流Id和总的栅极电容Cg之间进行折衷权衡,这就使得本发明的技术可以提供更加良好的控制性。 Performance optimization will require tradeoffs between the driving current Id and total gate capacitance Cg, which makes the technique of the present invention can provide a more excellent controllability. 例如,使用本发明的局部各向同性蚀刻技术,可以提供界面520相对于栅极电极边缘640的位置,使得栅极电容Cg和驱动电流Id的折衷权衡最优化。 For example, an isotropic etching technique using local present invention, the interface 520 can be provided with respect to the edge of the gate electrode 640, so that the trade-off the gate capacitance Cg and drive current Id are optimized.

使用本发明的技术,随之会产生下列益处,但并不限制与此。 Using the techniques of the present invention, the following benefits will be produced, but is not limited to this. 第一,局部各向同性蚀刻步骤提供了在栅极电极之下的肖特基或类肖特基接触设置的精确位置的附加制造控制。 First, the isotropic etch step provides a partial Schottky type under the gate electrode or the precise location of the Schottky contact is provided for producing an additional control. 所产生的肖特基或类肖特基接触位置因此可以可控制地放置在栅极电极下方的横向位置上,以使得驱动电流最大、总的栅极电容最小以及器件性能最优。 The resulting Schottky or Schottky-like contact position can therefore be controllably placed at a lateral position below the gate electrode, so that the drive current of the maximum, minimum, and total gate capacitance optimal device performance. 第二个益处是通过蚀刻栅极电极的下方,可以减小有效沟道的长度。 The second benefit is obtained by etching under the gate electrode, the effective channel length can be reduced. 可以理解的是,沟道长度越短就能进一步增加驱动电流。 It will be appreciated that the shorter the channel length can be further increased drive current.

本发明尤其适用于在制造短沟道长度的MOSFET的情况下使用,特别是,在沟道长度小于100nm的情况下使用。 The present invention is particularly suitable for use in the case of manufacturing a short channel length of a MOSFET, in particular, in the case where the channel length is less than 100nm. 然而,在本发明的教导中并没有限制将本发明的教导应用于短的沟道长度器件。 However, the teachings of the present invention does not limit the teachings of the present invention is applied to a short channel length devices. 本发明的教导已经在任何尺寸的沟道长度中得到良好的应用。 The teachings of the present invention have good application in any dimension of the channel length.

尽管已经参考较佳实施例讨论了本发明,但是本领域熟练技术人员将会意识到,可以在不背离本发明的精神和范围的条件下在形式和细节上进行各种变化。 Although discussed with reference to the preferred embodiment of the present invention, those skilled in the art will appreciate that various changes in form and detail without departing from the spirit and scope of the invention. 本发明可以应用于多种沟道、衬底和阱注入轮廓。 The present invention may be applied to a variety of channel, substrate and well implant profiles. 本发明适用于金属源极和漏极技术的任何使用,无论是采用SOI衬底、富硅衬底、SiGe衬底、FinFET技术、高K栅极绝缘体、和金属栅极。 The present invention is applicable to any use of metal source and drain technology, whether it is the use of an SOI substrate, a silicon-rich substrate, SiGe substrate, a FinFET technology, high K gate insulators, and metal gates. 该列举并没有限制。 This list is not limited. 采用金属源极—漏极接触来调整电流的流动的任何器件都将具有本文所教授的益处。 Metal source - drain contacts any means to adjust the flow of current will have the benefit of being taught herein.

然而,本发明特别适用于SB-MOS半导体器件所使用,它也可以用于其它半导体器件。 However, the present invention is particularly suitable for SB-MOS semiconductor device used, it can also be used for other semiconductor devices. 因此,尽管本说明书描述了SB-MOS所使用的制造工艺,但是这些内容也应该广泛地理解成包括任何器件,只要该器件用于调整具有两点或多点电性能接触且其中至少一个电性能接触是肖特基或类肖特基接触的导电沟道的电流流动。 Thus, although the present specification describes a SB-MOS fabrication process used, but these elements should be broadly interpreted to include any device, as long as the device having two or more points is used to adjust the electrical performance of the contact and wherein the at least one electrical property It is the contact current flow conduction channel Schottky contact or Schottky-like.

Claims (25)

1.一种制造用于调整电流量的器件的方法,该方法包括:制备半导体衬底;在所述半导体衬底上制备栅极电极;在接近于所述栅极电极的区域内暴露所述半导体衬底;使用局部各向同性蚀刻将所述半导体衬底蚀刻在所述暴露区域上;在所述半导体衬底的蚀刻区域内沉积金属薄膜;以及,金属和所述衬底反应,以形成肖特基或类肖特基源极电极或漏极电极。 1. A method of manufacturing a device for adjusting a current amount, the method comprising: preparing a semiconductor substrate; a gate electrode on the prepared semiconductor substrate; exposed in the region close to the gate electrode of said a semiconductor substrate; partial isotropic etching using the semiconductor substrate is etched in the exposed area; etching the deposited metal film in the region of the semiconductor substrate; and a metal and the substrate, to form Schottky or Schottky-like source electrode or the drain electrode.
2.如权利要求1所述的方法,其特征在于,所述半导体衬底由硅、富硅、绝缘体上硅、硅锗、砷化镓或者磷化铟构成。 2. The method according to claim 1, wherein said semiconductor substrate is made of silicon, silicon-rich, silicon on insulator, silicon germanium, gallium arsenide or indium phosphide.
3.如权利要求1所述的方法,其特征在于,所述蚀刻步骤是使用横向蚀刻速率大约是垂直蚀刻速率的1/10至10倍的蚀刻进行的。 The method according to claim 1, wherein said etching step is performed using a lateral etch rate of about 1/10 to 10 times the vertical etch rate of the etching.
4.如权利要求1所述的方法,其特征在于,所述局部各向同性蚀刻包括半导体衬底的垂直蚀刻速率和半导体衬底的横向蚀刻速率,其中,垂直蚀刻速率大约是横向蚀刻速率的10倍。 4. The method according to claim 1, wherein said isotropic etching comprises a partial vertical lateral etch rate of the etch rate of the semiconductor substrate and the semiconductor substrate, wherein the vertical etch rate is approximately the lateral etch rate 10 times.
5.如权利要求1所述的方法,其特征在于,所述局部各向同性蚀刻包括半导体衬底的横向蚀刻速率和半导体衬底的垂直蚀刻速率,其中,横向蚀刻速率大约是垂直蚀刻速率的10倍。 5. The method according to claim 1, wherein said isotropic etching comprises a partial vertical lateral etch rate of the etch rate of the semiconductor substrate and the semiconductor substrate, wherein the lateral etch rate is approximately vertical etching rate 10 times.
6.如权利要求1所述的方法,其特征在于,所述局部各向同性蚀刻包括半导体衬底的横向蚀刻速率和半导体衬底的垂直蚀刻速率,其中,横向蚀刻速率与垂直蚀刻速率大致相同。 6. The method according to claim 1, wherein said isotropic etching comprises a partial vertical lateral etch rate and an etch rate of the semiconductor substrate, a semiconductor substrate, wherein the lateral etching rate and the vertical etching rate is substantially the same .
7.如权利要求1所述的方法,其特征在于,所述栅极电极可采用下列步骤制备:在所述半导体衬底上制备薄的绝缘层;在所述绝缘层上沉积薄的导电膜;对所述导电薄膜进行图形化和蚀刻,以形成栅极电极;以及,在所述栅极电极的一个或多个侧壁上形成一个或多个薄的绝缘层。 7. The method according to claim 1, wherein the gate electrode can be prepared in the following steps: preparing a thin insulating layer on the semiconductor substrate; depositing a conductive thin film on the insulating layer ; of patterning said conductive film and etched to form a gate electrode; and, forming one or more thin insulating layers on one or more of the side walls of the gate electrode.
8.如权利要求1所述的方法,其特征在于,还包括在形成肖特基或类肖特基源极和漏极电极之后从器件上去除未反应的金属。 8. The method according to claim 1, characterized in that, further comprising removing unreacted metal from the device after forming the Schottky or Schottky-like source and drain electrodes.
9.如权利要求1所述的方法,其特征在于,所述反应步骤通过热退火来进行。 9. The method according to claim 1, wherein said reacting step is carried out by thermal annealing.
10.如权利要求1所述的方法,其特征在于,所述源极电极和漏极电极由硅化铂、硅化钯、硅化铱中的任何一种或者其组合所形成。 10. The method according to claim 1, wherein the source electrode and the drain electrode is formed of platinum silicide, palladium silicide, iridium silicide, any or a combination thereof.
11.如权利要求1所述的方法,其特征在于,所述源极电极和漏极电极由稀土硅化物所形成。 11. The method according to claim 1, wherein the source electrode and the drain electrode is formed of a rare earth silicide.
12.如权利要求1所述的方法,其特征在于,所述肖特基或类肖特基接触至少形成在栅极电极之下的沟道区域邻近的区域内。 12. The method according to claim 1, wherein the Schottky or Schottky-like contact with at least the channel formed in the region below the region adjacent to the gate electrode.
13.如权利要求1所述的方法,其特征在于,所述源极电极和漏极电极至少一个的整个表面形成与所述半导体衬底的肖特基或类肖特基接触。 13. The method according to claim 1, characterized in that the entire surface of at least one of the source electrode and the drain electrode of the semiconductor substrate forms a Schottky or Schottky-like contacts.
14.如权利要求1所述的方法,其特征在于,在制备所述栅极电极步骤之前,对所述半导体衬底引入杂质,其中在源极和漏极电极之间沟道区域中的杂质由砷、磷或锑组成。 14. The method according to claim 1, characterized in that, prior to the step of preparing the gate electrodes, introducing impurities of the semiconductor substrate, wherein between the source and drain electrodes in the channel region impurity arsenic, phosphorus or antimony.
15.如权利要求1所述的方法,其特征在于,在制备所述栅极电极步骤之前,对所述半导体衬底引入杂质,其中在源极和漏极电极之间沟道区域中的杂质由硼、铟或镓组成。 15. The method according to claim 1, characterized in that, prior to the step of preparing the gate electrodes, introducing impurities of the semiconductor substrate, wherein between the source and drain electrodes in the channel region impurity boron, gallium or indium.
16.如权利要求14所述的方法,其特征在于,所述半导体衬底具有在垂直方向上显著变化而在横向方向基本恒定的沟道杂质浓度。 16. The method according to claim 14, wherein said semiconductor substrate has a significant change in the transverse direction of the channel substantially constant impurity concentration in the vertical direction.
17.如权利要求14所述的方法,其特征在于,所述半导体衬底具有在垂直方向上和在横向方向上都显著变化的沟道杂质浓度。 17. The method according to claim 14, wherein said semiconductor substrate has an impurity concentration of a channel in the vertical direction and in the transverse direction, significantly changes.
18.如权利要求15所述的方法,其特征在于,所述半导体衬底具有在垂直方向上显著变化而在横向方向基本恒定的沟道杂质浓度。 18. The method according to claim 15, wherein said semiconductor substrate has a significant change in the transverse direction of the channel substantially constant impurity concentration in the vertical direction.
19.如权利要求15所述的方法,其特征在于,所述半导体衬底具有在垂直方向上和在横向方向上都显著变化的沟道杂质浓度。 19. The method according to claim 15, wherein said semiconductor substrate has an impurity concentration of a channel in the vertical direction and in the transverse direction, significantly changes.
20.一种制造用于调整电流量的器件的方法,该方法包括:在栅极电极附近区域内暴露半导体衬底;使用局部各向同性蚀刻将所述半导体衬底蚀刻在暴露区域上;以及,沉积和热退火薄膜金属和所述半导体衬底,以形成肖特基或类肖特基源极电极或漏极电极。 20. A method of manufacturing a device for adjusting a current amount, the method comprising: exposing a semiconductor substrate in a region near the gate electrode; partial isotropic etching using the semiconductor substrate etching on the exposed region; , a metal film deposition and thermal annealing and the semiconductor substrate to form a Schottky or Schottky-like source electrode or the drain electrode.
21.如权利要求20所述的方法,其特征在于,所述局部各向同性蚀刻包括半导体衬底的垂直蚀刻速率和半导体衬底的横向蚀刻速率,其中,垂直蚀刻速率大约是横向蚀刻速率的10倍。 21. The method according to claim 20, wherein said isotropic etching comprises a partial vertical lateral etch rate of the etch rate of the semiconductor substrate and the semiconductor substrate, wherein the vertical etch rate is approximately the lateral etch rate 10 times.
22.如权利要求20所述的方法,其特征在于,所述局部各向同性蚀刻包括半导体衬底的横向蚀刻速率和半导体衬底的垂直蚀刻速率,其中,横向蚀刻速率大约是垂直蚀刻速率的10倍。 22. The method according to claim 20, wherein said isotropic etching comprises a partial vertical lateral etch rate of the etch rate of the semiconductor substrate and the semiconductor substrate, wherein the lateral etch rate is approximately vertical etching rate 10 times.
23.如权利要求20所述的方法,其特征在于,所述局部各向同性蚀刻包括半导体衬底的横向蚀刻速率和半导体衬底的垂直蚀刻速率,其中,横向蚀刻速率与垂直蚀刻速率大致相同。 23. The method according to claim 20, wherein said isotropic etching comprises a partial vertical lateral etch rate and an etch rate of the semiconductor substrate, a semiconductor substrate, wherein the lateral etching rate and the vertical etching rate is substantially the same .
24.如权利要求20所述的方法,其特征在于,所述蚀刻步骤是使用横向蚀刻速率大约是垂直蚀刻速度的1/10至10倍的蚀刻进行的。 24. The method according to claim 20, wherein said etching step is performed using a lateral etch rate of about 1/10 to 10 times the vertical etch rate of the etching.
25.如权利要求20所述的方法,其特征在于,所述半导体衬底在所述沉积步骤的过程中被加热,以促进金属原子扩散进入所述半导体衬底。 25. The method according to claim 20, wherein said semiconductor substrate is heated during the deposition step in order to promote diffusion of metal atoms into the semiconductor substrate.
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JP2007507905A (en) 2007-03-29

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