CN110349854A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN110349854A
CN110349854A CN201910180129.8A CN201910180129A CN110349854A CN 110349854 A CN110349854 A CN 110349854A CN 201910180129 A CN201910180129 A CN 201910180129A CN 110349854 A CN110349854 A CN 110349854A
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pattern
layer
presoma
substrate
alloy
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CN110349854B (zh
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朴圭熙
朴阳仙
林载顺
曹仑廷
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了一种制造半导体装置的方法，所述方法包括：在基底上形成半导体图案，使得半导体图案彼此竖直间隔开；以及形成金属逸出功图案以填充半导体图案之间的空间，其中，形成金属逸出功图案的步骤包括执行原子层沉积(ALD)工艺以形成合金层，并且ALD工艺包括在基底上提供包含有机铝化合物的第一前驱体以及在基底上提供包含钒‑卤素化合物的第二前驱体。

Description

制造半导体装置的方法
于2018年4月2日在韩国知识产权局提交的第10-2018-0037939号且发明名称为“制造半导体装置的方法”的韩国专利申请通过引用全部包含于此。
技术领域
实施例涉及一种制造半导体装置的方法。
背景技术
由于半导体装置的小尺寸、多功能和/或低成本特性，使得半导体装置是电子工业中的重要元件。通常，半导体装置分为用于存储数据的存储装置、用于处理数据的逻辑装置以及用于执行各种功能的混合装置。
发明内容
可以通过提供制造半导体装置的方法来实现实施例，所述方法包括：在基底上形成半导体图案，使得半导体图案彼此竖直间隔开；以及形成金属逸出功图案以填充半导体图案之间的空间，其中，形成金属逸出功图案的步骤包括执行原子层沉积(ALD)工艺以形成合金层，并且ALD工艺包括在基底上提供包含有机铝化合物的第一前驱体以及在基底上提供包含钒-卤素化合物的第二前驱体。
可以通过提供制造半导体装置的方法来实现实施例，所述方法包括在基底上形成栅电极使得栅电极包括包含钒和铝的合金层，其中，形成包括合金层的栅电极的步骤包括：在基底上提供第一前驱体；以及在基底上提供包含钒-卤素化合物的第二前驱体，其中，第一前驱体包括由下面的化学式1表示的化合物：
其中，在化学式1中，R1至R3均独立地为氢原子、C1-C10烷基、C3-C10烯基或C3-C10炔基，并且R1至R3中的至少一个为C1-C10烷基、C3-C10烯基或C3-C10炔基。
可以通过提供制造半导体装置的方法来实现实施例，所述方法包括执行原子层沉积(ALD)工艺以在基底上形成VAlC层，其中，ALD工艺包括多个工艺循环，每个工艺循环包括在基底上提供第一前驱体，以及在基底上提供包含VCl4的第二前驱体，其中，第一前驱体包括由下面的化学式1表示的化合物：
并且
其中，在化学式1中，R1至R3均独立地为氢原子、C1-C10烷基、C3-C10烯基或C3-C10炔基，并且R1至R3中的至少一个为C1-C10烷基、C3-C10烯基或C3-C10炔基。
附图说明
通过参照附图详细地描述示例性实施例，特征对于本领域技术人员将是明显的，在附图中：
图1示出了根据一些实施例的用于形成合金层的原子层沉积(ALD)工艺的循环的流程图。
图2示出了示意性地示出根据一些实施例的用于沉积合金层的沉积系统的概念图。
图3和图4示出了图1中示出的ALD工艺的循环的剖视图。
图5示出了通过根据一些实施例的方法制造的合金层的剖视图。
图6示出了根据一些实施例的半导体装置的平面图。
图7示出了沿着图6的线A-A'和线B-B'截取的竖直剖面的视图。
图8、图10、图12和图14示出了根据一些实施例的制造半导体装置的方法中的阶段的平面图。
图9示出了沿着图8的线A-A'和线B-B'截取的竖直剖面的视图。
图11示出了沿着图10的线A-A'和线B-B'截取的竖直剖面的视图。
图13示出了沿着图12的线A-A'和线B-B'截取的竖直剖面的视图。
图15和图16示出了沿着图14的线A-A'和线B-B'截取的竖直剖面的视图。
图17示出了示出根据实验实施例1至实验实施例3的VAlC层的电阻率值的曲线图。
图18A至图18C示出了通过根据实验实施例1至实验实施例3的VAlC层的X射线光电子能谱获得的结果的曲线图。
具体实施方式
图1是示出根据一些实施例的用于形成合金层的原子层沉积(ALD)工艺的循环的流程图。图2是示意性地示出根据一些实施例的用于沉积合金层的沉积系统的概念图。图3和图4是示出图1中示出的ALD工艺的循环的剖视图。图5是示出通过根据一些实施例的方法制造的合金层的剖视图。
参照图1至图5，可以在基底100上形成合金层CAL。合金层CAL的形成可以包括在基底100上执行原子层沉积(ALD)工艺。
ALD工艺可以包括顺序执行的多个工艺循环A，并且每个工艺循环A包括将第一前驱体送入到室中(在步骤S100中)、吹扫室(在步骤S110中)、将第二前驱体送入到室中(在步骤S120中)以及吹扫室(在步骤S130中)。
例如，如图2中所示，基底100可以设置在工艺室CHA中。基底100可以装载在可置于工艺室CHA中的基座SUS上。基座SUS可以支撑基底100。另外，基座SUS可以使基底100旋转。
可以将第一前驱体送入到设置有基底100的工艺室CHA中(在S100中)。第一前驱体可以存储在连接到工艺室CHA的第一容器CNa中。可以对第一容器CNa中的第一前驱体进行加热，并使第一容器CNa中的第一前驱体蒸发。可以将蒸发的第一前驱体与供应到第一容器CNa中的第一载气一起送入到工艺室CHA中。第一载气可以是例如氩气、氦气或氖气的惰性气体。
第一前驱体可以包含具有下面的化学式1的有机铝化合物。
[化学式1]
在化学式1中，R1至R3可以均独立地为例如氢原子、(C1-C10)烷基、(C3-C10)烯基或(C3-C10)炔基。在实施方式中，R1至R3中的至少一个可以是(C1-C10)烷基、(C3-C10)烯基或(C3-C10)炔基。在实施方式中，第一前驱体可以是下面的化学式2的化合物，即三乙基铝。
[化学式2]
送入到工艺室CHA中的第一前驱体可以通过分布板DIS均匀地喷射到基底100上。可以在第一进料时间期间将第一前驱体送入到工艺室CHA中。第一进料时间可以为0.1秒至100秒。喷射到基底100上的第一前驱体可以用于在基底100上形成第一原子层AL1。
在将第一前驱体送入到工艺室CHA中之后，可以使用吹扫气体来吹扫工艺室CHA的内部空间(在步骤S110中)。吹扫气体可以是惰性气体。
返回参照图1、图2和图4，可以将第二前驱体送入到设置有基底100的工艺室CHA中(在步骤S120中)。第二前驱体可以存储在连接到工艺室CHA的第二容器CNb中。可以对第二容器CNb中的第二前驱体进行加热，并使第二容器CNb中的第二前驱体蒸发。可以将蒸发的第二前驱体与供应到第二容器CNb中的第二载气一起送入到工艺室CHA中。
第二前驱体可以包含钒-卤素化合物。在实施方式中，第二前驱体可以包括例如氯化钒、氟化钒或溴化钒。在实施方式中，第二前驱体可以包括例如VCl4、VCl5、VF4、VF5、VBr4或VBr5。第二前驱体可以在大气压(例如，1atm)和室温(例如，25℃)下保持液态或固态。
例如，VCl4可以在大气压和室温下保持液态，并且呈液态状态的VCl4可以存储在第二容器CNb中。液态VCl4可以易于处理。可以通过包括热加热的各种蒸发方法容易地蒸发VCl4。此外，VCl4可以在ALD工艺的工艺温度下具有相对高的蒸气压，并且可以大大减少工艺时间。
送入到工艺室CHA中的第二前驱体可以通过分布板DIS均匀地喷射到基底100上。可以在第二进料时间期间将第二前驱体送入到工艺室CHA中。第二进料时间可以为0.1秒至100秒。
喷射到基底100上的第二前驱体可以与第一原子层AL1反应，从而形成第二原子层AL2。例如，第二前驱体可以与第一原子层AL1的烃反应，在这种情况下，第一原子层AL1的碳原子和第二前驱体的钒原子可以彼此反应以形成C-V键。在形成C-V键期间，可以产生氢-卤素化合物(例如，HCl)的挥发性气体。
在将第二前驱体送入到工艺室CHA中之后，可以使用吹扫气体吹扫工艺室CHA的内部空间(在步骤S130中)。吹扫气体可以是惰性气体。
在ALD工艺期间，工艺室CHA的内部压强可以保持在0.01kPa至150kPa的范围内。工艺室CHA的内部温度可以保持在200℃至500℃的范围内。
返回参照图1、图2和图5，可以重复执行循环A以形成构成合金层CAL的多个第二原子层AL2。合金层CAL可以包括例如VxAlyCz，其中x的范围为20至40，y的范围为5至30，z的范围为30至55。可以通过控制合金层CAL的铝含量(即，y值)来将合金层CAL的逸出功和电阻率调节到所期望的水平。合金层CAL的铝含量越高，合金层CAL的电阻率越高，并且合金层CAL的逸出功越低。将y保持在5或更大可以有助于确保合金层CAL具有足够高的电阻率和足够低的逸出功。将y保持在30或更小可以有助于确保合金层CAL具有足够高的逸出功和足够低的电阻率。例如，在y值在5至30的范围内的情况下，合金层CAL可以形成为具有相对低的电阻率和相对低的逸出功。
在实施方式中，合金层CAL可以包括钒铝碳化物。合金层CAL可以包括C-V键和C-Al键。在实施方式中，合金层CAL还可以包括氧和/或氢。
提供下面的示例以突出一个或更多个实施例的特性，但将理解的是，示例不应解释为限制实施例的范围。此外，将理解的是，实施例不限于示例中描述的具体细节。
[实验示例]
使用图2的沉积系统来在形成在基底上的氧化硅层上形成VAlC层。使用三乙基铝(Et3Al)作为第一前驱体，使用四氯化钒(VCl4)作为第二前驱体。
将包含第一前驱体的第一容器CNa保持在60℃。使用水浴瓶(bubbler)对第一前驱体进行加热，并使第一前驱体蒸发。将包含第二前驱体的第二容器CNb保持在25℃。使用水浴瓶对第二前驱体进行加热，并使第二前驱体蒸发。在沉积工艺期间，基底的温度保持在400℃。将工艺室CHA的内部压强调节到100Pa。
在实验实施例1中，将第一前驱体送入到工艺室CHA中，持续5秒(即，第一前驱体的进料时间为5秒)。在送入第一前驱体之后，使用氩气吹扫工艺室CHA 30秒。将第二前驱体送入到工艺室CHA中，持续0.1秒。在送入第二前驱体之后，使用氩气吹扫工艺室CHA 30秒。将包括上述步骤的循环重复三十次以形成VAlC层(在实验实施例1中)。
在实验实施例2中，第一前驱体的进料时间为6秒，并且除了第一前驱体的进料时间不同之外，通过与实验实施例1中的方法相同的方法来形成实验实施例2中的VAlC层。在实验实施例3中，第一前驱体的进料时间为7秒，并且除了第一前驱体的进料时间不同之外，通过与实验实施例1中的方法相同的方法来形成实验实施例3中的VAlC层。
图17示出了分别示出从实验实施例1至实验实施例3的VAlC层测量的电阻率值的曲线图。如图17中所示，第一前驱体的进料时间越长，VAlC层的电阻率越高。例如，VAlC层的铝含量越高，VAlC层的电阻率越高。
图18A、图18B和图18C示出了示出通过实验实施例1至实验实施例3的VA1C层的X射线光电子能谱获得的结果的曲线图。如图18A、图18B和图18C中所示，实验实施例1至实验实施例3的VAlC层中的每个是含钒和铝的碳化物层。此外，图18A、图18B和图18C示出第一前驱体的进料时间越长，VAlC层的铝含量越大。
图6是示出根据一些实施例的半导体装置的平面图。图7是示出沿着图6的线A-A'和线B-B'截取的竖直剖面的视图。
参照图6和图7，可以提供基底100。基底100可以是半导体基底。在实施方式中，基底100可以是硅基底或锗基底。在实施方式中，基底100可以是绝缘体上硅(SOI)晶圆。晶体管可以设置在基底100的区域上。
在实施方式中，用于存储数据的多个存储单元可以形成在作为基底100的区域的存储单元区域上。例如，构成多个SRAM单元的多个存储单元晶体管可以设置在基底100的存储单元区域上。图6和图7的晶体管可以是存储单元晶体管中的一些。
在实施方式中，构成半导体装置的逻辑电路的多个逻辑晶体管可以形成在作为基底100的区域的逻辑单元区域上。例如，逻辑晶体管可以设置在基底100的逻辑单元区域上。图6和图7的晶体管可以是逻辑晶体管中的一些。
例如，图6和图7的晶体管可以是PMOSFET。例如，图6和图7的晶体管可以是NMOSFET。
器件隔离层ST可以设置在基底100上。器件隔离层ST可以限定作为基底100的上部的上图案UP。上图案UP可以在第二方向D2上延伸。器件隔离层ST可以形成为填充形成在上图案UP的两侧处的沟槽。器件隔离层ST的顶表面可以比上图案UP的顶表面低。
有源图案AP可以设置在上图案UP上。例如，有源图案AP可以与上图案UP竖直叠置。有源图案AP可以是在第二方向D2上延伸的线形图案。
有源图案AP可以包括沟道图案CH和源极/漏极图案SD。沟道图案CH可以置于一对源极/漏极图案SD之间。沟道图案CH可以包括多个竖直堆叠的半导体图案NS。
半导体图案NS可以在与基底100的顶表面垂直的第三方向D3上彼此间隔开。半导体图案NS可以彼此竖直叠置。每个源极/漏极图案SD可以与半导体图案NS的侧表面直接接触。换句话说，半导体图案NS可以设置为使相邻的一对源极/漏极图案SD彼此连接。在实施方式中，沟道图案CH可以具有三个半导体图案NS。在实施方式中，所有的半导体图案NS可以具有基本相同的厚度，或者半导体图案NS中的至少两个可以具有彼此不同的厚度。半导体图案NS可以由例如Si、SiGe和Ge中的至少一种形成，或者可以包括例如Si、SiGe和Ge中的至少一种。
源极/漏极图案SD可以是外延图案，外延图案使用半导体图案NS和上图案UP作为种子层通过外延生长工艺来形成。在图6和图7的晶体管是PMOSFET的情况下，源极/漏极图案SD可以由能够对沟道图案CH施加压应力的材料形成，或者可以包括能够对沟道图案CH施加压应力的材料。例如，源极/漏极图案SD可以由其晶格常数比沟道图案CH的晶格常数大的半导体材料(例如，SiGe)形成，或者可以包括其晶格常数比沟道图案CH的晶格常数大的半导体材料(例如，SiGe)。源极/漏极图案SD可以掺杂有杂质以具有p型导电性。
在图6和图7的晶体管是NMOSFET的情况下，源极/漏极图案SD可以由与沟道图案CH的半导体材料相同的半导体材料(例如，Si)形成，或者可以包括与沟道图案CH的半导体材料相同的半导体材料(例如，Si)。源极/漏极图案SD可以掺杂有杂质以具有n型导电性。
栅电极GE可以设置为跨过沟道图案CH并在第一方向D1上延伸。栅电极GE中的每个可以包括金属逸出功图案WF和电极图案EL。电极图案EL可以设置在金属逸出功图案WF上。电极图案EL可以具有比金属逸出功图案WF的电阻低的电阻。电极图案EL可以具有比合金层CAL的电阻低的电阻。例如，电极图案EL可以由低电阻金属材料(例如，包括铝(Al)、钨(W)、钛(Ti)和钽(Ta))中的至少一种形成，或者可以包括低电阻金属材料(例如，包括铝(Al)、钨(W)、钛(Ti)和钽(Ta))中的至少一种。
金属逸出功图案WF可以包括金属氮化物层MN和位于金属氮化物层MN上的合金层CAL。合金层CAL可以具有与先前参照图1至图5描述的合金层CAL的特征基本相同的特征。例如，合金层CAL可以包括具有VxAlyCz的化学结构或由VxAlyCz表示的材料。合金层CAL可以具有相对低的逸出功。可以调节合金层CAL的铝含量(即，y值)以控制合金层CAL的逸出功和电阻率。金属氮化物层MN可以具有比合金层CAL的逸出功大的逸出功。例如，金属氮化物层MN可以是氮化钛(TiN)层或氮氧化钛(TiON)层。
金属逸出功图案WF可以设置为填充半导体图案NS之间的第一空间SP1。金属逸出功图案WF可以围绕每个半导体图案NS。例如，金属逸出功图案WF可以设置为面对每个半导体图案NS的顶表面、底表面和侧表面。图6和图7的晶体管中的每个可以以全栅极环绕(gate-all-around)型场效应晶体管的形式提供。
每个栅电极GE可以具有第一部分P1和第二部分P2。第一部分P1可以位于第一空间SP1中，第一空间SP1形成在半导体图案NS中的竖直相邻的半导体图案NS之间。例如，第一部分P1可以置于半导体图案NS中的竖直相邻的半导体图案NS之间。
第二部分P2可以位于第二空间SP2中，第二空间SP2形成在半导体图案NS中的最顶部的半导体图案NS上。第二空间SP2可以是由一对栅极间隔件GS和半导体图案NS中的最顶部的半导体图案NS限定的空间，所述一对栅极间隔件GS将在下面描述。例如，第二部分P2可以位于半导体图案NS中的最顶部的半导体图案NS上，并且可以置于所述一对栅极间隔件GS之间。
栅电极GE的第一部分P1可以由金属逸出功图案WF构成，栅电极GE的第二部分P2可以由顺序堆叠的金属逸出功图案WF和电极图案EL构成。电极图案EL可以与栅电极GE的第一部分P1间隔开。例如，电极图案EL可以不填充第一空间SP1。电极图案EL可以不存在于第一空间SP1中。
一对栅极间隔件GS可以设置在每个栅电极GE的两个相对的侧表面上。栅极间隔件GS可以沿栅电极GE或沿第一方向D1延伸。栅极间隔件GS可以具有比栅电极GE的顶表面高的顶表面。沟道图案CH上的金属逸出功图案WF可以沿栅极间隔件GS的内侧表面或沿第三方向D3延伸。栅极间隔件GS可以由例如SiCN、SiCON和SiN中的至少一种形成，或者可以包括例如SiCN、SiCON和SiN中的至少一种。在实施方式中，栅极间隔件GS可以包括由SiCN、SiCON和SiN中的至少两种制成的多层。
栅极盖层CP可以设置在每个栅电极GE上。栅极盖层CP可以沿栅电极GE或沿第一方向D1延伸。栅极盖层CP的顶表面可以与栅极间隔件GS的顶表面基本上共面。栅极盖层CP可以由相对于第一层间绝缘层110具有蚀刻选择性的材料形成，或者可以包括相对于第一层间绝缘层110具有蚀刻选择性的材料，该第一层间绝缘层110将在下面描述。在实施方式中，栅极盖层CP可以由SiON、SiCN、SiCON和SiN中的至少一种形成，或者可以包括SiON、SiCN、SiCON和SiN中的至少一种。
绝缘图案IP可以置于源极/漏极图案SD与栅电极GE之间。绝缘图案IP可以置于彼此竖直分离的半导体图案NS之间。绝缘图案IP可以使栅电极GE与源极/漏极图案SD电断开。第一空间SP1可以由彼此水平相邻的一对绝缘图案IP和彼此竖直相邻的一对半导体图案NS限定。绝缘图案IP可以由例如氮化硅形成，或者可以包括例如氮化硅。
界面层IL可以设置为围绕半导体图案NS中的每个。界面层IL可以设置为直接覆盖半导体图案NS。界面层IL可以由例如氧化硅形成，或者可以包括例如氧化硅。
栅极介电层GI可以置于半导体图案NS与栅电极GE之间。栅极介电层GI可以设置为共形地覆盖第一空间SP1，并且部分地填充第一空间SP1。栅极介电层GI可以由高k介电材料中的至少一种形成，或者可以包括高k介电材料中的至少一种，该高k介电材料的介电常数比氧化硅的介电常数高。例如，高k介电材料可以由氧化铪、氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化锂、氧化铝、氧化铅钪钽和铌酸铅锌中的至少一种形成，或者可以包括氧化铪、氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化锂、氧化铝、氧化铅钪钽和铌酸铅锌中的至少一种。
第一层间绝缘层110可以设置在基底100的顶表面上。第一层间绝缘层110可以设置为覆盖器件隔离层ST和源极/漏极图案SD。第一层间绝缘层110的顶表面可以与栅极盖层CP的顶表面基本上共面。在实施方式中，第一层间绝缘层110可以包括氧化硅层或氮氧化硅层。
在实施方式中，接触件可以设置为穿透第一层间绝缘层110，并且可以连接到源极/漏极图案SD。接触件可以由金属材料(例如，钨(W)、钛(Ti)和钽(Ta))中的至少一种形成，或者可以包括金属材料(例如，钨(W)、钛(Ti)和钽(Ta))中的至少一种。
图8、图10、图12和图14示出了根据一些实施例的制造半导体装置的方法中的阶段的平面图。图9示出了沿着图8的线A-A'和线B-B'截取的竖直剖面的视图，图11示出了沿着图10的线A-A'和线B-B'截取的竖直剖面的视图，图13示出了沿着图12的线A-A'和线B-B'截取的竖直剖面的视图，图15和图16示出了沿着图14的线A-A'和线B-B'截取的竖直剖面的视图。
参照图8和图9，可以在基底100的顶表面上交替地且重复地堆叠牺牲层120和半导体层130。在实施方式中，可以在基底100上堆叠三个半导体层130。在实施方式中，牺牲层120可以由可相对于半导体层130以蚀刻选择性被蚀刻的材料形成，或者可以包括可相对于半导体层130以蚀刻选择性被蚀刻的材料。例如，半导体层130可以由在蚀刻牺牲层120的工艺期间不被蚀刻的材料形成。在实施方式中，在蚀刻牺牲层120的工艺期间，牺牲层120与半导体层130的蚀刻速率的比可以在10:1至200:1的范围内。在实施方式中，牺牲层120可以由SiGe或Ge形成，半导体层130可以由Si形成。
可以通过外延生长工艺来形成牺牲层120和半导体层130，在外延生长工艺中基底100用作种子层。在不中断的情况下，可以在同一室中形成牺牲层120和半导体层130。可以生长牺牲层120和半导体层130中的每个以共形地覆盖基底100的顶表面或具有均匀的厚度。
可以对牺牲层120、半导体层130和基底100执行图案化工艺以形成预备有源图案PAP。可以执行图案化工艺以蚀刻基底100的上部。结果，可以形成上图案UP，并且预备有源图案PAP可以设置在上图案UP上。预备有源图案PAP可以形成为具有线形状或条形状并在第二方向D2上延伸。
作为图案化工艺期间的蚀刻工艺的结果，可以在上图案UP的两侧处形成沟槽。此后，可以形成器件隔离层ST以填充沟槽。器件隔离层ST的形成可以包括在基底100的顶表面上形成绝缘层，并且使绝缘层凹陷以完全暴露预备有源图案PAP。例如，器件隔离层ST可以形成为具有比上图案UP的顶表面低的顶表面。
参照图10和图11，可以形成牺牲栅极图案140以跨过预备有源图案PAP。牺牲栅极图案140可以形成为具有线形状或条形状并在第一方向D1上延伸。在特定实施例中，可以分别在牺牲栅极图案140上形成栅极掩模图案MP。牺牲栅极图案140和栅极掩模图案MP的形成可以包括在基底100上顺序地形成牺牲栅极层和栅极掩模层，并且对栅极掩模层和牺牲栅极层进行图案化。牺牲栅极层可以由多晶硅形成，或者可以包括多晶硅。栅极掩模层可以包括氮化硅层和氮氧化硅层中的至少一个。
可以在牺牲栅极图案140中的对应的一个牺牲栅极图案140的两个相对的侧表面上形成一对栅极间隔件GS。栅极间隔件GS可以由例如SiCN、SiCON和SiN中的至少一种形成，或者可以包括例如SiC、SiCON和SiN中的至少一种。栅极间隔件GS的形成可以包括利用诸如CVD或ALD的沉积工艺形成间隔层，然后对间隔层执行各向异性蚀刻工艺。
参照图12和图13，可以对预备有源图案PAP进行图案化以形成沟道图案CH。可以利用栅极掩模图案MP和栅极间隔件GS作为蚀刻掩模来执行预备有源图案PAP的图案化。可以执行预备有源图案PAP的图案化以使上图案UP的一部分暴露。
例如，可以通过对预备有源图案PAP的牺牲层120进行图案化来形成牺牲图案125。可以通过对预备有源图案PAP的半导体层130进行图案化来形成半导体图案NS。半导体图案NS可以构成沟道图案CH。
在图案化工艺之后，可以横向蚀刻牺牲图案125的暴露部分以形成凹陷区域DR。凹陷区域DR的形成可以包括使用能够选择性地蚀刻牺牲图案125的蚀刻剂的蚀刻工艺。在实施方式中，在半导体图案NS包括Si，并且牺牲图案125包括SiGe的情况下，凹陷区域DR的形成可以包括使用包含过氧乙酸的蚀刻溶液的蚀刻工艺。
可以形成绝缘图案IP以分别填充凹陷区域DR。绝缘图案IP可以彼此竖直间隔开，并且半导体图案NS置于其间。例如，绝缘图案IP的形成可以包括在基底100的顶表面上共形地形成绝缘层。可以形成绝缘层以填充凹陷区域DR。此后，可以蚀刻绝缘层以在凹陷区域DR中局部地形成绝缘图案IP。
可以在每个沟道图案CH的两侧处形成源极/漏极图案SD。例如，可以通过选择性外延工艺来形成源极/漏极图案SD，在选择性外延工艺中半导体图案NS和上图案UP用作种子层。沟道图案CH和源极/漏极图案SD可以彼此连接以形成在第二方向D2上延伸的有源图案AP。
在实施方式中，源极/漏极图案SD可以由能够对沟道图案CH施加压应力的材料形成，或者可以包括能够对沟道图案CH施加压应力的材料。例如，源极/漏极图案SD可以由具有比硅的晶格常数大的晶格常数的SiGe形成。在选择性外延工艺期间或之后，源极/漏极图案SD可以掺杂有杂质以具有p型导电性。
在实施方式中，源极/漏极图案SD可以由与沟道图案CH的半导体材料相同的半导体材料(例如，Si)形成。在选择性外延工艺期间或之后，源极/漏极图案SD可以掺杂有杂质以具有n型导电性。
参照图14和图15，可以在基底100的顶表面上形成第一层间绝缘层110。此后，可以对第一层间绝缘层110进行平坦化以使牺牲栅极图案140的顶表面暴露。可以使用回蚀工艺和/或化学机械抛光(CMP)工艺来对第一层间绝缘层110进行平坦化。在一些实施例中，在第一层间绝缘层110的平坦化期间，可以去除栅极掩模图案MP。第一层间绝缘层110可以由例如氧化硅和氮氧化硅中的至少一种形成，或者可以包括例如氧化硅和氮氧化硅中的至少一种。
可以选择性地去除通过平坦化工艺暴露的牺牲栅极图案140。可以执行牺牲栅极图案140的去除以在基底100上形成沟槽TC。在实施方式中，可以形成沟槽TC以使沟道图案CH暴露。可以形成沟槽TC以使牺牲图案125暴露。
可以选择性地去除由沟槽TC暴露的牺牲图案125。在牺牲图案125和半导体图案NS分别包括SiGe和Si的情况下，可以通过使用包含过氧乙酸的蚀刻溶液的选择性蚀刻工艺来去除牺牲图案125。蚀刻溶液还可以包含氢氟酸(HF)溶液和去离子水。在一些实施例中，源极/漏极图案SD可以被绝缘图案IP和第一层间绝缘层110覆盖并保护。
作为去除牺牲图案125的结果，可以形成第一空间SP1和第二空间SP2。第一空间SP1可以是形成在彼此竖直相邻的半导体图案NS之间的空的空间。第二空间SP2可以是由一对栅极间隔件GS和半导体图案NS中的最顶部的半导体图案NS限定的空的空间。第一空间SP1和第二空间SP2可以连接到沟槽TC以使半导体图案NS暴露。
参照图14和图16，可以在由沟槽TC暴露的半导体图案NS上执行基于等离子体的氧化工艺。在这种情况下，界面层IL可以从半导体图案NS的暴露的表面生长。可以形成界面层IL以直接覆盖并包围半导体图案NS的暴露的表面。
界面层IL的形成可以包括热氧化工艺或化学氧化工艺。在一些实施例中，从氧、臭氧和蒸汽中的至少一种产生的等离子体可以用于氧化工艺。界面层IL可以由例如氧化硅形成，或者可以包括例如氧化硅。
可以在界面层IL上共形地形成栅极介电层GI。可以形成栅极介电层GI以部分地填充沟槽TC的第一空间SP1。可以形成栅极介电层GI以部分地填充沟槽TC的第二空间SP2。可以形成栅极介电层GI以直接覆盖绝缘图案IP和界面层IL。栅极介电层GI可以由高k介电材料中的至少一种形成，该高k介电材料的介电常数比氧化硅的介电常数高。
可以在每个沟槽TC中形成金属逸出功图案WF。可以形成金属逸出功图案WF以完全填充沟槽TC的第一空间SP1。可以形成金属逸出功图案WF以部分地填充沟槽TC的第二空间SP2。
金属逸出功图案WF的形成可以包括在沟槽TC中共形地形成金属氮化物层MN，并且在金属氮化物层MN上共形地形成合金层CAL。例如，可以通过沉积工艺(例如，ALD工艺)形成金属氮化物层MN和合金层CAL。在一些实施例中，可以通过与图1至图5的方法基本相同的方法来执行合金层CAL的形成。
在实施方式中，合金层CAL的形成可以包括提供包含有机铝化合物的第一前驱体，并且提供包含钒-卤素化合物的第二前驱体。通过控制第一前驱体的进料时间，可能够将合金层CAL的铝含量调节到期望的预定值。可以调节合金层CAL的铝含量以控制合金层CAL的逸出功和电阻率。这可以使晶体管具有期望的电特性(例如，阈值电压和电阻)。
返回参照图6和图7，可以执行蚀刻工艺以使栅极介电层GI的上部和金属逸出功图案WF的上部凹陷。可以在每个沟槽TC中形成电极图案EL。可以在金属逸出功图案WF的凹陷结构上形成电极图案EL。电极图案EL可以由具有低电阻的金属材料形成，或者可以包括具有低电阻的金属材料。金属逸出功图案WF和电极图案EL可以构成栅电极GE。
可以在栅电极GE上形成栅极盖层CP。作为示例，栅极盖层CP可以由SiON、SiCN、SiCON和SiN中的至少一种形成，或者可以包括SiON、SiCN、SiCON和SiN中的至少一种。在实施方式中，可以形成接触件以穿透第一层间绝缘层110，并且接触件可以连接到源极/漏极图案SD。
如本领域中的惯例，根据功能块、单元和/或模块，描述并在附图中示出了实施例。本领域技术人员将理解的是，这些块、单元和/或模块通过诸如逻辑电路、离散组件、微处理器、硬布线电路、存储元件、布线连接等的电子(或光学)电路物理地实现，电子(或光学)电路可以使用基于半导体的制造技术或其它制造技术形成。在通过微处理器或类似的硬件来实现块、单元和/或模块的情况下，可以使用软件(例如，微码)对它们进行编程，以执行这里所讨论的各种功能，并且可以选择地通过固件和/或软件来驱动它们。可选择地，每个块、单元和/或模块可以通过专用硬件来实现，或者以执行某些功能的专用硬件和执行其它功能的处理器(例如，一个或更多个编程的微处理器和相关电路)的组合来实现。此外，在不脱离这里的范围的情况下，实施例中的每个块、单元和/或模块可以物理地被分成两个或更多个交互的且离散的块、单元和/或模块。另外，在不脱离这里的范围的情况下，实施例中的块、单元和/或模块可以物理地组合成更复杂的块、单元和/或模块。
通过总结和回顾，随着电子工业的发展，半导体装置可以具有更高的集成密度和更高的性能。为了满足这种要求，(例如，在光刻工艺中)减少工艺余量可以是有帮助的。尽管可以考虑各种研究，但是工艺余量的减少会导致制造半导体装置中的若干问题。因此，进行了各种研究。
在根据一些实施例的制造方法中，可以促进将合金层CAL的铝含量调节到期望的水平。这可能够形成具有期望的电特性(例如，阈值电压和电阻)的全栅极环绕型晶体管。
根据一些实施例，制造半导体装置的方法可以包括形成V-Al合金层，该V-Al合金层的电阻率和逸出功相对低。V-Al合金层可以在全栅极环绕型场效应晶体管中用作逸出功控制材料。
实施例可以提供利用原子层沉积工艺制造半导体装置的方法。
实施例可以提供利用原子层沉积工艺形成包含钒和铝的合金层的方法。
这里已经公开了示例实施例，尽管采用了特定的术语，但是仅以一般的和描述性的含义来使用并解释它们，而不是为了限制的目的。在一些情况下，如本领域普通技术人员将清楚的是，自提交本申请之时起，结合具体实施例描述的特征、特性和/或元件可以单独使用，或者可以与结合其它实施例描述的特征、特性和/或元件组合起来使用，除非另外特别说明。因此，本领域技术人员将理解的是，在不脱离由权利要求阐述的本发明的精神和范围的情况下，可以做出形式上和细节上的各种改变。

Claims (20)

1.一种制造半导体装置的方法，所述方法包括以下步骤：
在基底上形成多个半导体图案，使得多个半导体图案彼此竖直间隔开；以及
形成金属逸出功图案以填充多个半导体图案之间的空间，
其中：
形成金属逸出功图案的步骤包括执行原子层沉积工艺以形成合金层，并且
原子层沉积工艺包括：
在基底上提供包含有机铝化合物的第一前驱体，以及
在基底上提供包含钒-卤素化合物的第二前驱体。
2.根据权利要求1所述的方法，其中：
有机铝化合物由下面的化学式1表示：
在化学式1中，R1至R3均独立地为氢原子、C1-C10烷基、C3-C10烯基或C3-C10炔基，
其中，R1至R3中的至少一个为C1-C10烷基、C3-C10烯基或C3-C10炔基。
3.根据权利要求1所述的方法，其中，钒-卤素化合物包括VCl4、VCl5、VF4、VF5、VBr4或VBr5。
4.根据权利要求1所述的方法，所述方法还包括在金属逸出功图案上形成电极图案，使得电极图案由具有比金属逸出功图案的电阻低的电阻的低电阻金属材料形成。
5.根据权利要求4所述的方法，其中：
形成所述金属逸出功图案以完全填充半导体图案之间的空间，并且
半导体图案之间的空间中不存在所述电极图案。
6.根据权利要求1所述的方法，其中：
形成金属逸出功图案的步骤还包括在形成合金层之前形成金属氮化物层，并且
金属氮化物层具有比合金层的逸出功高的逸出功。
7.根据权利要求1所述的方法，其中，在基底上提供第二前驱体的步骤包括使第二前驱体与第一前驱体中的烃反应以形成C-V键。
8.根据权利要求1所述的方法，其中，合金层具有VxAlyCz的化学结构，其中，x的范围为20至40，y的范围为5至30，并且z的范围为30至55。
9.根据权利要求1所述的方法，其中，形成半导体图案的步骤包括：
在基底上交替地并重复地堆叠牺牲层和半导体层；
对牺牲层和半导体层进行图案化以形成包括牺牲图案和半导体图案的预备有源图案；以及
选择性地去除牺牲图案。
10.根据权利要求9所述的方法，其中，选择性地去除牺牲图案的步骤包括：
形成牺牲栅极图案以跨过预备有源图案；
在基底上形成层间绝缘层；以及
选择性地去除牺牲栅极图案以在层间绝缘层中形成沟槽，使得沟槽暴露牺牲图案和半导体图案。
11.根据权利要求10所述的方法，所述方法还包括：
蚀刻预备有源图案的在牺牲栅极图案的两侧处的部分；以及
执行选择性外延工艺以在牺牲栅极图案的两侧处形成一对源极/漏极图案。
12.一种制造半导体装置的方法，所述方法包括：
在基底上形成栅电极，使得栅电极包括包含钒和铝的合金层，
其中，形成包括合金层的栅电极的步骤包括：
在基底上提供第一前驱体；以及
在基底上提供包含钒-卤素化合物的第二前驱体，
其中，第一前驱体包括由下面的化学式1表示的化合物：
其中，在化学式1中，R1至R3均独立地为氢原子、C1-C10烷基、C3-C10烯基或C3-C10炔基，并且R1至R3中的至少一个为C1-C10烷基、C3-C10烯基或C3-C10炔基。
13.根据权利要求12所述的方法，其中，钒-卤素化合物包括VCl4、VCl5、VF4、VF5、VBr4或VBr5。
14.根据权利要求12所述的方法，其中：
形成栅电极的步骤还包括在形成合金层之前形成金属氮化物层，并且
金属氮化物层具有比合金层的逸出功高的逸出功。
15.根据权利要求12所述的方法，其中，形成栅电极的步骤还包括在合金层上形成电极图案，使得电极图案由具有比合金层的电阻低的电阻的低电阻金属材料形成。
16.根据权利要求12所述的方法，其中，合金层具有VxAlyCz的化学结构，其中，x的范围为20至40，y的范围为5至30，并且z的范围为30至55。
17.一种制造半导体装置的方法，所述方法包括:
执行原子层沉积工艺以在基底上形成VAlC层，
其中，原子层沉积工艺包括多个工艺循环，每个工艺循环包括：
在基底上提供第一前驱体；以及
在基底上提供包含VCl4的第二前驱体，
其中，第一前驱体包括由下面的化学式1表示的化合物：
其中，在化学式1中，R1至R3均独立地为氢原子、C1-C10烷基、C3-C10烯基或C3-C10炔基，并且R1至R3中的至少一个为C1-C10烷基、C3-C10烯基或C3-C10炔基。
18.根据权利要求17所述的方法，其中，在基底上提供第二前驱体的步骤包括使第二前驱体与第一前驱体中的烃反应以形成C-V键。
19.根据权利要求17所述的方法，其中：
从容器提供VCl4，
容器中的VCl4处于液态，
提供第二前驱体的步骤包括：
对容器中的VCl4进行加热并使容器中的VCl4蒸发；以及
使用载气将蒸发的VCl4送入到设置有基底的工艺室中。
20.根据权利要求17所述的方法，其中，提供第一前驱体的步骤包括控制第一前驱体的进料时间，使得将VAlC层的逸出功和电阻率调节到预定水平。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102333599B1 (ko) * 2019-11-15 2021-11-30 주식회사 이지티엠 표면 보호 물질을 이용한 박막 형성 방법
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TW202146701A (zh) * 2020-05-26 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 氣相沉積系統、在基材上形成氮化釩層之方法、直接液體注入系統

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090315093A1 (en) * 2008-04-16 2009-12-24 Asm America, Inc. Atomic layer deposition of metal carbide films using aluminum hydrocarbon compounds
US20130277748A1 (en) * 2012-04-20 2013-10-24 Samsung Electronics Co., Ltd. Fin-type field effect transistors including aluminum doped metal-containing layer
CN104126228A (zh) * 2011-12-23 2014-10-29 英特尔公司 非平面栅极全包围器件及其制造方法
CN106030757A (zh) * 2014-02-18 2016-10-12 通用电气公司 碳化硅半导体装置和用于制造碳化硅半导体装置的方法
US20170069763A1 (en) * 2015-09-04 2017-03-09 International Business Machines Corporation Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
US20170278969A1 (en) * 2016-03-28 2017-09-28 International Business Machines Corporation Single process for liner and metal fill
WO2018026830A1 (en) * 2016-08-01 2018-02-08 Agilome, Inc. Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2493517A1 (en) * 2002-07-22 2004-01-29 Nanogram Corporation High capacity and high rate batteries
US7311946B2 (en) 2003-05-02 2007-12-25 Air Products And Chemicals, Inc. Methods for depositing metal films on diffusion barrier layers by CVD or ALD processes
US8178401B2 (en) 2005-08-25 2012-05-15 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device
US8679587B2 (en) 2005-11-29 2014-03-25 State of Oregon acting by and through the State Board of Higher Education action on Behalf of Oregon State University Solution deposition of inorganic materials and electronic devices made comprising the inorganic materials
US8101485B2 (en) 2005-12-16 2012-01-24 Intel Corporation Replacement gates to enhance transistor strain
US7611751B2 (en) * 2006-11-01 2009-11-03 Asm America, Inc. Vapor deposition of metal carbide films
KR101742616B1 (ko) 2010-10-12 2017-06-01 엘지이노텍 주식회사 발광소자 및 그 발광 소자의 제조 방법
US8404530B2 (en) 2011-07-07 2013-03-26 International Business Machines Corporation Replacement metal gate with a conductive metal oxynitride layer
US20130175619A1 (en) 2012-01-06 2013-07-11 International Business Machines Corporation Silicon-on-insulator transistor with self-aligned borderless source/drain contacts
US9006094B2 (en) 2012-04-18 2015-04-14 International Business Machines Corporation Stratified gate dielectric stack for gate dielectric leakage reduction
US9187511B2 (en) 2012-05-01 2015-11-17 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Titanium-aluminum alloy deposition with titanium-tetrahydroaluminate bimetallic molecules
JP6120250B2 (ja) 2013-06-05 2017-04-26 三菱マテリアル株式会社 サーミスタ用金属窒化物材料及びその製造方法並びにフィルム型サーミスタセンサ
JP6242198B2 (ja) 2013-12-10 2017-12-06 京都エレックス株式会社 半導体デバイスの導電膜形成用導電性ペースト、および半導体デバイス、並びに半導体デバイスの製造方法
US20150362374A1 (en) 2014-06-16 2015-12-17 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Atomic Layer Deposition of Vanadium Oxide for Microbolometer and Imager
KR102325522B1 (ko) 2015-01-29 2021-11-12 엘지전자 주식회사 금속 칼코게나이드 박막의 제조 방법
US9553092B2 (en) 2015-06-12 2017-01-24 Globalfoundries Inc. Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
KR20160148795A (ko) * 2015-06-16 2016-12-27 삼성전자주식회사 반도체 소자 및 이의 제조 방법
JP2017020056A (ja) 2015-07-07 2017-01-26 神港精機株式会社 合金窒化物膜形成装置および合金窒化物膜形成方法
KR102435622B1 (ko) 2016-03-10 2022-08-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10068901B2 (en) 2016-01-25 2018-09-04 Samsung Electronics Co., Ltd. Semiconductor device including transistors with different threshold voltages
US10431583B2 (en) 2016-02-11 2019-10-01 Samsung Electronics Co., Ltd. Semiconductor device including transistors with adjusted threshold voltages
KR102461174B1 (ko) * 2016-02-26 2022-11-01 삼성전자주식회사 반도체 소자
JP7133904B2 (ja) 2016-03-31 2022-09-09 住友化学株式会社 積層フィルム及びその製造方法
KR102532497B1 (ko) * 2016-09-19 2023-05-17 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR102403729B1 (ko) * 2017-11-03 2022-05-30 삼성전자주식회사 집적 회로 소자 및 그의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090315093A1 (en) * 2008-04-16 2009-12-24 Asm America, Inc. Atomic layer deposition of metal carbide films using aluminum hydrocarbon compounds
CN104126228A (zh) * 2011-12-23 2014-10-29 英特尔公司 非平面栅极全包围器件及其制造方法
US20130277748A1 (en) * 2012-04-20 2013-10-24 Samsung Electronics Co., Ltd. Fin-type field effect transistors including aluminum doped metal-containing layer
CN106030757A (zh) * 2014-02-18 2016-10-12 通用电气公司 碳化硅半导体装置和用于制造碳化硅半导体装置的方法
US20170069763A1 (en) * 2015-09-04 2017-03-09 International Business Machines Corporation Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
US20170278969A1 (en) * 2016-03-28 2017-09-28 International Business Machines Corporation Single process for liner and metal fill
WO2018026830A1 (en) * 2016-08-01 2018-02-08 Agilome, Inc. Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same

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