CN110299179B - 使用每存储器实例活动定制的动态功率分析 - Google Patents
使用每存储器实例活动定制的动态功率分析 Download PDFInfo
- Publication number
- CN110299179B CN110299179B CN201910131291.0A CN201910131291A CN110299179B CN 110299179 B CN110299179 B CN 110299179B CN 201910131291 A CN201910131291 A CN 201910131291A CN 110299179 B CN110299179 B CN 110299179B
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- CN
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- activity
- bist
- register
- memory
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/928587 | 2018-03-22 | ||
US15/928,587 US10748635B2 (en) | 2018-03-22 | 2018-03-22 | Dynamic power analysis with per-memory instance activity customization |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110299179A CN110299179A (zh) | 2019-10-01 |
CN110299179B true CN110299179B (zh) | 2023-07-18 |
Family
ID=67848478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910131291.0A Active CN110299179B (zh) | 2018-03-22 | 2019-02-22 | 使用每存储器实例活动定制的动态功率分析 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10748635B2 (zh) |
CN (1) | CN110299179B (zh) |
DE (1) | DE102019202019A1 (zh) |
TW (1) | TWI708255B (zh) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8677196B1 (en) * | 2011-06-20 | 2014-03-18 | Cadence Design Systems, Inc. | Low cost production testing for memory |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5983355A (en) * | 1996-05-20 | 1999-11-09 | National Semiconductor Corporation | Power conservation method and apparatus activated by detecting specific fixed interrupt signals indicative of system inactivity and excluding prefetched signals |
CA2212089C (en) | 1997-07-31 | 2006-10-24 | Mosaid Technologies Incorporated | Bist memory test system |
US6321320B1 (en) * | 1998-10-30 | 2001-11-20 | Hewlett-Packard Company | Flexible and programmable BIST engine for on-chip memory array testing and characterization |
US7269766B2 (en) * | 2001-12-26 | 2007-09-11 | Arm Limited | Method and apparatus for memory self testing |
US20050034089A1 (en) * | 2003-08-06 | 2005-02-10 | Mcguffin Tyson R. | Area based power estimation |
US7000204B2 (en) * | 2003-09-02 | 2006-02-14 | Hewlett-Packard Development Company, L.P. | Power estimation based on power characterizations |
US20060009959A1 (en) * | 2004-07-07 | 2006-01-12 | Fischer Timothy C | Activity factor based design |
JP2006209861A (ja) * | 2005-01-27 | 2006-08-10 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびそのテスト手法 |
US7555688B2 (en) * | 2005-04-26 | 2009-06-30 | Lsi Logic Corporation | Method for implementing test generation for systematic scan reconfiguration in an integrated circuit |
US7925899B2 (en) * | 2005-12-29 | 2011-04-12 | Intel Corporation | Method, system, and apparatus for runtime power estimation |
US20080046789A1 (en) * | 2006-08-21 | 2008-02-21 | Igor Arsovski | Apparatus and method for testing memory devices and circuits in integrated circuits |
US8090965B1 (en) | 2008-04-17 | 2012-01-03 | Lsi Corporation | System and method for testing memory power management modes in an integrated circuit |
US8513957B2 (en) * | 2010-06-02 | 2013-08-20 | International Business Machines Corporation | Implementing integral dynamic voltage sensing and trigger |
US9092622B2 (en) * | 2012-08-20 | 2015-07-28 | Freescale Semiconductor, Inc. | Random timeslot controller for enabling built-in self test module |
US8937845B2 (en) * | 2012-10-31 | 2015-01-20 | Freescale Semiconductor, Inc. | Memory device redundancy management system |
US20140249782A1 (en) * | 2013-03-01 | 2014-09-04 | International Business Machines Corporation | Dynamic power prediction with pin attribute data model |
EP3105674B1 (en) * | 2013-11-28 | 2018-01-10 | Telefonaktiebolaget LM Ericsson (publ) | Testing a feedback shift-register |
US9728273B2 (en) * | 2014-05-21 | 2017-08-08 | Lattice Semiconductor Corporation | Embedded memory testing using back-to-back write/read operations |
US9588177B1 (en) * | 2016-01-05 | 2017-03-07 | International Business Machines Corporation | Optimizing generation of test configurations for built-in self-testing |
-
2018
- 2018-03-22 US US15/928,587 patent/US10748635B2/en active Active
-
2019
- 2019-02-15 DE DE102019202019.4A patent/DE102019202019A1/de not_active Withdrawn
- 2019-02-18 TW TW108105231A patent/TWI708255B/zh active
- 2019-02-22 CN CN201910131291.0A patent/CN110299179B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8677196B1 (en) * | 2011-06-20 | 2014-03-18 | Cadence Design Systems, Inc. | Low cost production testing for memory |
Also Published As
Publication number | Publication date |
---|---|
TWI708255B (zh) | 2020-10-21 |
DE102019202019A1 (de) | 2019-09-26 |
CN110299179A (zh) | 2019-10-01 |
US20190295676A1 (en) | 2019-09-26 |
TW201946069A (zh) | 2019-12-01 |
US10748635B2 (en) | 2020-08-18 |
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Legal Events
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PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20230412 Address after: Singapore, Singapore Applicant after: Marvell Asia Pte. Ltd. Address before: Grand Cayman, Cayman Islands Applicant before: Kaiwei International Effective date of registration: 20230412 Address after: Bermuda Hamilton Applicant after: MARVELL INTERNATIONAL Ltd. Address before: Grand Cayman, Cayman Islands Applicant before: GLOBALFOUNDRIES INC. Effective date of registration: 20230412 Address after: Grand Cayman, Cayman Islands Applicant after: Kaiwei International Address before: Bermuda Hamilton Applicant before: MARVELL INTERNATIONAL Ltd. |
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