CN110265479B - Logic device, logic assembly and manufacturing method thereof - Google Patents
Logic device, logic assembly and manufacturing method thereof Download PDFInfo
- Publication number
- CN110265479B CN110265479B CN201910447226.9A CN201910447226A CN110265479B CN 110265479 B CN110265479 B CN 110265479B CN 201910447226 A CN201910447226 A CN 201910447226A CN 110265479 B CN110265479 B CN 110265479B
- Authority
- CN
- China
- Prior art keywords
- layer
- logic device
- heavy metal
- metal layer
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 65
- 230000008878 coupling Effects 0.000 claims abstract description 35
- 238000010168 coupling process Methods 0.000 claims abstract description 35
- 238000005859 coupling reaction Methods 0.000 claims abstract description 35
- 230000005294 ferromagnetic effect Effects 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 230000005291 magnetic effect Effects 0.000 claims description 34
- -1 polyethylene terephthalate Polymers 0.000 claims description 13
- 230000008859 change Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 8
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 8
- 230000002159 abnormal effect Effects 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010445 mica Substances 0.000 claims description 4
- 229910052618 mica group Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910002902 BiFeO3 Inorganic materials 0.000 claims description 3
- 229910019236 CoFeB Inorganic materials 0.000 claims description 3
- 239000004743 Polypropylene Substances 0.000 claims description 3
- 229910009567 YMnO3 Inorganic materials 0.000 claims description 3
- 229920001155 polypropylene Polymers 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000005502 peroxidation Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 239000004695 Polyether sulfone Substances 0.000 claims 1
- 229920006393 polyether sulfone Polymers 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000001125 extrusion Methods 0.000 abstract description 3
- 230000001105 regulatory effect Effects 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 238000001755 magnetron sputter deposition Methods 0.000 description 13
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 6
- 238000005265 energy consumption Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000004506 ultrasonic cleaning Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000005070 sampling Methods 0.000 description 5
- 150000002978 peroxides Chemical class 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000011265 semifinished product Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 125000004836 hexamethylene group Chemical group [H]C([H])([*:2])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])[*:1] 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 150000005690 diesters Chemical class 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66984—Devices using spin polarized carriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention provides a logic device and a manufacturing method thereof, wherein the logic device comprises: a substrate, a heavy metal layer, a ferromagnetic layer, a multiferroic layer, and an oxide layer; the heavy metal layer comprises a cross structure with the outer end provided with a corresponding electrode, and the resistance of the heavy metal layer is changed by changing the direction of an electric field applied between the oxide layer and the heavy metal layer. Specifically, the substrate is a flexible substrate, has the advantages of extrusion resistance, flexibility and the like, and the device realizes the regulation and control of an electric field on spin orbit coupling critical current through multiferroic materials at room temperature, so that spin orbit coupling signals are effectively regulated and controlled. The effect of the logic device is changed by utilizing interfaces (oxide layers) with different oxidation states, so that the regulation degree of the input voltage on the spin orbit coupling critical current is different, the n-type or p-type logic operation function can be achieved, a portable, portable and low-power-consumption logic device can be obtained, and the logic device can be combined to obtain a logic component integrating the n-type and p-type logic functions.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a logic device based on multiple ferromagnetic electric coupling and spin orbit coupling effects and a manufacturing method thereof.
Background
Traditional electronics are based on the charge property of electrons, and people realize information storage and logic processing through control of the charge of electrons. However, as electronic devices are increasingly miniaturized, the effects of quantum effects, energy loss, etc. are more and more apparent, and conventional electronic devices have failed to meet the needs of development.
The spintronic device has the advantages of non-volatility, low energy consumption, high integration level and the like, so that the spintronic device is rapidly developed, and the characteristics of high computing capacity, low energy consumption and the like of the spintronic device in information processing are incomparable with those of the traditional semiconductor electronic device. Spin-orbit coupling can utilize the torque generated by the spin-orbit coupling to realize the control of magnetic moment, and can realize spin-flip control under small size without generating spin-polarized current by means of specific magnetic materials. Spin logic devices based on spin orbit torque (spin orbit coupling) have particular advantages in terms of logic configuration, which can reconfigure logic operations. Spin-orbit coupling is readily modulated in conjunction with the voltage-controlled magnetic anisotropy (VCMA) effect. Conventional spin-orbit coupling modulation relies on current-generated magnetic fields, spin torque, etc., which require higher current densities and thus generate significant energy consumption. The multiferroic material can regulate and control spin orbit coupling by using an electric field, can effectively reduce energy consumption, and has great potential application prospects in the aspects of information storage, spintronics and the like.
In view of this, it is an object of the present invention to design a logic device that is lightweight, portable, low-power-consumption, and has good stability, and a method for manufacturing the same.
Disclosure of Invention
In view of the above, the present invention provides a logic device based on multiple ferromagnetic electric coupling and spin orbit coupling effects, so as to solve the problems of insufficient flexibility and high energy consumption of the logic device in the prior art.
In one aspect, the present invention provides a logic device, comprising:
the substrate is used for bearing the logic device and is a flexible substrate;
the heavy metal layer is positioned on the substrate and has the thickness of 3-10 nanometers;
The ferromagnetic layer is positioned on the heavy metal layer and has the thickness of 1-30 nanometers;
The multiferroic layer is positioned on the ferromagnetic layer and has the thickness of 2-200 nanometers;
An oxide layer, which is positioned on the multiferroic layer and has a thickness of 1-10 nanometers;
The heavy metal layer comprises at least one cross structure, and a corresponding electrode is arranged at the outer side end of the cross structure, and the resistance of the heavy metal layer is changed by changing the direction of voltage applied between the oxide layer and the heavy metal layer.
Preferably, the oxide layer is in one of a peroxidized or underoxidized state.
Preferably, the outer end of the cross structure includes an input electrode, the other end electrode opposite to the input electrode is grounded, the electrode at the other end of the cross structure in the direction perpendicular to the input electrode is an output end, and the abnormal hall voltage is detected from the output end as an output signal.
Preferably, the oxide layer is in a peroxidized state, when a positive voltage is applied between the oxide layer and the heavy metal layer, a spin-orbit coupling critical current of the peroxidized layer is I 11, and when a negative voltage is applied between the oxide layer and the heavy metal layer, a spin-orbit coupling critical current of the peroxidized layer is I 21, wherein I 11 is greater than I 21.
Preferably, the input current I is supplied to the input electrode, and when I 21＜I＜I11 is applied, the output signal does not change with a change in the direction of the input current I at a positive voltage, and the output signal reverses with a change in the direction of the input current I at a negative voltage.
Preferably, the peroxide layer is in an under-oxidized state, when a positive voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the peroxide layer is I 12, and when a negative voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the peroxide layer is I 22, wherein I 12 is smaller than I 22.
Preferably, the input current I is supplied to the input electrode, and when I 12＜I＜I22 is applied, the output signal is inverted with a change in the direction of the input current I at a positive voltage, and is not changed with a change in the direction of the input current I at a negative voltage.
According to another aspect of the present invention, there is also provided a logic assembly, including: at least 2 of the above logic devices; the logic device comprises two types of oxide layers, namely a peroxidation state and an underoxidation state, wherein the two types of logic devices are connected in series, the two types of heavy metal layers and the oxide layers of the logic devices are respectively connected in series, and at least one type of logic devices is controlled by changing the voltage direction selectivity between the oxide layers and the heavy metal layers.
According to another aspect of the present invention, there is also provided a method for manufacturing a logic device, including:
Cleaning the substrate;
preparing a heavy metal layer on the cleaned substrate;
photoetching and etching the heavy metal layer to form a cross structure;
corresponding electrodes are arranged at the outer side ends of the cross structures;
preparing a ferromagnetic layer on the heavy metal layer;
preparing a multiferroic layer on the ferromagnetic layer;
preparing an oxide layer on the multiferroic layer;
when the oxide layer is prepared on the multiferroic layer, the oxide layer can be in a peroxidized state or a underoxidized state by controlling the oxidation state of the oxide layer so as to form a p-type logic device or an n-type logic device respectively.
Preferably, the substrate is made of at least one material selected from polyether sulfone PES, polyethylene terephthalate PI, polyethylene terephthalate PET, polydimethylsiloxane PDMS, polypropylene hexamethylene diester PPA and Mica Mica;
The heavy metal layer is made of at least one material of Pt, W and Ta;
the electrode is made of at least one material of Pt, W and Ta;
The ferromagnetic layer is made of at least one of CoFeB, coFe, niFe, feCrCo, feCoV;
The multiferroic layer includes at least one of BiFeO3、GaFeO3、BiCrO3、TbMnO3、Bi2FeCrO6、BiMnO3、HoMn2O5、HoMn2O5、YbMn2O5、ScMn2O5、YMn2O5、GaMn2O5、DyMn2O5、ErMn2O5、HoMnO3、YbMnO3、ScMnO3、YMnO3、GaMnO3、DyMnO3、ErMnO3;
The material of the oxide layer is at least one of an oxide of Al, an oxide of Si and an oxide of Mg.
The logic device provided by the invention has the following advantages or beneficial effects: by adopting the flexible material to manufacture the substrate, the corresponding logic device has the advantages of lighter weight, extrusion resistance, flexibility and the like compared with the traditional device; the oxidation state of the oxide layer of the logic device can be adjusted according to the requirement, so that the required n-type or p-type logic device is formed, the n-type or p-type logic function is executed, the light, portable and low-power-consumption logic device is obtained, and correspondingly, the manufacturing method corresponding to the logic device has strong practicability.
Furthermore, the invention also provides a logic component formed by combining the two logic devices, which can directly execute the n-type logic function and the p-type logic function, integrates the n-type logic function and the p-type logic function, has the functions of simultaneously initializing and erasing the information of the two devices, is convenient and quick to operate, and further enhances the reliability of the logic component due to the logic complementarity of the logic component.
Based on the logic component provided by the invention, the logic component not only has a complementary logic operation function, but also has an information initialization or erasure function, and has a wide application prospect in the field of multifunctional or programmable spin logic devices.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a logic device according to an embodiment of the present invention;
FIG. 2 is a top view of a heavy metal layer of a logic device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a logic device according to an embodiment of the present invention;
FIG. 4a is a diagram illustrating experimental characteristics of a first embodiment of a logic device according to the present invention;
FIG. 4b is a truth table of a first embodiment of the logic device of the present invention;
FIG. 5a is a diagram illustrating experimental characteristics of a second embodiment of a logic device according to the present invention;
FIG. 5b is a truth table of a second embodiment of the logic device of the present invention;
FIG. 6 is a flow chart of a logic device according to an embodiment of the present invention;
FIG. 7a is a schematic diagram of a first embodiment of a logic component of the present invention;
FIG. 7b is a schematic diagram of a second embodiment of a logic assembly according to the present invention;
FIG. 8 is a truth table of the logic components of an embodiment of the present invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific embodiments of components or arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application.
Furthermore, in the description and claims, the terms "first," "second," and the like, are used to distinguish between similar elements, not necessarily to describe a temporal, spatial, hierarchical, or any other manner of order, it being understood that the terms may be interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
It is to be noticed that the term 'comprising', used in the claims, should not be interpreted as being restricted to the means listed thereafter, but not excluding other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, numbers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, numbers, steps or components, or groups thereof. Thus, the scope of the phrase "an apparatus comprising means a and B" should not be limited to only means consisting of only components a and B. This means that the relevant components of the device are a and B with respect to the present invention.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description provided herein, numerous specific details are set forth. It will be appreciated, however, that embodiments of the invention may be practiced without such specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
The invention may be embodied in various forms, some examples of which are described below.
Fig. 1 is a schematic structural diagram of a logic device according to an embodiment of the present invention, and as shown in fig. 1, a logic device 100 includes: the device comprises a substrate 110, a heavy metal layer 120, a ferromagnetic layer 130, a multiferroic layer 140 and an oxide layer 150, wherein the heavy metal layer 120 comprises a cross structure, and a corresponding electrode is arranged at the outer side end of the cross structure.
The whole structure is formed by stacking the substrate 110, the heavy metal layer 120, the ferromagnetic layer 130, the multiferroic layer 140 and the oxide layer 150 in sequence from bottom to top, wherein the heavy metal layer 120, the ferromagnetic layer 130, the multiferroic layer 140 and the oxide layer 150 are all in a film shape.
The substrate 110 may be made of Polyethersulfone (PES), polyethylene terephthalate (PI), polyethylene terephthalate (PET), polydimethylsiloxane (PDMS), polypropylene hexamethylene (polypropyleneadipate, PPA), mica (Mica), and the like, to realize a flexible substrate.
The heavy metal layer 120 may be made of Pt, W, ta, etc., and is formed into a cross structure by photolithography and etching, and a corresponding electrode is disposed at an outer end of the cross structure for electrical connection and measurement, and the thickness of the heavy metal layer is about 3nm to 10nm.
The ferromagnetic layer 130 may be made of CoFeB, coFe, niFe, feCrCo, feCoV a or the like and may have a thickness of about 1nm to about 30nm.
The multiferroic layer 140 is made of at least one material, such as BiFeO3、GaFeO3、BiCrO3、TbMnO3、Bi2FeCrO6、BiMnO3、HoMn2O5、HoMn2O5、YbMn2O5、ScMn2O5、YMn2O5、GaMn2O5、DyMn2O5、ErMn2O5、HoMnO3、YbMnO3、ScMnO3、YMnO3、GaMnO3、DyMnO3、ErMnO3 a, and has a thickness of about 2nm to about 200nm.
The oxide layer 150 may be made of AlO X、SiOX、MgOX (Al oxide, si oxide, mg oxide) or the like, wherein the value of X may be determined according to the oxidation state (peroxidized or underoxidized) of the corresponding oxide layer, and the thickness of the oxide layer 150 may be about 1nm to about 10nm.
Fig. 2 is a top view of a heavy metal layer of a logic device according to an embodiment of the present invention, as shown in fig. 2, a heavy metal layer 120 is located on a substrate 110, and a cross structure (hall bar structure) is formed by performing photolithography and etching treatment on the heavy metal layer 120.
Specifically, a single cross structure may be formed, or a double cross structure may be formed as shown in series, with corresponding electrodes 161 (162, 163) provided at the outer ends of the cross structure for electrical connection and measurement. The leftmost electrode 161 in the transverse direction is, for example, an input electrode, the rightmost electrode 162 on the opposite side to the electrode 161 is grounded, the other group of longitudinal electrodes 163 perpendicular to the transverse electrodes 161, 162 in the cross structure is, for example, an output electrode, for example, a rectangular pulse current I is input to the electrode 161, and an output signal is obtained by detecting an abnormal hall voltage of the electrode 163.
Fig. 3 is a schematic measurement diagram of a logic device according to an embodiment of the present invention, an input current I, for example, a rectangular pulse is connected to one end of the heavy metal layer 120, the other end of the heavy metal layer 120 is grounded, and an input voltage V is applied to the oxide layer 150, so that a potential difference is formed between the oxide layer 150 and the heavy metal layer 120, and an electric field is regulated.
In particular, oxide interfaces have a large effect on spin-orbit coupling, and different degrees of oxidation can change the polarity of the electric field effect on magnetic anisotropy. By varying the degree of oxidation of the oxide layer 150 (the degree of oxidation of the multiferroic interface), the spin-orbit coupling signal can be effectively modulated. The magnetic anisotropy effect is changed by changing the oxidation state of the oxide layer 150 (at the interface of the multiferroic layer 140 and the oxide layer 150). For the under-oxidized oxide layer 150 (under-oxidized interface), the forward voltage reduces the magnetic anisotropy; the opposite is true for the peroxo oxide layer 150 (peroxo interface), the forward voltage enhances the magnetic anisotropy. This dependence of the magnetic anisotropy effect on voltage allows us to form different kinds of logic devices (i.e., n-type or p-type spin logic devices) by controlling the oxidation state of the oxide layer 150, and further to realize the complementary functions of the logic devices by combining the two spin logic devices.
Further, referring to fig. 2, an input current I is connected to an electrode 161 at an outer end of the cross structure of the heavy metal layer 120, the electrode 162 is grounded, the electrode 163 is used as an output electrode, and an output signal of the logic device is obtained by detecting an abnormal hall voltage of the electrode 163.
Fig. 4a is an experimental characteristic diagram of a first embodiment of the logic device according to the present invention, in which the oxide layer 150 of the logic device according to the first embodiment is in a peroxidized state, specifically, the oxide layer 150 of the embodiment is made of an oxide of Al, the oxidation time t OX of Al is 120 seconds, and fig. 4a is an R xy -I curve of the logic device, in which the input voltage V of the oxide layer 150 can be changed between +3v and-3V, for example.
When the input voltage V is +3v or slightly greater than +3v, the spin orbit coupling critical flip current I 11 of the logic device of the first embodiment is 14mA, and when the input voltage V is less than or equal to-3V, the critical flip current I 21 is 11mA.
When the input current I is 12mA, the input current I is between the critical switching currents of spin orbit coupling corresponding to the two voltages. When v= +3v, the spin orbit coupling resistance signal R XY (output signal) does not flip with the change of direction of the input current I; when v= -3V, the spin-orbit coupling signal is flipped as the input current I changes direction, so the logic device of this first embodiment can be seen as a p-type spin logic device.
As can be seen from the characteristic diagram, the logic device of the first embodiment may be referred to as a p-type spin logic device by making the input current I be between the critical switching currents (i.e., I 21＜I＜I11) of the spin-orbit coupling corresponding to the two voltages, and when the input current I is greater than I 21 and less than I 11, the input current I is the normal operating current of the p-type logic device.
Further, as shown in connection with FIG. 3, since the resistor R xy reflects the component of the magnetic moment in the ferromagnetic layer 130 in the longitudinal z-direction, the magnetic moment of the ferromagnetic layer 130 in the logic device can be initialized with the external magnetic field such that the initial magnetic moment is oriented upward. Fig. 4b, a truth table of the logic device of the first embodiment in this initial state, obtains its output signal R p by detecting the abnormal hall voltage of the electrode 163 of the heavy metal layer 120 according to the direction (positive and negative) transition of the input current I and the input voltage V.
Fig. 5a is an experimental characteristic diagram of a second embodiment of the logic device according to the present invention, in which the oxide layer 150 of the logic device according to the second embodiment is in an underoxidized state, specifically, the oxide layer 150 in this embodiment is made of an oxide of Al, and the oxidation time t OX of Al is 30 seconds, for example, and fig. 5a is an R xy -I curve of the logic device, in which the input voltage V of the oxide layer 150 can be changed between +3v and-3V, for example.
When the input voltage V is +3v or slightly greater than +3v, the spin orbit coupling critical flip current I 12 of the logic device of the second embodiment is 11mA, and when the input voltage V is less than or equal to-3V, the critical flip current I 22 is 14mA.
When the input current I is 12mA, the input current I is between the critical switching currents of spin orbit coupling corresponding to the two voltages. When v= +3v, the spin orbit coupling resistance signal R XY (output signal) turns over as the input current I changes direction; when v= -3V, the spin-orbit coupling signal does not flip with the change of direction of the input current I, so the logic device of this second embodiment can be seen as an n-type spin logic device.
As can be seen from the characteristic diagram, the logic device of the first embodiment may be referred to as a p-type spin logic device by making the input current I be between the critical switching currents of the spin orbit coupling corresponding to the two voltages (i.e., I 12＜I＜I22), and when the input current I is greater than I 12 and less than I 22, the input current I is the normal operating current of the n-type logic device.
Likewise, the initial magnetic moment of the ferromagnetic layer 130 in the logic device of this second embodiment is oriented upward. Fig. 5b, a truth table for the logic device of the second embodiment in this initial state, obtains its output signal R n by detecting the abnormal hall voltage of the electrode 163 of the heavy metal layer 120 according to the direction (positive and negative) transition of the input current I and the input voltage V.
FIG. 6 is a flow chart of a logic device according to an embodiment of the present invention, and a method for fabricating the logic device includes:
s10, cleaning a substrate;
S20, preparing a heavy metal layer;
s30, processing the heavy metal layer to form a cross structure;
s40, preparing an electrode at the outer side end of the cross structure;
S50, preparing a ferromagnetic layer;
s60, preparing a multiferroic layer;
s70, preparing an oxide layer;
Wherein, when preparing the oxide layer, the oxide layer can be in a peroxidized state or a underoxidized state by controlling the oxidation state of the oxide layer so as to form a p-type logic device or an n-type logic device respectively.
In the following manufacturing method, metal Ta is selected as a material of the heavy metal layer 120, pt is selected as a material of the electrode, co 32Fe48B20 is selected as a material of the ferromagnetic layer, biFeO 3 is selected as a material of the multiferroic layer, and an oxide of Al is selected as a material of the oxide layer. The choice of materials for the layers is merely exemplary, and of course, other alternative materials mentioned in the description above may be used, as well as the logic devices described in the present invention may be made by the same or similar methods.
S10, cleaning the substrate. The substrate 110 is cleaned using an ultrasonic cleaner. Immersing the substrate 110 in acetone and methanol for ultrasonic cleaning for 10min each time, and cleaning for three times; immersing the substrate 110 in alcohol for ultrasonic cleaning; and finally, ultrasonically cleaning the glass by deionized water. The substrate 110 was blow-dried with a nitrogen gun for the next step.
S20, preparing a metal layer. And preparing a heavy metal layer 120 on the cleaned substrate, wherein the heavy metal layer 120 is made of metal Ta, specifically, a metal Ta film with the thickness of about 5nm is grown on the substrate through magnetron sputtering, and further, the whole magnetron sputtering is completed through four steps of lofting, vacuumizing, electromagnetic sputtering and sampling in sequence. Parameters involved in magnetron sputtering include: the vacuum degree of the background of the sputtering chamber is higher than 10 -5 Pa, the temperature of the electromagnetic sputtering is room temperature, and the sputtering air pressure is 0.1-1.5Pa.
S30, processing the heavy metal layer to form a cross structure. The prepared heavy metal layer 120 was subjected to electron beam exposure using a negative photoresist, then subjected to ultrasonic cleaning, then subjected to photoresist coating and heating, respectively, subjected to electron beam exposure using an electron beam direct writing system and development and fixation, and subjected to argon ion beam etching to remove the part not protected by the photoresist, and finally, subjected to acetone soaking and ultrasonic cleaning to remove the negative photoresist, leaving a double cross structure (hall bar structure) of 80×10μm as shown in fig. 2.
S40 an electrode is prepared at the outer end of the cross structure (double cross structure). The electrode is manufactured by adopting a mode of electron beam exposure and magnetron sputtering, specifically, if Pt is selected as an electrode material, ultrasonic cleaning is carried out on the semi-finished product after the step S30, then gluing and heating are respectively carried out, an electron beam direct writing system is used for carrying out electron beam exposure and development fixation, then acetone soaking and ultrasonic cleaning are used for removing a positive photoresist part of an exposure part, and pits are left for growing the electrode; electrode landfill is carried out by utilizing a magnetron sputtering method, and the whole magnetron sputtering is completed through four steps of lofting, vacuumizing, electromagnetic sputtering and sampling in sequence, so that corresponding electrodes are formed.
Specifically, parameters involved in magnetron sputtering include: the vacuum degree of the background of the sputtering chamber is higher than 10 -5 Pa, the temperature of the electromagnetic sputtering is room temperature, the sputtering air pressure is 0.1-1.5Pa, and the thickness of the film of the prepared Pt electrode is about 5nm. Finally, the semi-finished product filled with the electrode is soaked in acetone and cleaned by ultrasonic to remove redundant photoresist and insulating layers, and a cross structure of the heavy metal layer 120 and the Pt electrode are left.
S50, preparing a ferromagnetic layer. And (3) growing a Co 32Fe48B20 film with the thickness of about 1nm on the semi-finished product after the step S40 by magnetron sputtering, and finishing the whole magnetron sputtering by four steps of lofting, vacuumizing, electromagnetic sputtering and sampling. Parameters involved in magnetron sputtering include: the background vacuum degree of the sputtering chamber is higher than 10 -5 Pa, the sputtering temperature is room temperature, and the sputtering air pressure is 0.1-1.5Pa.
S60, preparing a multiferroic layer. The multiferroic layer is formed by adopting laser pulse deposition, and specifically, the multiferroic layer is prepared through five steps of lofting, vacuumizing, heating, laser pulse emission and cooling sampling, wherein the thickness of the multiferroic layer is about 2nm. Parameters involved in preparing the multiferroic layer include: the background vacuum degree of the deposition chamber is higher than 10 -4 Pa, the oxygen pressure is 1Pa-10Pa during deposition, the deposition temperature is 700-750 ℃, the energy of laser pulse is 100mJ-400mJ during deposition, and the laser frequency is 1-5Hz.
The logic device can provide a weak bias magnetic field by itself without providing an external magnetic field for magnetic storage.
S70, preparing an oxide layer; and growing metal Al with the thickness of about 1.5nm on the multiferroic layer by magnetron sputtering, and completing the whole magnetron sputtering step by four steps of lofting, vacuumizing, electromagnetic sputtering and sampling. Basic parameters in the magnetron sputtering process include: the background vacuum degree of the sputtering chamber is higher than 10 -5 Pa, the electromagnetic sputtering temperature is room temperature, the sputtering air pressure is 0.1-1.5Pa, after metal Al grows on the multiferroic layer, the grown metal Al is exposed to O 2 plasma species under the pressure of 4Pa and the power of 30W, so that oxide layers 150 with different oxidation degrees are formed according to different oxidation times tox.
Further, since the resistance R xy of the heavy metal layer 120 reflects the component of the magnetic moment in the ferromagnetic layer 130 in the longitudinal z-direction, the magnetic moment of the ferromagnetic layer 130 in the logic device can be initialized by using the external magnetic field, so that the initial magnetic moment is directed upward or downward.
The logic device can regulate the magnetic moment direction of the ferromagnetic layer by using the input voltage V without external magnetic field, and can initialize the signal of the logic device by applying the input voltage V; and the logic device utilizes the electromagnetic spin orbit coupling effect, and spin orbit coupling critical current is regulated and controlled through an electric field, so that the energy consumption of the logic device can be effectively reduced.
Fig. 7a and 7b are schematic diagrams of a first embodiment and a second embodiment of the logic assembly according to the present invention, respectively, as shown in fig. 7a, a p-type logic device having a peroxidized oxide layer 151 is connected in series with an n-type logic device having an underoxidized oxide layer 152, specifically, heavy metal layers and oxide layers of the two logic devices are respectively connected in series, the p-type logic device is in front, the n-type logic device is in rear, an electrode 162 of the heavy metal layer 120 of the p-type logic device opposite to an input electrode 161 is electrically connected to the input electrode 161 of the n-type logic device, and the oxide layers of the p-type logic device and the n-type logic device are both connected to an input voltage V, wherein one logic device can be selectively controlled by changing the direction of the input voltage V.
Specifically, when the initial magnetic moment directions of the ferromagnetic layers 130 of the two logic devices are the same and both are upward, when the input current I (e.g., i=12ma) satisfies both the normal operation current of the p-type spin logic device and the normal operation current of the n-type spin logic device, the state of the p-type logic device or the state of the n-type logic device can be selectively controlled by the input current I by changing the direction of the input voltage V, thereby realizing the complementary function of the logic device, and correspondingly, the logic component has the logic complementary function.
As shown in fig. 7b, a p-type logic device with a peroxide oxide layer 151 is also connected in series with an n-type logic device with an under-oxide layer 152 in a similar manner to fig. 7a, but with the n-type logic device in this embodiment being preceded and the p-type logic device being followed by the ferromagnetic layers 130 of both logic devices having the same initial magnetic moment orientation and both magnetic moments facing downward, and the corresponding logic complementary function is also achieved in this embodiment.
In the illustration, only one p-type logic device and one n-type logic device are connected in series to form a logic assembly, however, the logic assembly can also be formed by connecting a plurality of p-type logic devices and a plurality of n-type logic devices in series in a similar manner, the arrangement sequence of the two logic devices can also be adjusted according to the situation, and further, the initial direction of the magnetic moment of the ferromagnetic layer 130 can also be adjusted correspondingly according to the requirement.
Fig. 8 is a truth table corresponding to a logic device according to an embodiment of the present invention, where the output of an n-type logic device and a p-type logic device under different input conditions are recorded when the initial magnetic moment direction (∈) of the ferromagnetic layer 130 is upward (∈) and the initial magnetic moment direction is downward (∈) respectively.
In comparison of the first and second embodiments of the logic components shown in fig. 7a and 7b, and in combination with the truth table of fig. 8, in the first embodiment of the logic component shown in fig. 7a, when the input current I IN (for example, I IN =12 mA) satisfies both the normal operating current of the p-type spin logic device and the normal operating current of the n-type spin logic device, the output of a single logic device in the component can be realized as 0 only when the input current I IN is reverse, specifically, when I IN =12 mA and is reverse, the voltage V is also reverse, the corresponding output R p＝0,Rn =1, when I IN =12 mA and is reverse, the corresponding output R p＝1,Rn =0 when the voltage V is forward, and the remaining I IN =12 mA, and the corresponding outputs R p and R n are both 1 regardless of the forward and reverse directions of the voltage V. The logic component of this first embodiment can control the input current and input voltage so that a logic device of a specified type in the component outputs 0.
In a second embodiment of the logic component as shown in fig. 7b, when the input current I IN (e.g. I IN = 12 mA) satisfies both the normal operating current of the p-type spin logic device and the normal operating current of the n-type spin logic device, the output of a single logic device in the component can only be achieved 1 when the input current I IN is forward, in particular, when I IN = 12mA and is forward, the voltage V is reverse, the corresponding output R p＝1,Rn = 0, when I IN = 12mA and is forward, the voltage V is also forward, the corresponding output R p＝0,Rn = 1, and the remaining I IN = 12mA, both the corresponding outputs R p and R n are 0, regardless of the forward and reverse direction of the voltage V. The logic component of this second embodiment can control the input current and input voltage so that the specified type of logic device in the component outputs 1.
Further, the truth table shown in fig. 8 also lists the initialization of the logic device and the information erasing operation, initialization and information erasing: when the input current I (i=15ma, for example) satisfies the normal operating current greater than that of both the p-type spin logic device and the n-type spin logic device, both devices are simultaneously controlled regardless of whether the voltage is in the forward direction or the reverse direction, so that the logic devices are initialized and/or erased by the input current, and the corresponding logic components also allow all information in each logic device to be initialized and erased simultaneously.
The logic device provided by the invention has the following advantages or beneficial effects: the substrate is made of flexible materials such as mica monocrystalline slices, polyether sulfone (PES), polyethylene terephthalate (PI) and the like, so that the corresponding logic device has the advantages of portability, extrusion resistance, flexibility and the like compared with the traditional device;
the logic device can adjust the oxidation state of its oxide layer as needed to form a desired n-type or p-type logic device to perform n-type or p-type logic functions. The manufacturing method corresponding to the logic device has strong practicability.
Further, the logic component formed by combining the two logic devices can directly execute the n-type logic function and the p-type logic function, integrates the n-type logic function and the p-type logic function, has the functions of initializing and erasing the information of the two devices at the same time, is convenient and quick to operate, and further enhances the reliability due to the logic complementarity of the logic component.
Based on the logic component provided by the invention, the logic component not only has a complementary logic operation function, but also has an information initialization or erasure function, and has a wide application prospect in the field of multifunctional or programmable spin logic devices.
The invention realizes the regulation and control of the electric field on the spin orbit coupling critical current by adopting the multiferroic material, so that the corresponding logic device can effectively regulate and control the spin orbit coupling signal at room temperature.
The effect of the logic device is changed by utilizing interfaces (oxide layers) with different oxidation states, so that the regulation degree of positive and negative of an input voltage (electric field) to spin orbit coupling critical current is different, thereby achieving the n-type or p-type logic operation function, obtaining a light, portable and low-power-consumption logic device, and further manufacturing a memory device capable of rapidly reading and writing and high in storage density based on the logic device.
The above-described embodiments are merely examples of the present invention, and although the embodiments of the present invention and the accompanying drawings are disclosed for illustrative purposes, it will be understood by those skilled in the art that: various alternatives, variations and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Accordingly, the invention should not be limited to the disclosure of the embodiments and drawings.
Claims (9)
1. A logic device, comprising:
the substrate is used for bearing the logic device and is a flexible substrate;
the heavy metal layer is positioned on the substrate and has the thickness of 3-10 nanometers;
The ferromagnetic layer is positioned on the heavy metal layer and has the thickness of 1-30 nanometers;
The multiferroic layer is positioned on the ferromagnetic layer and has the thickness of 2-200 nanometers;
An oxide layer, which is positioned on the multiferroic layer and has a thickness of 1-10 nanometers;
The heavy metal layer comprises at least one cross structure, a corresponding electrode is arranged at the outer side end of the cross structure, the resistance of the heavy metal layer is changed by changing the direction of voltage applied between the oxide layer and the heavy metal layer, the resistance of the heavy metal layer is used for reflecting the component of the magnetic moment in the ferromagnetic layer in the longitudinal direction, and the magnetic moment of the ferromagnetic layer is initialized by utilizing an external magnetic field; the oxide layer is made to be in a peroxidized or underoxidized state by controlling the oxidation state of the oxide layer to form a p-type logic device or an n-type logic device, respectively.
2. The logic device according to claim 1, wherein the outer end of the cross structure includes an input electrode, the other end electrode opposite to the input electrode is grounded, and the other end electrode of the cross structure in a direction perpendicular to the input electrode is an output terminal from which an abnormal hall voltage is detected as an output signal.
3. The logic device of claim 2 wherein the oxide layer is in a peroxidized state, the oxide layer has a spin-orbit coupling threshold current of I 11 when a positive voltage is applied between the oxide layer and the heavy metal layer, and the oxide layer has a spin-orbit coupling threshold current of I 21 when a negative voltage is applied between the oxide layer and the heavy metal layer, wherein I 11 is greater than I 21.
4. A logic device according to claim 3, wherein the input current I is supplied to the input electrode, and wherein the output signal does not change with a change in direction of the input current I at a positive voltage and reverses with a change in direction of the input current I at a negative voltage when I 21＜I＜I11 is applied.
5. The logic device of claim 2 wherein the oxide layer is in an underoxidized state, the oxide layer has a spin-orbit coupling threshold current of I 12 when a positive voltage is applied between the oxide layer and the heavy metal layer, and the oxide layer has a spin-orbit coupling threshold current of I 22 when a negative voltage is applied between the oxide layer and the heavy metal layer, wherein I 12 is less than I 22.
6. The logic device of claim 5 wherein the input current I is applied to the input electrode, and wherein the output signal is inverted as the direction of the input current I changes at a positive voltage and is unchanged as the direction of the input current I changes at a negative voltage when I 12＜I＜I22 is applied.
7. A logic assembly, comprising: at least 2 logic devices as claimed in claim 1; the logic device comprises two types of oxide layers, namely a peroxidation state and an underoxidation state, wherein the two types of logic devices are connected in series, the two types of heavy metal layers and the oxide layers of the logic devices are respectively connected in series, and at least one type of logic devices is controlled by changing the voltage direction selectivity between the oxide layers and the heavy metal layers.
8. A method of fabricating a logic device, the method comprising:
Cleaning the substrate;
preparing a heavy metal layer on the cleaned substrate;
photoetching and etching the heavy metal layer to form a cross structure;
corresponding electrodes are arranged at the outer side ends of the cross structures;
preparing a ferromagnetic layer on the heavy metal layer;
preparing a multiferroic layer on the ferromagnetic layer;
preparing an oxide layer on the multiferroic layer;
When an oxide layer is prepared on a multiferroic layer, the oxide layer is in a peroxidized state or an underoxidized state by controlling the oxidation state of the oxide layer so as to respectively form a p-type logic device or an n-type logic device, the resistance of the heavy metal layer is changed by changing the direction of voltage applied between the oxide layer and the heavy metal layer, the resistance of the heavy metal layer is used for reflecting the component of the magnetic moment in the ferromagnetic layer in the longitudinal direction, and the magnetic moment of the ferromagnetic layer is initialized by using an external magnetic field.
9. The method of manufacturing a logic device according to claim 8,
The substrate is made of at least one material selected from polyethersulfone, polyethylene terephthalate, polydimethylsiloxane, polypropylene hexamethylene diester and mica;
The heavy metal layer is made of at least one material of Pt, W and Ta;
the electrode is made of at least one material of Pt, W and Ta;
The ferromagnetic layer is made of at least one of CoFeB, coFe, niFe, feCrCo, feCoV materials;
The multiferroic layer includes at least one of BiFeO3、GaFeO3、BiCrO3、TbMnO3、Bi2FeCrO6、BiMnO3、HoMn2O5、HoMn2O5、YbMn2O5、ScMn2O5、YMn2O5、GaMn2O5、DyMn2O5、ErMn2O5、HoMnO3、YbMnO3、ScMnO3、YMnO3、GaMnO3、DyMnO3、ErMnO3;
The material of the oxide layer is at least one of an oxide of Al, an oxide of Si and an oxide of Mg.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910447226.9A CN110265479B (en) | 2019-05-27 | 2019-05-27 | Logic device, logic assembly and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910447226.9A CN110265479B (en) | 2019-05-27 | 2019-05-27 | Logic device, logic assembly and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110265479A CN110265479A (en) | 2019-09-20 |
| CN110265479B true CN110265479B (en) | 2024-05-31 |
Family
ID=67915544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910447226.9A Active CN110265479B (en) | 2019-05-27 | 2019-05-27 | Logic device, logic assembly and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110265479B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113611795B (en) * | 2021-06-15 | 2023-09-26 | 北京航空航天大学 | Vertically stacked magnetic spin logic device and method for implementing information access |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006237304A (en) * | 2005-02-25 | 2006-09-07 | Osaka Industrial Promotion Organization | Ferromagnetic conductor material, its manufacturing method, magnetoresistive element and field effect transistor |
| CN102856488A (en) * | 2011-09-19 | 2013-01-02 | 中国科学院物理研究所 | Logic device based on reversible electroresistance effects |
| JP2013236014A (en) * | 2012-05-10 | 2013-11-21 | Toshiba Corp | Multivalued non-volatile semiconductor memory |
| WO2014207818A1 (en) * | 2013-06-25 | 2014-12-31 | 株式会社日立製作所 | Spin wave circuit |
| CN106531884A (en) * | 2016-12-23 | 2017-03-22 | 中国科学院半导体研究所 | Voltage control magnetic random access memory unit, memory and logic device formed from memory unit |
| CN108735891A (en) * | 2018-05-25 | 2018-11-02 | 叶建国 | A kind of memory device and its manufacturing method |
| CN109036485A (en) * | 2017-06-09 | 2018-12-18 | 桑迪士克科技有限责任公司 | The memory cell of erect spin track torque magnetic random access memory |
| CN210403738U (en) * | 2019-05-27 | 2020-04-24 | 叶建国 | Logic device and logic assembly |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005043574A1 (en) * | 2005-03-30 | 2006-10-05 | Universität Duisburg-Essen | Magnetoresistive element, in particular memory element or Lokikelement, and methods for writing information in such an element |
| US10833249B2 (en) * | 2017-09-18 | 2020-11-10 | Centre National De La Recherche Scientifique | Magnetic memory cell of current programming type |
-
2019
- 2019-05-27 CN CN201910447226.9A patent/CN110265479B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006237304A (en) * | 2005-02-25 | 2006-09-07 | Osaka Industrial Promotion Organization | Ferromagnetic conductor material, its manufacturing method, magnetoresistive element and field effect transistor |
| CN102856488A (en) * | 2011-09-19 | 2013-01-02 | 中国科学院物理研究所 | Logic device based on reversible electroresistance effects |
| JP2013236014A (en) * | 2012-05-10 | 2013-11-21 | Toshiba Corp | Multivalued non-volatile semiconductor memory |
| WO2014207818A1 (en) * | 2013-06-25 | 2014-12-31 | 株式会社日立製作所 | Spin wave circuit |
| CN106531884A (en) * | 2016-12-23 | 2017-03-22 | 中国科学院半导体研究所 | Voltage control magnetic random access memory unit, memory and logic device formed from memory unit |
| CN109036485A (en) * | 2017-06-09 | 2018-12-18 | 桑迪士克科技有限责任公司 | The memory cell of erect spin track torque magnetic random access memory |
| CN108735891A (en) * | 2018-05-25 | 2018-11-02 | 叶建国 | A kind of memory device and its manufacturing method |
| CN210403738U (en) * | 2019-05-27 | 2020-04-24 | 叶建国 | Logic device and logic assembly |
Non-Patent Citations (1)
| Title |
|---|
| Electric field control of deterministic current-induced magnetization switching in a hybrid ferromagnetic/ferroelectric structure;Cai, Kaiming等;《NATURE MATERIALS》;20170731;第16卷(第7期);第1-15页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110265479A (en) | 2019-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6438532B2 (en) | Magnetic tunnel junction device including spin filter structure | |
| CN100454599C (en) | Spin-injection field effect transistor, magnetic ram, and reconfigurable logical circuit | |
| US7764538B2 (en) | Magnetic memory and method for writing to magnetic memory | |
| US20100027330A1 (en) | Magnetic memory device and method for reading magnetic memory cell using spin hall effect | |
| JP2007103663A (en) | Magnetic element, recording regenerating element, logical operation element and logical computer | |
| JP2006179891A (en) | Mram of voltage controlled magnetization reversal writing type and method of writing and reading information | |
| WO2012064395A1 (en) | Non-volatile magnetic tunnel junction transistor | |
| JP5017135B2 (en) | Semiconductor device | |
| Portal et al. | An overview of non-volatile flip-flops based on emerging memory technologies | |
| CN108512545B (en) | Reconfigurable logic gate based on magnetic sigecum | |
| CN105514260A (en) | Spinning logic device and electronic device comprising same | |
| Endoh et al. | A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching | |
| US20100085805A1 (en) | Magnetic random access memory (mram) utilizing magnetic flip-flop structures | |
| JP2019165099A (en) | Magnetic storage device | |
| CN110265479B (en) | Logic device, logic assembly and manufacturing method thereof | |
| KR102302781B1 (en) | Spin Logic Device Based on Spin-Charge Conversion and Spin Logic Array | |
| US11417453B2 (en) | Electronic device, digital port, analog component, and method for generating a voltage | |
| JP2011175987A (en) | Spin valve element and storage device | |
| CN110335938B (en) | Logic device and method of manufacturing the same | |
| CN210403738U (en) | Logic device and logic assembly | |
| JP5201489B2 (en) | Logic circuit | |
| Wang et al. | Spintronic devices for low energy dissipation | |
| US10644227B2 (en) | Magnetic tunnel diode and magnetic tunnel transistor | |
| WO2007105284A1 (en) | Resistance-varying type storage element, and method for manufacturing the resistance-varying type storage element | |
| CN112863566A (en) | Storage array, memory, preparation method and writing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |