CN210403738U - Logic device and logic assembly - Google Patents
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- CN210403738U CN210403738U CN201920774015.1U CN201920774015U CN210403738U CN 210403738 U CN210403738 U CN 210403738U CN 201920774015 U CN201920774015 U CN 201920774015U CN 210403738 U CN210403738 U CN 210403738U
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Abstract
The utility model provides a logic device, this logic device includes: a substrate, a heavy metal layer, a ferromagnetic layer, a multiferroic layer, and an oxide layer; the heavy metal layer comprises a cross structure, wherein the outer end of the cross structure is provided with a corresponding electrode, and the resistance of the heavy metal layer is changed by changing the direction of an electric field applied between the oxide layer and the heavy metal layer. Specifically, the substrate is a flexible substrate, and has the advantages of extrusion resistance, flexibility and the like, and the device realizes the regulation and control of the spin-orbit coupling critical current by the electric field at room temperature through a multiferroic material, so that the spin-orbit coupling signal is effectively regulated and controlled. The effect of the logic device is changed by using different oxidation state interfaces (oxide layers), so that the regulation and control degrees of the input voltage on the spin-orbit coupling critical current are different, thereby achieving the n-type or p-type logic operation function, obtaining the logic device with light weight, portability and low power consumption, and combining the logic devices to obtain the logic component integrating the n-type and p-type logic functions.
Description
Technical Field
The utility model relates to a microelectronics technical field specifically relates to a logic device based on many ferromagnetic electricity coupling and spin orbit coupling effect and manufacturing method thereof.
Background
Conventional electronics are based on the charge properties of electrons, and people control the charge of electrons to realize information storage and logic processing. However, as electronic devices are gradually miniaturized, the effects of quantum effects, energy loss, and the like are more and more obvious, and the conventional electronic devices cannot meet the development requirements.
The spintronic device has the advantages of non-volatility, low energy consumption, high integration and the like, so that the spintronic device is developed at a rapid speed, and the characteristics of the spintronic device, such as high computing power, low energy consumption and the like in information processing, are incomparable with the traditional semiconductor electronic device. The spin orbit coupling can realize the control of magnetic moment by using the generated torque, and can realize the spin flip control under small size without generating spin polarized current by using a special magnetic material. Spin-orbit torque (spin-orbit coupling) based spin logic devices have particular advantages in terms of logic configuration, which can reconfigure logic operations. Spin-orbit coupling is easily controlled in combination with the voltage-controlled magnetic anisotropy (VCMA) effect. The traditional spin orbit coupling regulation depends on a magnetic field generated by current, spin torque and the like, which require higher current density, thereby generating a large amount of energy consumption. The multiferroic material can use an electric field to regulate and control spin-orbit coupling, can effectively reduce energy consumption, and has huge potential application prospects in the aspects of information storage, spin electronics and the like.
In view of this, the present invention provides a logic device and a method for manufacturing the same, which is light, portable, low in power consumption and good in stability.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a logic device based on many ferromagnetic electricity coupling and spin orbit coupling effect to solve the not enough and high scheduling problem of energy consumption of logic device pliability among the prior art.
In one aspect, the utility model provides a logic device, a serial communication port, include:
the substrate is used for bearing the logic device and is a flexible substrate;
the heavy metal layer is positioned on the substrate and has the thickness of 3-10 nanometers;
a ferromagnetic layer on the heavy metal layer and having a thickness of 1-30 nm;
a multiferroic layer on the ferromagnetic layer having a thickness of 2-200 nanometers;
the oxide layer is positioned on the multiferroic layer and has the thickness of 1-10 nanometers;
the heavy metal layer comprises at least one cross structure, corresponding electrodes are arranged at the outer side ends of the cross structures, and the resistance of the heavy metal layer is changed by changing the direction of voltage applied between the oxide layer and the heavy metal layer.
Preferably, the oxide layer is in one of a peroxide state or an underoxidized state.
Preferably, the outer end of the cross structure includes an input electrode, and the other end electrode opposite to the input end is grounded, and the other end electrode of the cross structure in the direction perpendicular to the input electrode is an output end, and the abnormal hall voltage is detected from the output end as an output signal.
Preferably, the initial magnetic moment direction of the ferromagnetic layer is up or down perpendicular to the ferromagnetic layer plane.
Preferably, the oxide layer is in a peroxide state, and when a forward voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the over-oxide layer is I11When negative voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the over-oxide layer is I21In which I11Is greater than I21。
Preferably, an input current I is applied to the input electrode when I21＜I＜I11When the voltage is positive, the output signal is not changed along with the change of the direction of the input current I, and when the voltage is negative, the output signal is not changed along with the change of the direction of the input current IThe output signal is inverted with the change of the direction of the input current I.
Preferably, the peroxide layer is in an underoxidized state, and when a forward voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the over-oxide layer is I12When negative voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the over-oxide layer is I22In which I12Is less than I22。
Preferably, an input current I is applied to the input electrode when I12＜I＜I22At positive voltage, the output signal is reversed with the change of the direction of the input current I, and at negative voltage, the output signal is unchanged with the change of the direction of the input current I.
According to another aspect of the present invention, there is provided a logic assembly, including: at least 2 of the above logic devices; the logic device comprises an oxide layer in a peroxide state and an oxide layer in an underoxide state, the two logic devices are connected in series, the heavy metal layer and the oxide layer of the two logic devices are respectively connected in series, and at least one of the two logic devices is controlled by changing the voltage direction selectivity between the oxide layer and the heavy metal layer.
Preferably, the initial magnetic moments of the ferromagnetic layers of both of the logic devices are in the same or opposite directions.
According to another aspect of the present invention, there is provided a method for manufacturing a logic device, the method comprising:
cleaning the substrate;
preparing a heavy metal layer on the cleaned substrate;
photoetching and etching the heavy metal layer to form a cross structure;
arranging corresponding electrodes at the outer ends of the cross structures;
preparing a ferromagnetic layer on the heavy metal layer;
preparing a multiferroic layer on the ferromagnetic layer;
preparing an oxide layer on the multiferroic layer;
when the oxide layer is prepared on the multiferroic layer, the oxide layer can be in a peroxide state or an underoxide state by controlling the oxidation state of the oxide layer so as to form a p-type logic device or an n-type logic device respectively.
Preferably, the substrate is made of at least one material selected from polyether sulfone (PES), polyethylene terephthalate (PI), polyethylene terephthalate (PET), Polydimethylsiloxane (PDMS), polypropylene adipate (PPA) and Mica (Mica);
the heavy metal layer is made of at least one of Pt, W and Ta;
the electrode is made of at least one material of Pt, W and Ta;
the ferromagnetic layer is made of at least one of CoFeB, CoFe, NiFe, FeCrCo and FeCoV;
the multiferroic layer comprises BiFeO3、GaFeO3、BiCrO3、TbMnO3、Bi2FeCrO6、BiMnO3、HoMn2O5、HoMn2O5、YbMn2O5、ScMn2O5、YMn2O5、GaMn2O5、DyMn2O5、ErMn2O5、HoMnO3、YbMnO3、ScMnO3、YMnO3、GaMnO3、DyMnO3、ErMnO3At least one of;
the material of the oxide layer is at least one of Al oxide, Si oxide and Mg oxide.
The utility model provides a logic device has following advantage or beneficial effect: by adopting the flexible material to manufacture the substrate, the corresponding logic device has the advantages of more portability, extrusion resistance, flexibility and the like compared with the traditional device; the logic device can adjust the oxidation state of the oxide layer according to the requirement, thereby forming the required n-type or p-type logic device to execute the n-type or p-type logic function, thereby obtaining the logic device with light weight, portability and low power consumption.
Further, the utility model discloses still provide a logic component that is formed by the combination of above-mentioned two kinds of logic devices, it can directly carry out n type, p type logic function, collects n type, p type logic function in an organic whole to initialize and erase the function when having two kinds of device information, and convenient operation is swift, and logic component's logical complementarity has also further strengthened its reliability.
Based on the utility model provides a logic assembly, it not only has complementary logical operation function, and information initialization or erasure function have wide application prospect in multi-functional or programmable spin logic device field in addition.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a logic device according to an embodiment of the present invention;
fig. 2 is a top view of a heavy metal layer of a logic device according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating measurement of a logic device according to an embodiment of the present invention;
fig. 4a is an experimental characteristic diagram of the first embodiment of the logic device of the present invention;
fig. 4b is a truth table of the first embodiment of the logic device of the present invention;
fig. 5a is an experimental characteristic diagram of a second embodiment of the logic device of the present invention;
fig. 5b is a truth table of a second embodiment of the logic device of the present invention;
fig. 6 is a flow chart illustrating a manufacturing process of a logic device according to an embodiment of the present invention;
fig. 7a is a schematic diagram of a first embodiment of the logic assembly of the present invention;
fig. 7b is a schematic diagram of a second embodiment of the logic assembly of the present invention;
fig. 8 is a truth table of logic elements according to an embodiment of the present invention.
Detailed Description
The following disclosure provides many different embodiments or examples for implementing different features of the application. Specific embodiments of components or arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention.
Moreover, in the description and claims, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a sequential, chronological, hierarchical or any other manner of ordering, it being understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
It is to be noticed that the term 'comprising', used in the claims, should not be interpreted as being restricted to the means listed thereafter, and does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the phrase "an apparatus comprising devices a and B" should not be limited to only devices consisting of only components a and B. This means that with respect to the present invention, the relevant components of the device are a and B.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
The present invention may be presented in a variety of forms, some of which are described below.
Fig. 1 is a schematic structural diagram of a logic device according to an embodiment of the present invention, and as shown in fig. 1, the logic device 100 includes: the substrate 110, the heavy metal layer 120, the ferromagnetic layer 130, the multiferroic layer 140, and the oxide layer 150, wherein the heavy metal layer 120 includes a cross structure, and a corresponding electrode is disposed at an outer end of the cross structure.
The entire structure is formed by stacking the substrate 110, the heavy metal layer 120, the ferromagnetic layer 130, the multiferroic layer 140, and the oxide layer 150 in this order from bottom to top, and the heavy metal layer 120, the ferromagnetic layer 130, the multiferroic layer 140, and the oxide layer 150 are all in a thin film shape.
The substrate 110 may be made of Polyethersulfone (PES), polyethylene terephthalate (PI), polyethylene terephthalate (PET), Polydimethylsiloxane (PDMS), polypropylene adipate (PPA), Mica (Mica), or the like, to realize a flexible substrate.
The heavy metal layer 120 may be made of Pt, W, Ta, etc., and formed into a cross structure by photolithography and etching, and corresponding electrodes are disposed at outer ends of the cross structure for electrical connection and measurement, and the thickness of the heavy metal layer is about 3nm to 10 nm.
The ferromagnetic layer 130 may be made of CoFeB, CoFe, NiFe, FeCrCo, FeCoV, etc. with a thickness of about 1nm to about 30 nm.
The multiferroic layer 140 is made of, for example, BiFeO3、GaFeO3、BiCrO3、TbMnO3、Bi2FeCrO6、BiMnO3、HoMn2O5、HoMn2O5、YbMn2O5、ScMn2O5、YMn2O5、GaMn2O5、DyMn2O5、ErMn2O5、HoMnO3、YbMnO3、ScMnO3、YMnO3、GaMnO3、DyMnO3、ErMnO3Etc. materialIs made of at least one material having a thickness of about 2nm to about 200 nm.
The oxide layer 150 may be made of AlOX、SiOX、MgOX(Al oxide, Si oxide, Mg oxide) and the like, wherein the value of X is determined according to the oxidation state (peroxide state or underoxidation state) of the corresponding oxide layer, and the thickness of the oxide layer 150 is about 1nm to 10 nm.
Fig. 2 is a top view of a heavy metal layer of a logic device according to an embodiment of the present invention, as shown in fig. 2, the heavy metal layer 120 is located on the substrate 110, and the heavy metal layer 120 is formed into a cross structure (hall bar structure) by performing photolithography and etching processes.
Specifically, a single cross structure may be formed, or a double cross structure may be formed in series as shown in the drawing, and corresponding electrodes 161(162, 163) are provided at outer ends of the cross structure for electrical connection and measurement. The leftmost electrode 161 in the transverse direction is, for example, an input electrode, the rightmost electrode 162 on the side opposite to the electrode 161 is grounded, and the other set of longitudinal electrodes 163 perpendicular to the cross-shaped transverse electrodes 161 and 162 is, for example, an output electrode, for example, a rectangular pulse current I is input to the electrode 161, and an output signal is obtained by detecting an abnormal hall voltage of the electrode 163.
Fig. 3 is a schematic diagram of a measurement of the logic device according to an embodiment of the present invention, an input current I is connected to one end of the heavy metal layer 120, the input current I is, for example, a rectangular pulse, the other end of the heavy metal layer 120 is grounded, and an input voltage V is applied to the oxide layer 150, so that a potential difference is formed between the oxide layer 150 and the heavy metal layer 120, and an electric field is controlled.
In particular, the oxide interface has a large effect on spin-orbit coupling, and different degrees of oxidation can change the polarity of the effect of the electric field on the magnetic anisotropy. By changing the oxidation degree of the oxide layer 150 (the oxidation degree of the multiferroic interface), the spin-orbit coupling signal can be effectively controlled. The magnetic anisotropy effect is changed by changing the oxidation state of the oxide layer 150 (at the interface of multiferroic layer 140 and oxide layer 150). For an under-oxidized oxide layer 150 (under-oxidized interface), the forward voltage decreases the magnetic anisotropy; the reverse is true for the peroxide oxide layer 150 (peroxide interface), where the forward voltage enhances the magnetic anisotropy. This dependence of the magnetic anisotropy effect on voltage allows one to control the oxidation state of the oxide layer 150 to form different types of logic devices (i.e., n-type or p-type spin logic devices) and further allows the complementary functionality of the logic devices to be achieved by combining the two types of spin logic devices.
Further, referring to fig. 2, an input current I is connected to the electrode 161 at the outer end of the cross structure of the heavy metal layer 120, the electrode 162 is grounded, the electrode 163 serves as an output electrode, and an output signal of the logic device is obtained by detecting an abnormal hall voltage of the electrode 163.
FIG. 4a is a diagram illustrating experimental characteristics of a first embodiment of the logic device according to the present invention, wherein the oxide layer 150 of the logic device of the first embodiment is in a peroxide state, specifically, the oxide layer 150 in this embodiment is made of an oxide of Al, and the oxidation time t of Al isOXE.g., 120 seconds, FIG. 4a is R of the logic devicexyAn I-curve, wherein the input voltage V of the oxide layer 150 may be shifted between +3V and-3V, for example.
When the input voltage V is +3V or slightly more than +3V, the spin-orbit coupling critical switching current I of the logic device of the first embodiment1114mA, and critical flip current I when input voltage V is less than or equal to-3V21And was 11 mA.
When the input current I is 12mA, the input current is between the critical switching currents of the spin-orbit coupling corresponding to the two voltages. When V is +3V, spin orbit coupling resistance signal RXY(output signal) does not flip with the change of direction of the input current I; when V is-3V, the spin-orbit coupling signal is inverted with the direction of the input current I, so the logic device of the first embodiment can be considered as a p-type spin logic device.
From this characteristic diagram, it can be derived that the input current I can be set between the critical switching currents of spin-orbit coupling corresponding to two voltages (i.e. I21＜I＜I11) When the logic device performs logic operation, the logic device of the first embodiment may be referred to as a p-type spin logic device, and when the input current I is greater than the input current II21Is less than I11When the p-type logic device is in the normal working state, the input current I is the normal working current of the p-type logic device.
Further, as shown in FIG. 3, due to the resistance RxyThe component of the magnetic moment in the ferromagnetic layer 130 in the longitudinal z-direction may be used to initialize the magnetic moment of the ferromagnetic layer 130 in the logic device with the initial magnetic moment in the upward direction using an external magnetic field. Fig. 4b is a truth table of the logic device of the first embodiment in the initial state, and the output signal R is obtained by detecting the abnormal hall voltage of the electrode 163 of the heavy metal layer 120 according to the direction (positive and negative) change of the input current I and the input voltage Vp。
FIG. 5a is a diagram illustrating experimental characteristics of a second embodiment of the logic device according to the present invention, wherein the oxide layer 150 of the logic device of the second embodiment is, for example, in an under-oxidized state, specifically, the oxide layer 150 in this embodiment is made of an oxide of Al, and the oxidation time t of Al isOXE.g., 30 seconds, FIG. 5a is R of the logic devicexyAn I-curve, wherein the input voltage V of the oxide layer 150 may be shifted between +3V and-3V, for example.
When the input voltage V is +3V or slightly more than +3V, the spin-orbit coupling critical switching current I of the logic device of the second embodiment1211mA, and critical flip current I when input voltage V is less than or equal to-3V22Is 14 mA.
When the input current I is 12mA, the input current is between the critical switching currents of the spin-orbit coupling corresponding to the two voltages. When V is +3V, spin orbit coupling resistance signal RXY(output signal) flips as the input current I changes direction; when V is-3V, the spin-orbit coupling signal does not flip with the direction of the input current I, so the logic device of the second embodiment can be considered as an n-type spin logic device.
From this characteristic diagram, it can be derived that the input current I can be set between the critical switching currents of spin-orbit coupling corresponding to two voltages (i.e. I12＜I＜I22) When the logic device performs logic operation, the logic device of the first embodiment may be referred to as a p-type spin logic device, and when the input current I is greater than I12Is less than I22In good time and in good timeThe input current I is the normal working current of the n-type logic device.
Likewise, the initial magnetic moment direction of the ferromagnetic layer 130 in the logic device of this second embodiment is upward. Fig. 5b is a truth table of the logic device of the second embodiment in the initial state, and the output signal R is obtained by detecting the abnormal hall voltage of the electrode 163 of the heavy metal layer 120 according to the direction (positive and negative) change of the input current I and the input voltage Vn。
Fig. 6 is a flowchart of a manufacturing method of a logic device according to an embodiment of the present invention, the manufacturing method includes:
s10, cleaning the substrate;
s20, preparing a heavy metal layer;
s30, processing the heavy metal layer to form a cross structure;
s40 preparing electrodes at the outer ends of the cross structures;
s50 preparing a ferromagnetic layer;
s60, preparing a multiferroic layer;
s70 preparing an oxide layer;
when the oxide layer is prepared, the oxide layer can be in a peroxide state or an underoxidation state by controlling the oxidation state of the oxide layer, so as to form a p-type logic device or an n-type logic device respectively.
In the following manufacturing method, Ta is used as the material of the heavy metal layer 120, Pt is used as the material of the electrode, and Co is used32Fe48B20BiFeO is selected as the material of the ferromagnetic layer3As the material of the multiferroic layer, an oxide of Al is selected as the material of the oxide layer. The choice of materials for the layers is merely exemplary, and other alternative materials mentioned above in the description may of course be used, as well as the logic device described in the present invention may be made by the same or similar methods.
S10 cleaning the substrate. The substrate 110 is cleaned using an ultrasonic cleaner. Immersing the substrate 110 in acetone and methanol for ultrasonic cleaning, 10min each time, and cleaning three times in total; then, the substrate 110 is immersed in alcohol for ultrasonic cleaning; and finally, ultrasonically cleaning the substrate by using deionized water. The substrate 110 is blow dried with a nitrogen gun for further processing.
S20 preparing a metal layer. Preparing a heavy metal layer 120 on the cleaned substrate, wherein the heavy metal layer 120 is made of metal Ta, specifically, growing a metal Ta film with the thickness of about 5nm on the substrate by magnetron sputtering, and further completing the whole magnetron sputtering by four steps of lofting, vacuumizing, electromagnetic sputtering and sampling in sequence. Parameters involved in magnetron sputtering include: the vacuum degree of the background of the sputtering chamber needs to be higher than 10-5Pa, the temperature of the electromagnetic sputtering is room temperature, and the sputtering pressure is 0.1-1.5 Pa.
S30 processes the heavy metal layer to form a cross structure. The prepared heavy metal layer 120 is subjected to electron beam exposure by using negative resist, ultrasonic cleaning is performed on the heavy metal layer, then glue coating and heating are respectively performed, electron beam exposure and development fixing are performed by using an electron beam direct writing system, a part without the protection of the photoresist is removed by using argon ion beam etching, and finally, the negative resist is removed by acetone soaking and ultrasonic cleaning, so that a 80 × 10 μm double cross structure (hall bar structure) is left as shown in fig. 2.
S40 electrodes were prepared at the outer ends of the cross structure (double cross structure). The electrode is made by adopting electron beam exposure and magnetron sputtering, for example, specifically, if Pt is selected as an electrode material, the semi-finished product after the step S30 is subjected to ultrasonic cleaning, then glue coating and heating are respectively carried out, an electron beam direct writing system is used for carrying out electron beam exposure and development and fixation, then acetone soaking and ultrasonic cleaning are carried out to remove the positive glue part of the exposed part, and a pit is left to grow the electrode; and (3) burying the electrode by using a magnetron sputtering method, and completing the whole magnetron sputtering by sequentially performing lofting, vacuumizing, electromagnetic sputtering and sampling to form a corresponding electrode.
Specifically, parameters involved in magnetron sputtering include: the vacuum degree of the background of the sputtering chamber needs to be higher than 10-5Pa, the temperature of the electromagnetic sputtering is room temperature, the sputtering pressure is 0.1-1.5Pa, and the film thickness of the prepared Pt electrode is about 5 nm. Finally, the semi-finished product buried by the electrode is soaked in acetone and cleaned by ultrasonic waves to remove the redundant photoresist and the insulating layer, and the cross-shaped junction of the heavy metal layer 120 is leftAnd a Pt electrode.
S50 preparing the ferromagnetic layer. Growing Co of about 1nm thickness on the semi-finished product after the step S40 by magnetron sputtering32Fe48B20And (3) similarly completing the whole magnetron sputtering by four steps of lofting, vacuumizing, electromagnetic sputtering and sampling. Parameters involved in magnetron sputtering include: the background vacuum degree of the sputtering chamber needs to be higher than 10-5Pa, the sputtering temperature is room temperature, and the sputtering pressure is 0.1-1.5 Pa.
S60 preparing a multiferroic layer. The multiferroic layer is formed by laser pulse deposition, and specifically, the multiferroic layer is prepared by five steps of lofting, vacuumizing, heating, emitting laser pulses and cooling and sampling, wherein the thickness of the multiferroic layer is about 2 nm. The parameters involved in the preparation of the multiferroic layer include: the background vacuum degree of the deposition chamber needs to be higher than 10-4Pa, the oxygen pressure is 1Pa to 10Pa during deposition, the deposition temperature is 700 ℃ to 750 ℃, the energy of laser pulse is 100mJ to 400mJ during deposition, and the laser frequency is 1 Hz to 5 Hz.
The logic device can provide a weak bias magnetic field by the exchange bias field formed by the multiferroic layer and the ferromagnetic layer, and does not need to provide an external magnetic field for magnetic storage.
S70 preparing an oxide layer; and growing metal Al with the thickness of about 1.5nm on the multiferroic layer by magnetron sputtering, and completing the whole magnetron sputtering step by four steps of lofting, vacuumizing, electromagnetic sputtering and sampling. The basic parameters in the magnetron sputtering process include: the background vacuum degree of the sputtering chamber needs to be higher than 10-5Pa, room temperature electromagnetic sputtering temperature, sputtering pressure of 0.1-1.5Pa, growing Al on the multiferroic layer, and exposing the grown Al to O under 4Pa and 30W2Plasma species to form oxide layers 150 of different oxidation degrees according to different oxidation times tox.
Further, due to the resistance R of the heavy metal layer 120xyThe component of the magnetic moment in the ferromagnetic layer 130 in the longitudinal z-direction may be used to initialize the magnetic moment of the ferromagnetic layer 130 in the logic device with an external magnetic field, with the initial magnetic moment directed up or down.
The logic device can regulate and control the magnetic moment direction of the ferromagnetic layer by using the input voltage V without an external magnetic field, namely, a signal of the logic device can be initialized by applying the input voltage V; the logic device utilizes the electromagnetic spin orbit coupling effect, and the spin orbit coupling critical current is regulated and controlled by the electric field, so that the energy consumption of the logic device can be effectively reduced.
Fig. 7a and 7b are schematic diagrams of a first embodiment and a second embodiment of the logic assembly of the present invention, respectively, as shown in fig. 7a, a p-type logic device having a peroxide oxide layer 151 is connected in series with an n-type logic device having an under-oxide layer 152, specifically, the heavy metal layer and the oxide layer of the two logic devices are connected in series, the p-type logic device is in front of the n-type logic device, the n-type logic device is in back of the p-type logic device, an electrode 162 opposite to the input electrode 161 in the heavy metal layer 120 of the p-type logic device is electrically connected to the input electrode 161 of the n-type logic device, the oxide layers of the p-type logic device and the n-type logic device are both connected to the input voltage V, and one of the logic devices can be selectively controlled by changing the direction of the input voltage V.
Specifically, when the initial magnetic moments of the ferromagnetic layers 130 of the two logic devices are in the same direction and both are upward, when the input current I (I ═ 12mA, for example) simultaneously satisfies the normal operating current of the p-type spin logic device and the normal operating current of the n-type spin logic device, the state of the p-type logic device or the state of the n-type logic device can be selectively controlled by the input current I by changing the direction of the input voltage V, so as to implement the complementary function of the logic device, and accordingly, the logic assembly has a logic complementary function.
As shown in fig. 7b, a p-type logic device with a peroxide oxide layer 151 is also connected in series with an n-type logic device with an under-oxidized oxide layer 152 in a similar manner as in fig. 7a, but in this embodiment the n-type logic device is in the front and the p-type logic device is in the back, and the initial magnetic moments of the ferromagnetic layers 130 of both logic devices are in the same direction and both downward, and similarly, this embodiment can also achieve the corresponding logic complementary function.
In the illustration, only one p-type logic device and one n-type logic device are connected in series to form a logic assembly, but of course, the logic assembly may also be formed by connecting a plurality of p-type logic devices and a plurality of n-type logic devices in series in a similar manner, the arrangement order of the two logic devices may also be adjusted according to the situation, and further, the initial direction of the magnetic moment of the ferromagnetic layer 130 may also be adjusted accordingly according to the requirement.
Fig. 8 is a truth table corresponding to the logic component according to an embodiment of the present invention, in which when the magnetic moment initial direction of the ferromagnetic layer 130 is upward (↓) and the magnetic moment initial direction is downward (↓) are recorded, the outputs of the n-type logic device and the p-type logic device are output under different input conditions.
Comparing the first and second embodiments of the logic element shown in FIG. 7a and FIG. 7b, in conjunction with the truth table of FIG. 8, in the first embodiment of the logic element shown in FIG. 7a, when the input current I isIN(e.g. I)IN12mA) can only be satisfied when the normal operating current of the p-type spin logic device and the normal operating current of the n-type spin logic device are satisfied simultaneouslyINTo achieve a single logic device output of 0 in the assembly when inverted, in particular when IINWhen the voltage V is reversed while the voltage is 12mA, the corresponding output R is obtainedp＝0，RnWhen 1 is equal toINWhen the voltage V is positive direction, the corresponding output R is 12mA and is reverse directionp＝1，RnNot equal to 0, the rest IINIn the case of 12mA, the corresponding output R is given regardless of the forward or reverse direction and regardless of the forward or reverse direction of the voltage VpAnd RnAre all 1. The logic assembly of this first embodiment may be configured to control the input current and input voltage such that a given type of logic device in the assembly outputs a 0.
In a second embodiment of the logic component as shown in fig. 7b, when the current I is inputIN(e.g. I)IN12mA) can only be satisfied when the normal operating current of the p-type spin logic device and the normal operating current of the n-type spin logic device are satisfied simultaneouslyINIn the forward direction, a single logic device in the assembly is implemented with an output of 1, specifically, when IINWhen the voltage V is reverse direction and the voltage V is 12mA, the corresponding output Rp＝1，RnWhen I is equal to 0IN12mA in forward direction, and when the voltage V is also in forward directionCorresponding output Rp＝0，R n1, the rest of IINIn the case of 12mA, the corresponding output R is given regardless of the forward or reverse direction and regardless of the forward or reverse direction of the voltage VpAnd RnAre all 0. The logic assembly of this second embodiment may be configured to control the input current and input voltage such that a given type of logic device in the assembly outputs a 1.
Further, the initialization and information erasure operations of the logic device, initialization and information erasure: when the input current I (for example, I ═ 15mA) is greater than the normal operating current of both the p-type spin logic device and the n-type spin logic device, the two devices are controlled simultaneously no matter whether the voltage is in the forward direction or the reverse direction, so that the logic devices are initialized and/or erased by the input current, and the corresponding logic components also allow all information in each logic device to be initialized and erased simultaneously. Of course, the initial magnetic moments of the ferromagnetic layers of the two logic devices in the logic element can be reversed, and the inputs and outputs can be obtained from the truth table.
The utility model provides a logic device has following advantage or beneficial effect: by adopting flexible materials such as mica single crystal sheets, polyether sulfone (PES), polyethylene terephthalate (PI) and the like to manufacture the substrate, the corresponding logic device has the advantages of being lighter, more resistant to extrusion, bendable and the like compared with the traditional device;
the logic device may have its oxide layer oxidation state adjusted as needed to form the desired n-type or p-type logic device to perform the n-type or p-type logic function. The manufacturing method corresponding to the logic device also has strong practicability.
Furthermore, the logic component formed by combining the two logic devices can directly execute n-type and p-type logic functions, integrates the n-type and p-type logic functions into a whole, has the functions of simultaneously initializing and erasing information of the two devices, is convenient and quick to operate, and further enhances the reliability of the logic component due to the logic complementarity.
Based on the utility model provides a logic assembly, it not only has complementary logical operation function, and information initialization or erasure function have wide application prospect in multi-functional or programmable spin logic device field in addition.
The utility model discloses an adopt many iron materials to realize the regulation and control of electric field to spin orbit coupling critical current for the logic device that corresponds can effectively regulate and control spin orbit coupling signal at the room temperature.
The effect of the logic device is changed by using different oxidation state interfaces (oxide layers), so that the regulation and control degrees of positive and negative input voltages (electric fields) to spin orbit coupling critical current are different, an n-type or p-type logic operation function can be achieved, a logic device which is light, portable and low in power consumption is obtained, and a storage device which can be read and written quickly and has high storage density can be manufactured on the basis of the logic device.
The above embodiments are merely examples of the present invention, and although the embodiments of the present invention and the accompanying drawings are disclosed for illustrative purposes, those skilled in the art will understand that: various substitutions, changes and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the disclosure of the embodiment and the drawings.
Claims (10)
1. A logic device, comprising:
a substrate for carrying the logic device;
the heavy metal layer is positioned on the substrate;
a ferromagnetic layer on the heavy metal layer;
a multiferroic layer on the ferromagnetic layer;
an oxide layer on the multiferroic layer;
the heavy metal layer comprises at least one cross structure, corresponding electrodes are arranged at the outer side ends of the cross structures, and the resistance of the heavy metal layer is changed by changing the direction of voltage applied between the oxide layer and the heavy metal layer.
2. The logic device of claim 1, wherein the oxide layer is in one of a peroxide state or an underoxide state.
3. The logic device as claimed in claim 2, wherein the outer end of the cross structure includes an input electrode, and the other end electrode opposite to the input electrode is grounded, and the other end electrodes of the cross structure in a direction perpendicular to the input electrode are output terminals from which abnormal hall voltages are detected as output signals.
4. The logic device of claim 1, wherein the initial magnetic moment direction of the ferromagnetic layer is up or down perpendicular to the ferromagnetic layer plane.
5. The logic device according to claim 1, wherein the substrate is a flexible substrate, and the heavy metal layer, the ferromagnetic layer, the multiferroic layer, and the oxide layer are each in a thin film shape.
6. The logic device of claim 1,
the thickness of the heavy metal layer is 3-10 nanometers;
the ferromagnetic layer has a thickness of 1-30 nanometers;
the thickness of the multiferroic layer is 2-200 nanometers;
the thickness of the oxide layer is 1-10 nanometers.
7. The logic device as claimed in claim 1, wherein the oxide layer is in a peroxide state, and wherein a forward voltage between the oxide layer and the heavy metal layer results in a spin-orbit coupling critical current of the oxide layer of I11When a negative voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the oxide layer is I21In which I11Is greater than I21；
Introducing input to the input electrodeThe input current I is when21＜I＜I11At positive voltage, the output signal does not change with the change of the direction of the input current I, and at negative voltage, the output signal reverses with the change of the direction of the input current I.
8. The logic device as claimed in claim 1, wherein the oxide layer is in an underoxidized state and a spin-orbit coupling critical current of the oxide layer is I at a forward voltage between the oxide layer and the heavy metal layer12When a negative voltage is applied between the oxide layer and the heavy metal layer, the spin-orbit coupling critical current of the oxide layer is I22In which I12Is less than I22；
Inputting an input current I to the input electrode when I is12＜I＜I22At positive voltage, the output signal is reversed with the change of the direction of the input current I, and at negative voltage, the output signal is unchanged with the change of the direction of the input current I.
9. A logic assembly, comprising: at least 2 logic devices according to claim 1; the logic device comprises an oxide layer in a peroxide state and an oxide layer in an underoxide state, the two logic devices are connected in series, the heavy metal layer and the oxide layer of the two logic devices are respectively connected in series, and at least one of the two logic devices is controlled by changing the voltage direction selectivity between the oxide layer and the heavy metal layer.
10. The logic assembly of claim 9, wherein the initial magnetic moments of the ferromagnetic layers of both of the logic devices are in the same or opposite directions.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110265479A (en) * | 2019-05-27 | 2019-09-20 | 叶建国 | Logical device, logic module and its manufacturing method |
| CN110265479B (en) * | 2019-05-27 | 2024-05-31 | 叶建国 | Logic device, logic assembly and manufacturing method thereof |
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| CN110265479A (en) * | 2019-05-27 | 2019-09-20 | 叶建国 | Logical device, logic module and its manufacturing method |
| CN110265479B (en) * | 2019-05-27 | 2024-05-31 | 叶建国 | Logic device, logic assembly and manufacturing method thereof |
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