CN110223657B - Time schedule controller and control method thereof - Google Patents
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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Abstract
The invention provides a time schedule controller and a control method thereof. The timing controller includes: the system comprises a receiving module, a detecting module electrically connected with the receiving module, an internal clock module electrically connected with the detecting module, a control module electrically connected with the detecting module and an internal self-checking module electrically connected with the detecting module; the receiving module is used for generating a signal to be detected; the internal clock module is used for generating a sampling clock signal; the control module is used for outputting preset threshold data to the detection module; the detection module is used for determining a threshold range according to preset threshold data, sampling a signal to be detected by using a sampling clock signal to obtain a sampling value, comparing the sampling value with the threshold range, and controlling the internal self-detection module to be closed if the sampling value is within the threshold range, or controlling the internal self-detection module to be started if the sampling value is not within the threshold range. According to the invention, the internal clock module is adopted to replace the existing external crystal oscillator, so that the production cost can be reduced, and the product competitiveness is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a time schedule controller and a control method thereof.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have advantages of high image quality, power saving, thin body, and wide application range, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices.
Most of the existing liquid crystal displays in the market are backlight type liquid crystal displays (lcds) including a liquid crystal panel and a backlight module (backlight module). The liquid crystal panel operates on the principle that liquid crystal molecules are filled between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter Substrate (Color Filter, CF), and driving voltages are applied to the two substrates to control the rotation direction of the liquid crystal molecules, so that light of the backlight module is refracted out to generate a picture. In the active liquid crystal display, each pixel is electrically connected with a Thin Film Transistor (TFT), a Gate (Gate) of the TFT is connected to a horizontal scanning line, a Source (Source) is connected to a data line in a vertical direction, and a Drain (Drain) is connected to a pixel electrode. Applying sufficient voltage to the horizontal scanning lines can turn on all TFTs electrically connected to the horizontal scanning lines, so that signal voltage on the data lines can be written into the pixels, and the transmittance of different liquid crystals can be controlled, thereby achieving the effect of controlling color and brightness.
The conventional liquid crystal display device needs to be driven by an external driving circuit, which generally includes: the LCD panel driving Circuit comprises a timing control chip (TCON), a Power management chip (Power management IC), a programmable gamma correction chip (P-gamma IC) and the like, wherein the TCON, the Power management IC and the P-gamma IC are arranged on a Printed Circuit Board (PCB), the timing control chip is mainly used for generating timing signals for driving the LCD panel according to Low-Voltage Differential Signaling (LVDS) signals or Mini-LVDS signals, the Power management chip is mainly used for generating various voltages for driving the LCD panel, and the programmable gamma correction chip is mainly used for generating gamma voltages.
The conventional time schedule controller needs to provide accurate and reliable internal clock signals for the conventional time schedule controller during working, and in order to generate the internal clock signals, the conventional time schedule controller generally needs to be matched with an external clock crystal oscillator for use.
Disclosure of Invention
The invention aims to provide a time schedule controller which can reduce the product cost and improve the product competitiveness on the premise of ensuring the working stability.
The invention also aims to provide a control method of the time schedule controller, which can reduce the product cost and improve the product competitiveness on the premise of ensuring the working stability.
To achieve the above object, the present invention provides a timing controller, comprising: the system comprises a receiving module, a detecting module electrically connected with the receiving module, an internal clock module electrically connected with the detecting module, a control module electrically connected with the detecting module and an internal self-checking module electrically connected with the detecting module;
the receiving module is used for generating a signal to be detected and outputting the signal to be detected to the detecting module;
the internal clock module is used for generating a sampling clock signal and outputting the sampling clock signal to the detection module;
the control module is used for outputting preset threshold data to the detection module;
the detection module is used for determining a threshold range according to preset threshold data and sampling a signal to be detected by using a sampling clock signal to obtain a sampling value, the sampling value is compared with the threshold range, if the sampling value is in the threshold range, the internal self-checking module is controlled to be closed, the time schedule controller normally works, otherwise, the internal self-checking module is controlled to be started, and the time schedule controller stops working and enters the internal self-checking.
The preset threshold data comprises an initial pulse upper limit value, an initial pulse lower limit value, an internal sampling compensation pulse upper limit value and an internal sampling compensation pulse lower limit value;
the upper limit of the threshold range is the sum of the upper limit value of the initial pulse and the upper limit value of the internal sampling compensation pulse, and the lower limit is the sum of the lower limit value of the initial pulse and the lower limit value of the internal sampling compensation pulse;
the sampling value is the number of high potential pulses of the sampling clock signal sampled in a high potential pulse interval of the signal to be detected.
The receiving module receives an input signal and generates a signal to be detected by decompressing the input signal, wherein the input signal is an LVDS signal or a Mini-LVDS signal.
The internal clock module comprises an oscillator and a phase-locked loop electrically connected with the oscillator and the detection module.
The signal to be detected comprises at least one of a working clock signal and a data enable signal of the time schedule controller.
The invention also provides a control method of the time schedule controller, which comprises the following steps:
providing a time schedule controller, wherein the time schedule controller comprises a receiving module, a detecting module electrically connected with the receiving module, an internal clock module electrically connected with the detecting module, a control module electrically connected with the detecting module and an internal self-checking module electrically connected with the detecting module;
the receiving module generates a signal to be detected and outputs the signal to be detected to the detecting module;
the internal clock module generates a sampling clock signal and outputs the sampling clock signal to the detection module;
the control module outputs preset threshold data to the detection module;
the detection module determines a threshold range according to preset threshold data and samples a signal to be detected by using a sampling clock signal to obtain a sampling value, the sampling value is compared with the threshold range, if the sampling value is in the threshold range, the internal self-checking module is controlled to be closed, the time schedule controller normally works, otherwise, the internal self-checking module is controlled to be started, and the time schedule controller stops working and enters the internal self-checking.
The preset threshold data comprises an initial pulse upper limit value, an initial pulse lower limit value, an internal sampling compensation pulse upper limit value and an internal sampling compensation pulse lower limit value;
the upper limit of the threshold range is the sum of the upper limit value of the initial pulse and the upper limit value of the internal sampling compensation pulse, and the lower limit is the sum of the lower limit value of the initial pulse and the lower limit value of the internal sampling compensation pulse;
the sampling value is the number of high potential pulses of the sampling clock signal sampled in a high potential pulse interval of the signal to be detected.
The receiving module receives an input signal and generates a signal to be detected by decompressing the input signal, wherein the input signal is an LVDS signal or a Mini-LVDS signal.
The internal clock module comprises an oscillator and a phase-locked loop electrically connected with the oscillator and the detection module.
The signal to be detected comprises at least one of a working clock signal and a data enable signal of the time schedule controller.
The invention has the beneficial effects that: the present invention provides a timing controller, comprising: the system comprises a receiving module, a detecting module electrically connected with the receiving module, an internal clock module electrically connected with the detecting module, a control module electrically connected with the detecting module and an internal self-checking module electrically connected with the detecting module; the receiving module is used for generating a signal to be detected and outputting the signal to be detected to the detecting module; the internal clock module is used for generating a sampling clock signal and outputting the sampling clock signal to the detection module; the control module is used for outputting preset threshold data to the detection module; the detection module is used for determining a threshold range according to preset threshold data and sampling a signal to be detected by utilizing a sampling clock signal to obtain a sampling value, the sampling value is compared with the threshold range, if the sampling value is in the threshold range, the internal self-checking module is controlled to be closed, the time schedule controller normally works, otherwise, the internal self-checking module is controlled to be started, the time schedule controller stops working to enter the internal self-checking, the internal clock module is adopted to replace an existing external crystal oscillator, the production cost can be reduced, and the product competitiveness is improved. The invention also provides a control method of the time schedule controller, which can reduce the production cost and improve the product competitiveness.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic diagram of a timing controller according to the present invention;
FIG. 2 is a sampling timing diagram of a timing controller according to a first embodiment of the present invention;
FIG. 3 is a sampling timing diagram of a second embodiment of the timing controller of the present invention;
FIG. 4 is a sampling timing diagram of a third embodiment of the timing controller of the present invention;
fig. 5 is a flowchart of a control method of a timing controller according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides a timing controller, including: the system comprises a receiving module 10, a detecting module 20 electrically connected with the receiving module 10, an internal clock module 30 electrically connected with the detecting module 20, a control module 40 electrically connected with the detecting module 20 and an internal self-test module 50 electrically connected with the detecting module 20;
the receiving module 10 is configured to generate a signal to be detected S2, and output the signal to be detected S2 to the detecting module 20;
the internal clock module 30 is configured to generate a sampling clock signal CKE and output the sampling clock signal to the detection module 20;
the control module 40 is configured to output preset threshold data Cod to the detection module 20;
the detection module 20 is configured to determine a threshold range according to preset threshold data Cod and sample a signal to be detected S2 with a sampling clock signal CKE to obtain a sampling value, compare the sampling value with the threshold range, and control the internal self-checking module 50 to be turned off and the timing controller to normally operate if the sampling value is within the threshold range, otherwise control the internal self-checking module 50 to be turned on and the timing controller to stop operating and enter internal self-checking.
Specifically, the preset threshold data Cod includes an initial pulse upper limit value, an initial pulse lower limit value, an internal sampling compensation pulse upper limit value, and an internal sampling compensation pulse lower limit value;
the upper limit of the threshold range is the sum of the upper limit value of the initial pulse and the upper limit value of the internal sampling compensation pulse, and the lower limit is the sum of the lower limit value of the initial pulse and the lower limit value of the internal sampling compensation pulse;
the sampling value is the number of high potential pulses of the sampling clock signal CKE sampled within a high potential pulse interval of the signal to be detected S2.
It should be noted that the initial pulse upper limit value and the initial pulse lower limit value are set values in the control module when the external crystal oscillator is used for sampling, that is, when the external crystal oscillator is used for generating a sampling clock signal, the corresponding threshold range upper limit and lower limit are the initial pulse upper limit value and the initial pulse lower limit value, respectively.
Further, different from an external crystal oscillator, the internal clock module (i.e. the internal crystal oscillator) is adopted to generate a sampling clock signal, because the stability of the internal clock module is reduced compared with that of the external crystal oscillator, when the internal clock module is interfered by the environment, the internal clock module is easy to drift, so that the frequency of the sampling clock signal changes, and further the final sampling value is influenced, for example, under the condition that the frequency of a signal to be detected is not changed, the frequency of the sampling clock signal drifts upwards (slightly) to cause the final sampling value to be larger, and the frequency of the sampling clock signal drifts downwards (slightly) to cause the final sampling value to be smaller, in order to compensate the influence of the drift of the sampling clock signal on the sampling value, the internal sampling compensation pulse upper limit value and the internal sampling compensation pulse lower limit value are additionally added in threshold data, so as to realize that under the condition that the internal clock module is used to generate, the accuracy of detection is guaranteed, and misjudgment is reduced.
Specifically, the detection module 20 outputs a self-test control signal Ctr to the internal self-test module 50 to control the internal self-test module 50 to be turned on or off.
Specifically, referring to fig. 2, in the first embodiment of the present invention, the upper limit of the threshold range, that is, the sum of the upper limit of the initial pulse and the upper limit of the internal sampling compensation pulse, is 4, the lower limit, that is, the sum of the lower limit of the initial pulse and the lower limit of the internal sampling compensation pulse, is 2, the number of high-potential pulses of the sampling clock signal CKE sampled in a high-potential pulse interval of the signal to be detected S2 is 5, the sampling value exceeds the threshold range, the frequency of the signal to be detected S2 is too low to meet the normal operation requirement of the timing controller, the self-check control signal Ctr is switched from the low potential to the high potential, the internal self-check module 50 is started under the control of the high-potential self-check control signal Ctr, and the timing controller enters the internal self-.
Specifically, referring to fig. 3, in the second embodiment of the present invention, the upper limit of the threshold range, that is, the sum of the upper limit of the initial pulse and the upper limit of the internal sampling compensation pulse, is 4, the lower limit, that is, the sum of the lower limit of the initial pulse and the lower limit of the internal sampling compensation pulse, is 2, the number of high-potential pulses of the sampling clock signal CKE sampled in a high-potential pulse interval of the signal to be detected S2 is 1, the sampling value exceeds the threshold range, the frequency of the signal to be detected S2 is too high and does not meet the normal operation requirement of the timing controller, the self-checking control signal Ctr is switched from the low potential to the high potential, the internal self-checking module 50 is started under the control of the high-potential self-checking control signal Ctr, and the timing controller enters the internal self.
Specifically, referring to fig. 4, in the third embodiment of the present invention, the upper limit of the threshold range, i.e., the sum of the upper limit of the initial pulse and the upper limit of the internal sampling compensation pulse, is 4, the lower limit, i.e., the sum of the lower limit of the initial pulse and the lower limit of the internal sampling compensation pulse, is 2, the number of high-potential pulses of the sampling clock signal CKE sampled in a high-potential pulse interval of the signal to be detected S2 is 3, the frequency of the signal to be detected S2 is normal when the sampling value is in the threshold range, and meets the normal operation requirement of the timing controller, the self-checking control signal Ctr keeps a low potential, the internal self-checking module 50 is turned off under the control of the self-checking control signal Ctr with the low potential, and the timing controller operates normally.
Specifically, the receiving module 10 receives an input signal S1 and generates a signal to be detected S2 by decompressing the input signal S1, where the input signal S1 is a Low-Voltage Differential Signaling (LVDS) or a Mini-LVDS signal, the signal to be detected S2 includes at least one of an operating clock signal RX _ CLK and a data enable signal DE of the timing controller, and both the operating clock signal RX _ CLK and the data enable signal DE are decompressed by the LVDS or Mini-LVDS signal.
Specifically, the internal clock module 30 includes an Oscillator (OSC) 31 and a Phase Locked Loop (PLL) 32 electrically connecting the Oscillator 31 and the detection module 20, so as to generate a required sampling clock signal through cooperation of the Oscillator 31 and the PLL 32.
It should be noted that, the timing controller is configured to drive the display panel to display a picture, when the timing controller normally works, the timing controller generates a corresponding video signal according to the input signal S1 and provides the video signal to the display panel to enable the display panel to display a corresponding video picture, and when the timing controller stops working normally and enters the internal self-checking mode, the timing controller stops providing the video signal obtained according to the input signal S1 to the display panel, but directly provides a predetermined self-checking signal to the display panel to enable the display panel to display a self-checking picture, and the self-checking picture displayed by the display panel under the control of the self-checking signal is generally a pure color picture, for example, in some embodiments of the present invention, after the timing controller enters the internal self-checking mode, the self-checking signal output by the timing controller controls the display panel to cyclically display pure black, pure white, pure red, pure blue, and pure green pictures, each solid picture is displayed for 2 seconds.
Referring to fig. 5, the present invention further provides a method for controlling a timing controller, including the following steps:
a timing controller is provided, which includes a receiving module 10, a detecting module 20 electrically connected to the receiving module 10, an internal clock module 30 electrically connected to the detecting module 20, a control module 40 electrically connected to the detecting module 20, and an internal self-test module 50 electrically connected to the detecting module 20.
Specifically, the internal clock module 30 includes an oscillator 31 and a phase-locked loop 32 electrically connecting the oscillator 31 and the detection module 20.
The receiving module 10 generates a signal to be detected S2, and outputs the signal to be detected S2 to the detecting module 20.
Specifically, the receiving module 10 receives an input signal S1 and generates a signal to be detected S2 by decompressing the input signal S1, where the input signal S1 is a Low-Voltage Differential Signaling (LVDS) or a Mini-LVDS signal, the signal to be detected S2 includes at least one of an operating clock signal RX _ CLK and a data enable signal DE of the timing controller, and both the operating clock signal RX _ CLK and the data enable signal DE are decompressed by the LVDS or Mini-LVDS signal.
The internal clock module 30 generates a sampling clock signal CKE and outputs the sampling clock signal CKE to the detection module 20;
the control module 40 outputs preset threshold data Cod to the detection module 20;
the detection module 20 determines a threshold range according to preset threshold data Cod and samples the signal to be detected S2 with the sampling clock signal CKE to obtain a sampling value, and compares the sampling value with the threshold range, if the sampling value is within the threshold range, the internal self-checking module 50 is controlled to be closed, the timing controller normally works, otherwise, the internal self-checking module 50 is controlled to be started, and the timing controller stops working to enter internal self-checking.
Specifically, the preset threshold data Cod includes an initial pulse upper limit value, an initial pulse lower limit value, an internal sampling compensation pulse upper limit value, and an internal sampling compensation pulse lower limit value;
the upper limit of the threshold range is the sum of the upper limit value of the initial pulse and the upper limit value of the internal sampling compensation pulse, and the lower limit is the sum of the lower limit value of the initial pulse and the lower limit value of the internal sampling compensation pulse;
the sampling value is the number of high potential pulses of the sampling clock signal CKE sampled within a high potential pulse interval of the signal to be detected S2.
It should be noted that the initial pulse upper limit value and the initial pulse lower limit value are set values in the control module when the external crystal oscillator is used for sampling, that is, when the external crystal oscillator is used for generating a sampling clock signal, the corresponding threshold range upper limit and lower limit are the initial pulse upper limit value and the initial pulse lower limit value, respectively.
Further, different from an external crystal oscillator, the internal clock module (i.e. the internal crystal oscillator) is adopted to generate a sampling clock signal, because the stability of the internal clock module is reduced compared with that of the external crystal oscillator, when the internal clock module is interfered by the environment, the internal clock module is easy to drift, so that the frequency of the sampling clock signal changes, and further the final sampling value is influenced, for example, under the condition that the frequency of a signal to be detected is not changed, the frequency of the sampling clock signal drifts upwards (slightly) to cause the final sampling value to be larger, and the frequency of the sampling clock signal drifts downwards (slightly) to cause the final sampling value to be smaller, in order to compensate the influence of the drift of the sampling clock signal on the sampling value, the internal sampling compensation pulse upper limit value and the internal sampling compensation pulse lower limit value are additionally added in threshold data, so as to realize that under the condition that the internal clock module is used to generate, the accuracy of detection is guaranteed, and misjudgment is reduced.
Specifically, the detection module 20 outputs a self-test control signal Ctr to the internal self-test module 50 to control the internal self-test module 50 to be turned on or off.
Specifically, referring to fig. 2, in the first embodiment of the present invention, the upper limit of the threshold range, that is, the sum of the upper limit of the initial pulse and the upper limit of the internal sampling compensation pulse, is 4, the lower limit, that is, the sum of the lower limit of the initial pulse and the lower limit of the internal sampling compensation pulse, is 2, the number of high-potential pulses of the sampling clock signal CKE sampled in a high-potential pulse interval of the signal to be detected S2 is 5, the sampling value exceeds the threshold range, the frequency of the signal to be detected is too low, and does not meet the normal operation requirement of the timing controller, the self-checking control signal Ctr is switched from the low potential to the high potential, the internal self-checking module 50 is started under the control of the high-potential self-checking control signal Ctr, and the timing controller enters internal.
Specifically, referring to fig. 3, in the second embodiment of the present invention, the upper limit of the threshold range, that is, the sum of the upper limit of the initial pulse and the upper limit of the internal sampling compensation pulse, is 4, the lower limit, that is, the sum of the lower limit of the initial pulse and the lower limit of the internal sampling compensation pulse, is 2, the number of high-potential pulses of the sampling clock signal CKE sampled in a high-potential pulse interval of the signal to be detected S2 is 1, the sampling value exceeds the threshold range, the frequency of the signal to be detected is too high, and does not meet the normal operation requirement of the timing controller, the self-checking control signal Ctr is switched from the low potential to the high potential, the internal self-checking module 50 is started under the control of the high-potential self-checking control signal Ctr, and the timing controller enters internal self.
Specifically, referring to fig. 4, in the third embodiment of the present invention, the upper limit of the threshold range, i.e., the sum of the upper limit of the initial pulse and the upper limit of the internal sampling compensation pulse, is 4, the lower limit, i.e., the sum of the lower limit of the initial pulse and the lower limit of the internal sampling compensation pulse, is 2, the number of high-potential pulses of the sampling clock signal CKE sampled in a high-potential pulse interval of the signal to be detected S2 is 3, the frequency of the signal to be detected is normal in the threshold range, and meets the normal operation requirement of the timing controller, the self-checking control signal Ctr keeps a low potential, the internal self-checking module 50 is turned off under the control of the self-checking control signal Ctr with the low potential, and the timing controller operates normally.
It should be noted that, the timing controller is configured to drive the display panel to display a picture, when the timing controller normally works, the timing controller generates a corresponding video signal according to the input signal S1 and provides the video signal to the display panel to enable the display panel to display a corresponding video picture, and when the timing controller stops working normally and enters the internal self-inspection, the timing controller stops providing the video signal obtained according to the input signal S1 to the display panel, but directly provides a predetermined self-inspection signal to the display panel to enable the display panel to display a self-inspection picture, and the self-inspection picture displayed by the display panel is generally a pure color picture under the control of the self-inspection signal, for example, in some embodiments of the present invention, after the timing controller enters the internal self-inspection, the self-inspection signal output by the timing controller controls the display panel to cyclically display pure black, pure white, pure red, pure blue and pure green pictures, each solid picture is displayed for 2 seconds.
In summary, the present invention provides a timing controller, including: the system comprises a receiving module, a detecting module electrically connected with the receiving module, an internal clock module electrically connected with the detecting module, a control module electrically connected with the detecting module and an internal self-checking module electrically connected with the detecting module; the receiving module is used for generating a signal to be detected and outputting the signal to be detected to the detecting module; the internal clock module is used for generating a sampling clock signal and outputting the sampling clock signal to the detection module; the control module is used for outputting preset threshold data to the detection module; the detection module is used for determining a threshold range according to preset threshold data and sampling a signal to be detected by utilizing a sampling clock signal to obtain a sampling value, the sampling value is compared with the threshold range, if the sampling value is in the threshold range, the internal self-checking module is controlled to be closed, the time schedule controller normally works, otherwise, the internal self-checking module is controlled to be started, the time schedule controller stops working to enter the internal self-checking, the internal clock module is adopted to replace an existing external crystal oscillator, the production cost can be reduced, and the product competitiveness is improved. The invention also provides a control method of the time schedule controller, which can reduce the production cost and improve the product competitiveness.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (8)
1. A timing controller, comprising: the system comprises a receiving module (10), a detecting module (20) electrically connected with the receiving module (10), an internal clock module (30) electrically connected with the detecting module (20), a control module (40) electrically connected with the detecting module (20) and an internal self-checking module (50) electrically connected with the detecting module (20);
the receiving module (10) is used for generating a signal to be detected (S2) and outputting the signal to be detected (S2) to the detecting module (20);
the internal clock module (30) is used for generating a sampling clock signal (CKE) and outputting the sampling clock signal (CKE) to the detection module (20);
the control module (40) is used for outputting preset threshold data (Cod) to the detection module (20);
the detection module (20) is used for determining a threshold range according to preset threshold data (Cod), sampling a signal to be detected (S2) by using a sampling clock signal (CKE) to obtain a sampling value, comparing the sampling value with the threshold range, controlling the internal self-detection module (50) to be closed and the time schedule controller to normally work if the sampling value is in the threshold range, and otherwise controlling the internal self-detection module (50) to be started and stopping working to enter internal self-detection;
the preset threshold data (Cod) comprises an initial pulse upper limit value, an initial pulse lower limit value, an internal sampling compensation pulse upper limit value and an internal sampling compensation pulse lower limit value;
the upper limit of the threshold range is the sum of the upper limit value of the initial pulse and the upper limit value of the internal sampling compensation pulse, and the lower limit is the sum of the lower limit value of the initial pulse and the lower limit value of the internal sampling compensation pulse;
the sampling value is the number of high potential pulses of the sampling clock signal (CKE) sampled in a high potential pulse interval of the signal to be detected (S2).
2. The timing controller of claim 1, wherein the receiving module (10) receives an input signal (S1), and generates the signal to be detected (S2) by decompressing the input signal (S1), the input signal (S1) being an LVDS signal or a Mini-LVDS signal.
3. The timing controller of claim 1, wherein the internal clock module (30) comprises an oscillator (31) and a phase-locked loop (32) electrically connecting the oscillator (31) and the detection module (20).
4. The timing controller of claim 1, wherein the signal to be detected (S2) includes at least one of an operation clock signal and a data enable signal of the timing controller.
5. A control method of a time schedule controller is characterized by comprising the following steps:
providing a time schedule controller, wherein the time schedule controller comprises a receiving module (10), a detecting module (20) electrically connected with the receiving module (10), an internal clock module (30) electrically connected with the detecting module (20), a control module (40) electrically connected with the detecting module (20) and an internal self-checking module (50) electrically connected with the detecting module (20);
the receiving module (10) generates a signal to be detected (S2), and outputs the signal to be detected (S2) to the detecting module (20);
the internal clock module (30) generates a sampling clock signal (CKE) and outputs the sampling clock signal (CKE) to the detection module (20);
the control module (40) outputs preset threshold data (Cod) to the detection module (20);
the detection module (20) determines a threshold range according to preset threshold data (Cod) and samples a signal to be detected (S2) by using a sampling clock signal (CKE) to obtain a sampling value, the sampling value is compared with the threshold range, if the sampling value is within the threshold range, the internal self-detection module (50) is controlled to be closed, the time schedule controller normally works, otherwise, the internal self-detection module (50) is controlled to be started, and the time schedule controller stops working and enters internal self-detection;
the preset threshold data (Cod) comprises an initial pulse upper limit value, an initial pulse lower limit value, an internal sampling compensation pulse upper limit value and an internal sampling compensation pulse lower limit value;
the upper limit of the threshold range is the sum of the upper limit value of the initial pulse and the upper limit value of the internal sampling compensation pulse, and the lower limit is the sum of the lower limit value of the initial pulse and the lower limit value of the internal sampling compensation pulse;
the sampling value is the number of high potential pulses of the sampling clock signal (CKE) sampled in a high potential pulse interval of the signal to be detected (S2).
6. The control method of the timing controller of claim 5, wherein the receiving module (10) receives an input signal (S1) and generates the signal to be detected (S2) by decompressing the input signal (S1), the input signal (S1) being an LVDS signal or a Mini-LVDS signal.
7. The method of claim 5, wherein the internal clock module (30) comprises an oscillator (31) and a phase-locked loop (32) electrically connecting the oscillator (31) and the detection module (20).
8. The method of claim 5, wherein the signal to be detected (S2) includes at least one of an operation clock signal and a data enable signal of the timing controller.
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| CN111477187B (en) * | 2020-05-08 | 2022-01-04 | Tcl华星光电技术有限公司 | Time schedule controller, signal calibration method thereof and display device |
| CN115376437B (en) * | 2022-08-27 | 2023-07-25 | 亿慧云智能科技（深圳）股份有限公司 | Display method and system of display panel |
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