CN110176439A - A kind of module SiP structure and its manufacturing method - Google Patents

A kind of module SiP structure and its manufacturing method Download PDF

Info

Publication number
CN110176439A
CN110176439A CN201910457970.7A CN201910457970A CN110176439A CN 110176439 A CN110176439 A CN 110176439A CN 201910457970 A CN201910457970 A CN 201910457970A CN 110176439 A CN110176439 A CN 110176439A
Authority
CN
China
Prior art keywords
ltcc
substrate
shell
htcc
stiffening plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910457970.7A
Other languages
Chinese (zh)
Other versions
CN110176439B (en
Inventor
李林森
聂丽丽
张珂
李鸿高
张崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 43 Research Institute
Original Assignee
CETC 43 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 43 Research Institute filed Critical CETC 43 Research Institute
Priority to CN201910457970.7A priority Critical patent/CN110176439B/en
Publication of CN110176439A publication Critical patent/CN110176439A/en
Application granted granted Critical
Publication of CN110176439B publication Critical patent/CN110176439B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention relates to a kind of module SiP structure and its manufacturing methods, shell including sealing and the circuit unit in shell, the circuit unit includes the horizontal multilager base plate being set in shell, it is spaced from each other between adjacent substrate, the substrate is equipped with circuit components, it is connected and is connected by connecting line between each base on-board circuitry component, be additionally provided with the connecting pin being connected to circuit unit on the shell.Module SiP structure and its manufacturing method of the present invention realize highly integrated integration by the circuit layout of HTCC, LTCC multilayer wiring and precision, and volume reduces more compared with existing capability module;By design optimization, multilayer wiring and assembled with high precision, while reducing module volume, weight can reduce 30% or more.

Description

A kind of module SiP structure and its manufacturing method
Technical field
The present invention relates to a kind of electrical component assemblies, and in particular to a kind of module SiP structure and its manufacturing method.
Background technique
With large scale integrated circuit, semiconductor chip manufacture, it is integrated, encapsulation technology be constantly progressive, electronic system or Complete machine gradually shows multi-functional, high-performance, miniaturization, light-duty/portable, high speed, the development trend of low consumption and high reliability. This, which does not require nothing more than semiconductor chip, can integrate more different types of components, also to protection chip, increased thermal conductivity energy, play More stringent requirements are proposed for the encapsulation of the effects of bridge of chip chamber and peripheral circuit.Encapsulation technology by original monolithic IC, Discrete component encapsulation is integrated to develop to multi-chip, the system integration, high density, high reliability and high-performance package.
SiP is the abbreviation of " System in Package ", means that system encapsulates.SiP encapsulation can be by other such as passive group Component integration needed for the systems such as part and antenna makes it have more complete system function in single structure dress.With printing On circuit board carry out the system integration compare, SiP can to the maximum extent optimization system performance, avoid repeat encapsulate, shorten exploitation week Phase reduces cost, improves integrated level.Compare SOC(System on Chip system level chip), SiP has flexibility ratio height, collection At the features such as degree is high, the design cycle is short, development cost is low.
Authorization Notice No. provides for the Chinese invention patent of CN103765579B for manufacture system grade packaging Improved method, and in particular to the method and system in package device of manufacture system grade packaging.It in the method, will at least One first kind tube core, at least one second class tube core and system in package device with predetermined size with predetermined size At least one other component of part covers in system in package device.Select the first kind tube core and the second class tube core At least one of be used for resizing.To at least side added material of selected tube core, so that added material The tube core structure of resizing is formed with selected tube core.Articulamentum is formed on the tube core structure of the resizing.It is right The tube core structure of the resizing carries out scale cun, to allow non-selected tube core and at least one other portion Part manufacture is contacted at via the articulamentum with the tube core structure of the resizing.
Authorization Notice No. provides a kind of system-in-package module component, institute for the Chinese invention patent of CN105489597B State chip, inductance and electric elements that system-in-package module component includes substrate, is electrically connected with the substrate, the substrate packet Include first surface, the second surface and container opposite with the first surface, the container through the second surface with And the first surface;The inductance includes magnetic core and inductance coil, and the magnetic core includes matrix and is convexly equipped in described matrix The boss of one outer surface, the outer surface that described matrix is convexly equipped with the boss are bonded with the second surface, the boss receiving In in the container, the inductance coil is embedded in the boss, and the chip includes a manufacture face, the chip installing It is opposite with the first surface interval on the first surface and manufacture face, boss orthographic projection in the container in On the manufacture face of the chip, the electric elements are located at the chip periphery.A kind of system-level envelope that the invention provides Die-filling piece and electronic equipment mainly can reduce system-in-package module component integral thickness space, and then realize electronic product Slimming.Patent disclosed above, structure is all more complex, and manufacture is inconvenient, and not only volume is larger, and weight also compared with Weight.
Summary of the invention
The purpose of the present invention is to provide a kind of module SiP structure and its manufacturing methods, pass through multilayer wiring and high-precision Assembling, mitigates weight while reducing module volume.
To achieve the above object, the invention adopts the following technical scheme:
A kind of module SiP structure, the shell including sealing and the circuit unit in shell, the circuit unit include level Multilager base plate in shell is spaced from each other between adjacent substrate, and the substrate is equipped with circuit components, on each substrate It is connected and is connected by connecting line between circuit components, be additionally provided with the connecting pin being connected to circuit unit on the shell.
In above scheme, the circuit unit further includes stiffening plate, and the platform for fixing stiffening plate is equipped in the shell Rank, the stiffening plate are manufactured in shell by step level, and the upside of the stiffening plate is equipped with LTCC upper substrate, and downside is Equipped with LTCC lower substrate, the bottom of the shell is equipped with HTCC substrate, the LTCC upper substrate, LTCC lower substrate and HTCC substrate Between be connected to connecting pin by metal wire.
In above scheme, the stiffening plate is equipped with for the manufacturing hole across metal wire.
AlN-HTCC multilayer wiring is used on the HTCC substrate, the HTCC substrate is equipped with (PCC) power and for connecting Connect the connecting line of (PCC) power.
Further, the connecting pin uses glass insulator, and the glass insulator is introduced from shell side, passes through glass Glass sintering and canned integralization structure realize inside and outside interconnection by connecting line;Under HTCC substrate and LTCC upper substrate, LTCC It is connected between substrate by soft arranging wire.
Further, the stiffening plate is fixed in shell by detachable member, and LTCC upper substrate surface is pasted with naked Chip, flip-chip, the bare chip and flip-chip are realized by metal wire and are electrically connected;On LTCC lower substrate manufacture whether there is or not Source device;The LTCC upper substrate and LTCC lower substrate are all made of LTCC multilayer wiring, and pass through insulator or pottery between the two Porcelain block wire bonding.
A kind of manufacturing method of module SiP structure, comprising the following steps:
(1) integrated case package: the welding of shell outer lead, peripheral frame welding;
(2) LTCC upper substrate and its device assembling: being processed by shot blasting LTCC upper substrate surface, and after implementing thin-film technique, Filled under DSP back-off weldering and epoxy resin;Chip is buckled to postwelding, and surface protection is got up;By LTCC upper substrate surface device Part welding and the welding of substrate and stiffening plate are completed at the same time;Then remaining chip, component welded, be adhered to LTCC Substrate completes bonding;
(3) LTCC lower substrate device assembles: by the way that the passive device of signal circuit section is welded to LTCC lower substrate surface;
(4) HTCC substrate and its surface device assembling: entering shell for the device of driving circuit section and HTCC substrate synchronous welding, Then the bonding and wire bonding of surface device are carried out, and carries out the test of the partial circuit function;
(5) LTCC lower substrate is fixedly connected with stiffening plate, and LTCC upper and lower base plate is connect with HTCC shell;
(6) stiffening plate is fixed in shell, then tests, seals.
In above scheme, in the LTCC lower substrate device assembling, solder melt point is 179 degree, technological temperature 230- 250 degree.
In above scheme, the LTCC lower substrate is connected to stiffening plate, the LTCC upper and lower base plate, HTCC using Wear Characteristics of Epoxy Adhesive Substrate is connected with each other by gold wire bonding or soft arranging wire and shell, and the stiffening plate is fixed in shell by screw.
As shown from the above technical solution, module SiP structure and its manufacturing method of the present invention, pass through HTCC, LTCC Multilayer wiring and accurate circuit layout, realize highly integrated integration, volume can reduce 60% compared with existing capability module;Pass through Design optimization, multilayer wiring and assembled with high precision, while reducing module volume, weight can reduce 30% or more;Present invention tool There is high reliable: highly integrated integral structure, closed type≤1 × 10-3pacm3/s, securely and reliably;System-level precision Encapsulation, circuit performance are stablized: over-voltage, short circuit, overheat protector, resistance to temperature cycles, mechanical resistant impact.
Detailed description of the invention
Fig. 1 is structural schematic diagram of the invention;
Fig. 2 is top view of the invention.
Specific embodiment
The present invention will be further described with reference to the accompanying drawing:
As shown in Figure 1, the module SiP structure of the present embodiment, the circuit unit including shell 1 and in shell 1, the present embodiment Shell 1 include bottom case 11 and upper cover 12, the bottom case 11 and upper cover 12 are fixed by flange 14, realization integrated sealing;Circuit Component includes stiffening plate 2, and the step 13 for fixing stiffening plate 2 is equipped in shell 1, and stiffening plate 2 passes through the horizontal manufacture of step 13 In in shell 1, the upside of stiffening plate 2 is equipped with LTCC upper substrate 3, and the downside of stiffening plate 2 is equipped with LTCC lower substrate 4, shell 1 Bottom is equipped with HTCC substrate 5, is additionally provided with the connection being connected to circuit unit on shell 1, and 6, base under LTCC upper substrate 3, the LTCC It is electrically connected between plate 4 and HTCC substrate 5 by metal wire 8 and connecting pin 6.It is equipped in stiffening plate 2 for across metal wire 8 Manufacturing hole 9.
The present embodiment uses AlN-HTCC circuit board, and top is using ltcc substrate wiring manufacture signal control circuit portion Point, in order to promote the reliability of LTCC, use stiffening plate 2 as the support of ltcc substrate, control circuit interconnected, which uses, draws The interconnection of line interconnection, control circuit and power circuit is connected using soft arranging wire 14.The present embodiment uses the ltcc substrate number of plies for 10 Layer, barrier enclosure ring frame thickness 2mm, pin interconnection use 25 μm of φ of spun gold.
On the HTCC substrate 5 of the present embodiment use AlN-HTCC multilayer wiring, HTCC substrate 5 be equipped with (PCC) power 7 and For connecting the connecting line 8 of (PCC) power 7.
Connecting pin 6 uses glass insulator, and glass insulator is introduced from 1 side of shell, passes through glass sintering and 1 shape of shell Integralization structure realizes inside and outside interconnection by connecting line.
Stiffening plate 2 is fixed in shell by detachable member, the detachable member such as screw or stud etc., on LTCC 3 surface mount of substrate has bare chip, flip-chip, and bare chip and flip-chip are realized by metal wire to be electrically connected;Under LTCC Manufacture has passive device on substrate 5;LTCC upper substrate 3 and LTCC lower substrate 5 are all made of LTCC multilayer wiring, and lead between the two Cross insulator or ceramic block wire bonding.
As shown in Fig. 2, being connected between HTCC substrate 5 and LTCC upper substrate 3, LTCC lower substrate 4 by soft arranging wire 10.
The specific manufacturing step of the module SiP structure of the present embodiment is as follows:
Step 1: integrated case package: the welding of shell outer lead, peripheral frame welding;
Step 2:LTCC upper substrate and its device assembling:
LTCC upper substrate surface is processed by shot blasting, and after implementing thin-film technique, filled out under DSP back-off weldering and epoxy resin It fills;Chip is buckled to postwelding, and surface protection is got up;
The welding of the welding of upper substrate surface device, substrate and stiffening plate is completed at the same time;Then remaining chip, component are welded It connects, be adhered to ltcc substrate, complete bonding;
The assembling of 4 device of step 3:LTCC lower substrate: the passive device of signal circuit section is fabricated under LTCC by reflow welding 4 surface of substrate: 179 degree of solder melt point, 240 degree of technological temperature;
Step 4:HTCC substrate 5 and its surface device assembling: the device of driving circuit section and 5 synchronous welding of HTCC substrate are entered In shell 1, the bonding and wire bonding of surface device are then carried out, and carries out the test of the partial circuit function;
Step 5: LTCC lower substrate 4 is connected in stiffening plate 2 by Wear Characteristics of Epoxy Adhesive;
Step 6:LTCC upper and lower base plate 3 and 4 is connect by gold wire bonding or soft arranging wire with HTCC substrate 5, then leads to stiffening plate 2 Screw is crossed to be fixed in shell 1;
Step 7: completing test and sealing.
Embodiment described above only describe the preferred embodiments of the invention, not to model of the invention It encloses and is defined, without departing from the spirit of the design of the present invention, those of ordinary skill in the art are to technical side of the invention The various changes and improvements that case is made should all be fallen into the protection scope that claims of the present invention determines.

Claims (10)

1. a kind of module SiP structure, it is characterised in that: the shell including sealing and the circuit unit in shell, the electricity Road component includes the horizontal multilager base plate being set in shell, is spaced from each other between adjacent substrate, the substrate is equipped with circuit elements Device is connected between each base on-board circuitry component by connecting line and is connected, and is additionally provided on the shell and circuit unit connects Logical connecting pin.
2. module SiP structure according to claim 1, it is characterised in that: the circuit unit further includes stiffening plate, described The step for fixing stiffening plate is equipped in shell, the stiffening plate is manufactured in shell by step level, the stiffening plate Upside be equipped with LTCC upper substrate, downside is equipped with LTCC lower substrate, and the bottom of the shell is equipped with HTCC substrate, described It is connected to by metal wire with connecting pin between LTCC upper substrate, LTCC lower substrate and HTCC substrate.
3. module SiP structure according to claim 2, it is characterised in that: the stiffening plate is equipped with for across metal The manufacturing hole of line.
4. module SiP structure according to claim 1, it is characterised in that: more using AlN-HTCC on the HTCC substrate Layer wiring, the HTCC substrate are equipped with (PCC) power and the connecting line for connecting (PCC) power.
5. module SiP structure according to claim 1, it is characterised in that: the connecting pin uses glass insulator, described Glass insulator is introduced from shell side, by glass sintering and canned integralization structure, realized by connecting line inside and outside Interconnection.
6. module SiP structure according to claim 1, it is characterised in that: the stiffening plate is fixed by detachable member In in shell, LTCC upper substrate surface is pasted with bare chip, flip-chip, and the bare chip and flip-chip pass through metal wire reality Now it is electrically connected;Manufacture has passive device on LTCC lower substrate;It is more that the LTCC upper substrate and LTCC lower substrate are all made of LTCC Layer wiring, and pass through insulator or ceramic block wire bonding between the two.
7. module SiP structure according to claim 1, it is characterised in that: HTCC substrate and base under LTCC upper substrate, LTCC It is connected between plate by soft arranging wire.
8. the manufacturing method of module SiP structure according to claim 1, which comprises the following steps:
(1) integrated case package: the welding of shell outer lead, peripheral frame welding;
(2) LTCC upper substrate and its device assembling: being processed by shot blasting LTCC upper substrate surface, and after implementing thin-film technique, Filled under DSP back-off weldering and epoxy resin;Chip is buckled to postwelding, and surface protection is got up;By LTCC upper substrate surface device Part welding and the welding of substrate and stiffening plate are completed at the same time;Then remaining chip, component welded, be adhered to LTCC Substrate completes bonding;
(3) LTCC lower substrate device assembles: by the way that the passive device of signal circuit section is welded to LTCC lower substrate surface;
(4) HTCC substrate and its surface device assembling: entering shell for the device of driving circuit section and HTCC substrate synchronous welding, Then the bonding and wire bonding of surface device are carried out, and carries out the test of the partial circuit function;
(5) LTCC lower substrate is fixedly connected with stiffening plate, and LTCC upper and lower base plate is connect with HTCC shell;
(6) stiffening plate is fixed in shell, then tests, seals.
9. the manufacturing method of module SiP structure according to claim 8, it is characterised in that: the LTCC lower substrate device In assembling, solder melt point is 179 degree, and technological temperature is 230-250 degree.
10. the manufacturing method of module SiP structure according to claim 8, it is characterised in that: the LTCC lower substrate uses Wear Characteristics of Epoxy Adhesive is connected to stiffening plate, and the LTCC upper and lower base plate, HTCC substrate are mutually interconnected by gold wire bonding or soft arranging wire with shell It connects, the stiffening plate is fixed in shell by screw.
CN201910457970.7A 2019-05-29 2019-05-29 Module SiP structure and manufacturing method thereof Active CN110176439B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910457970.7A CN110176439B (en) 2019-05-29 2019-05-29 Module SiP structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910457970.7A CN110176439B (en) 2019-05-29 2019-05-29 Module SiP structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN110176439A true CN110176439A (en) 2019-08-27
CN110176439B CN110176439B (en) 2024-06-18

Family

ID=67696072

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910457970.7A Active CN110176439B (en) 2019-05-29 2019-05-29 Module SiP structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN110176439B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111627875A (en) * 2020-06-28 2020-09-04 中国电子科技集团公司第十四研究所 High heat conduction heat abstractor
CN114594351A (en) * 2022-03-18 2022-06-07 国网浙江省电力有限公司电力科学研究院 Transformer bushing partial discharge monitoring chip device and method
CN117202545A (en) * 2023-08-30 2023-12-08 山东航天电子技术研究所 High-density packaging structure and packaging method of aerospace module power supply

Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040090756A1 (en) * 2002-11-07 2004-05-13 Kwun-Yo Ho Chip packaging structure and manufacturing process thereof
US20040145039A1 (en) * 2003-01-23 2004-07-29 St Assembly Test Services Ltd. Stacked semiconductor packages and method for the fabrication thereof
US20060245308A1 (en) * 2005-02-15 2006-11-02 William Macropoulos Three dimensional packaging optimized for high frequency circuitry
US20070096335A1 (en) * 2005-10-28 2007-05-03 Houng-Kyu Kwon Chip stack structure having shielding capability and system-in-package module using the same
US20080029869A1 (en) * 2006-08-01 2008-02-07 Samsung Electronics Co., Ltd. Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability
US20080121878A1 (en) * 2006-07-12 2008-05-29 Moriyoshi Nakashima Interposer, semiconductor chip mounted sub-board, and semiconductor package
JP2009005262A (en) * 2007-06-25 2009-01-08 Olympus Imaging Corp Semiconductor device, and imaging apparatus
US20100244217A1 (en) * 2009-03-25 2010-09-30 Jong-Woo Ha Integrated circuit packaging system with stacked configuration and method of manufacture thereof
US20110140258A1 (en) * 2009-12-13 2011-06-16 Byung Tai Do Integrated circuit packaging system with package stacking and method of manufacture thereof
US20110156224A1 (en) * 2009-12-25 2011-06-30 Sony Corporation Circuit-substrate laminated module and electronic apparatus
KR20120058118A (en) * 2010-11-29 2012-06-07 삼성전자주식회사 Method of fabricating stacked package, and method of mounting stacked package fabricated by the same
KR20140045248A (en) * 2012-10-08 2014-04-16 에스티에스반도체통신 주식회사 Integrated circuit package and method for manufacturing the same
CN104538311A (en) * 2014-12-05 2015-04-22 中国航天科技集团公司第九研究院第七七一研究所 LTCC substrate 3D laminating structure
CN105762117A (en) * 2016-05-06 2016-07-13 中国工程物理研究院电子工程研究所 Staggered laminated three-dimensional packaging structure of LTCC substrates
CN107085270A (en) * 2017-06-20 2017-08-22 中国电子科技集团公司第四十三研究所 A kind of single-wavelength light receiving and transmitting integrated module
US20170301606A1 (en) * 2016-04-19 2017-10-19 Hyundai Mobis Co., Ltd. Bidirectional semiconductor package
CN108269775A (en) * 2018-01-24 2018-07-10 中国科学院地质与地球物理研究所 A kind of system-in-a-package method and package system based on 3D printing
US20180261569A1 (en) * 2016-12-07 2018-09-13 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming a 3D Interposer System-in-Package Module
CN109256373A (en) * 2018-09-29 2019-01-22 中国电子科技集团公司第四十三研究所 I/F converting system 3 D stereo encapsulating structure and packaging method
CN210403713U (en) * 2019-05-29 2020-04-24 中国电子科技集团公司第四十三研究所 Module SiP structure

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040090756A1 (en) * 2002-11-07 2004-05-13 Kwun-Yo Ho Chip packaging structure and manufacturing process thereof
US20040145039A1 (en) * 2003-01-23 2004-07-29 St Assembly Test Services Ltd. Stacked semiconductor packages and method for the fabrication thereof
US20060245308A1 (en) * 2005-02-15 2006-11-02 William Macropoulos Three dimensional packaging optimized for high frequency circuitry
US20070096335A1 (en) * 2005-10-28 2007-05-03 Houng-Kyu Kwon Chip stack structure having shielding capability and system-in-package module using the same
US20080121878A1 (en) * 2006-07-12 2008-05-29 Moriyoshi Nakashima Interposer, semiconductor chip mounted sub-board, and semiconductor package
US20080029869A1 (en) * 2006-08-01 2008-02-07 Samsung Electronics Co., Ltd. Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability
JP2009005262A (en) * 2007-06-25 2009-01-08 Olympus Imaging Corp Semiconductor device, and imaging apparatus
US20100244217A1 (en) * 2009-03-25 2010-09-30 Jong-Woo Ha Integrated circuit packaging system with stacked configuration and method of manufacture thereof
US20110140258A1 (en) * 2009-12-13 2011-06-16 Byung Tai Do Integrated circuit packaging system with package stacking and method of manufacture thereof
US20110156224A1 (en) * 2009-12-25 2011-06-30 Sony Corporation Circuit-substrate laminated module and electronic apparatus
KR20120058118A (en) * 2010-11-29 2012-06-07 삼성전자주식회사 Method of fabricating stacked package, and method of mounting stacked package fabricated by the same
KR20140045248A (en) * 2012-10-08 2014-04-16 에스티에스반도체통신 주식회사 Integrated circuit package and method for manufacturing the same
CN104538311A (en) * 2014-12-05 2015-04-22 中国航天科技集团公司第九研究院第七七一研究所 LTCC substrate 3D laminating structure
US20170301606A1 (en) * 2016-04-19 2017-10-19 Hyundai Mobis Co., Ltd. Bidirectional semiconductor package
CN105762117A (en) * 2016-05-06 2016-07-13 中国工程物理研究院电子工程研究所 Staggered laminated three-dimensional packaging structure of LTCC substrates
US20180261569A1 (en) * 2016-12-07 2018-09-13 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming a 3D Interposer System-in-Package Module
CN107085270A (en) * 2017-06-20 2017-08-22 中国电子科技集团公司第四十三研究所 A kind of single-wavelength light receiving and transmitting integrated module
CN108269775A (en) * 2018-01-24 2018-07-10 中国科学院地质与地球物理研究所 A kind of system-in-a-package method and package system based on 3D printing
CN109256373A (en) * 2018-09-29 2019-01-22 中国电子科技集团公司第四十三研究所 I/F converting system 3 D stereo encapsulating structure and packaging method
CN210403713U (en) * 2019-05-29 2020-04-24 中国电子科技集团公司第四十三研究所 Module SiP structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111627875A (en) * 2020-06-28 2020-09-04 中国电子科技集团公司第十四研究所 High heat conduction heat abstractor
CN114594351A (en) * 2022-03-18 2022-06-07 国网浙江省电力有限公司电力科学研究院 Transformer bushing partial discharge monitoring chip device and method
WO2023174448A1 (en) * 2022-03-18 2023-09-21 国网浙江省电力有限公司电力科学研究院 Transformer bushing partial discharge monitoring chip device and method
CN117202545A (en) * 2023-08-30 2023-12-08 山东航天电子技术研究所 High-density packaging structure and packaging method of aerospace module power supply
CN117202545B (en) * 2023-08-30 2024-05-10 山东航天电子技术研究所 High-density packaging structure of aerospace module power supply

Also Published As

Publication number Publication date
CN110176439B (en) 2024-06-18

Similar Documents

Publication Publication Date Title
CN101877348B (en) System and method for embedded chip package with chips stacked in an interconnecting laminate
CN102241388B (en) MEMS (micro electro mechanical system) wafer-level three-dimensional mixing integration packaging structure and method
US6492726B1 (en) Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US20180242455A1 (en) 3-d stacking of active devices over passive devices
CN110176439A (en) A kind of module SiP structure and its manufacturing method
CN101587847B (en) Perpendicular interconnection multi-chip assembly encapsulation method by PCB substrate
CN107579009A (en) A kind of multi-chip laminated packaging structure and preparation method thereof
CN105552065A (en) System-level package structure of T/R assembly control module and package method of system-level package structure
JPH03112688A (en) Ic card
CN106744646A (en) MEMS chip encapsulating structure and method for packing
CN107324274A (en) The package carrier three-dimensionally integrated for SIP
CN110211946A (en) A kind of chip-packaging structure and its manufacturing method
CN102176450B (en) High-density system-in-package structure
CN107507816A (en) Fan-out-type wafer scale multilayer wiring encapsulating structure
CN114314495A (en) MEMS integrated packaging structure and preparation method thereof
CN102937663B (en) The encapsulating structure of kernel module of intelligent electricity meter and method for packing
CN110246812A (en) A kind of semiconductor package and preparation method thereof
CN210403713U (en) Module SiP structure
CN208433405U (en) Circuit unit
CN115863315A (en) Packaging structure, electronic device and packaging method
CN108183098A (en) The 3D staggered floor stack package structures of mass storage circuit
CN209183532U (en) A kind of microelectronic component integrative packaging structure
CN111128918B (en) Chip packaging method and chip
CN100433327C (en) Chip packaging body and stack chip packaging structure
CN102253264A (en) Multi-chip hybrid packaged Hall effect current sensing module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant