CN110137274A - A kind of p-type high-efficiency battery and preparation method thereof of passivation on double surfaces contact - Google Patents
A kind of p-type high-efficiency battery and preparation method thereof of passivation on double surfaces contact Download PDFInfo
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- CN110137274A CN110137274A CN201910437603.0A CN201910437603A CN110137274A CN 110137274 A CN110137274 A CN 110137274A CN 201910437603 A CN201910437603 A CN 201910437603A CN 110137274 A CN110137274 A CN 110137274A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 36
- 238000002161 passivation Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 42
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 229910004205 SiNX Inorganic materials 0.000 claims abstract description 15
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000007639 printing Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 239000000243 solution Substances 0.000 claims description 8
- 229910017604 nitric acid Inorganic materials 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 238000002310 reflectometry Methods 0.000 claims description 4
- 238000007650 screen-printing Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HJELPJZFDFLHEY-UHFFFAOYSA-N silicide(1-) Chemical compound [Si-] HJELPJZFDFLHEY-UHFFFAOYSA-N 0.000 claims 9
- 235000008216 herbs Nutrition 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 210000002268 wool Anatomy 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 7
- 238000005215 recombination Methods 0.000 abstract description 7
- 230000006798 recombination Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 2
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 2
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006388 chemical passivation reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention discloses a kind of preparation methods of the p-type high-efficiency battery of passivation on double surfaces contact, comprising the following steps: S1, cleaning and texturing；S2, the preparation of front polysilicon；S3, exposure mask is prepared；S4, etching；S5, diffusion；S6, cleaning；S7, annealing；S8, the preparation of back side polysilicon layer；S9, the preparation of front SiNx antireflection layer；S10, printing.The invention also discloses a kind of p-type high-efficiency battery of passivation on double surfaces contact, including p type single crystal silicon, the N-type emitter is provided with the ultra-thin silicon oxide layer in front far from p type single crystal silicon；The p type single crystal silicon back side is provided with the ultra-thin silicon oxide layer in the back side.The present invention utilizes tunnel oxidation layer to be passivated contact structures in the tow sides of battery, has good surface passivation effect, silicon face is passivated immediately below front metal grid line and below the Al-BSF of the back side, metal is avoided to contact with the direct of silicon substrate, reduce surface recombination, promotes battery conversion efficiency.
Description
Technical field
The present invention relates to battery passivation technical field, specially a kind of the p-type high-efficiency battery and its system of passivation on double surfaces contact
Preparation Method.
Background technique
The efficiency of system crystal silicon solar batteries rises quickly in recent years, and demand of the market to high-efficiency battery and expectation are increasingly
Height, various new technologies, new construction are employed in nearest high-efficiency battery production, such as heterojunction structure (HIT) and tunnel oxygen
Change layer passivation contact (TOPCon) structure etc..
In every loss of solar battery, the loss of surface recombination occupies sizable specific gravity, and metal and silicon
The recombination losses of base contact position are also difficult to ignore.
In traditional PERC battery, contact of the front gate line with emitter is inevitable, although selective hair can be used
Emitter-base bandgap grading (SE) technology reduces surface recombination, but the disadvantage is that: contact of the metal with semiconductor still brings a large amount of compound, makes to open a way
Voltage Voc and short circuit current Isc incur loss.
Although the oxidation aluminium coat at the back side plays the role of passivated surface, but itself has insulating properties, need using
Laser, which is slotted, can just be such that back side Al-BSF contacts with silicon to collect carrier, and the size of laser aperture opening ratio influences whether table
The compound degree in face, but the disadvantage is that: the fill factor FF that will lead to battery is relatively low, there is certain limitation, limits PERC battery
The further promotion of efficiency.
The above-mentioned mode using selective emitter (SE) and laser slotting goes to reduce surface recombination reduction, and effect is inadequate
Good, defect is more obvious, so a kind of battery of novel passivation on double surfaces contact is needed to go to reduce surface recombination.
Summary of the invention
The purpose of the present invention is to provide a kind of p-type high-efficiency batteries and preparation method thereof of passivation on double surfaces contact, to solve
The problems mentioned above in the background art.
To achieve the above object, the invention provides the following technical scheme:
A kind of p-type high-efficiency battery of passivation on double surfaces contact, including p type single crystal silicon, the p type single crystal silicon front are provided with N
Type emitter, the N-type emitter are provided with the ultra-thin silicon oxide layer in front, the ultra-thin silica in front far from p type single crystal silicon
Layer top is provided with N-type polycrystalline silicon layer, and the ultra-thin conplane two sides of silicon oxide layer in front are provided with oxide layer, the N-type
Polysilicon layer and oxide layer are provided with SiNx antireflection layer, and Ag grid line is provided on N-type polycrystalline silicon layer, the Ag grid line
It is connected on N-type polycrystalline silicon layer across SiNx antireflection layer；
The p type single crystal silicon back side is provided with the ultra-thin silicon oxide layer in the back side, and the ultra-thin silicon oxide layer in the back side is far from p-type list
Crystal silicon side is provided with p-type polysilicon layer, is provided with Al back surface field below the p-type polysilicon layer.
A kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact, comprising the following steps: S1, cleaning and texturing: by P
Type monocrystalline silicon is once purged to prepare special suede structure, controls p type single crystal silicon surface reflectivity in 9-11%；
S2, the preparation of front polysilicon: one layer of ultra-thin silica in front is prepared in the p type single crystal silicon front for having prepared flannelette
Layer and one layer of N-type polycrystalline silicon layer, the thickness control of the ultra-thin silicon oxide layer in front use hot HNO in 1-2nm3Solution oxide or
The preparation of dry oxidation method, the thickness control of N-type polycrystalline silicon layer use PECVD to prepare in 30-50nm；
S3, it prepares exposure mask: preparing one layer of exposure mask, the figure and Ag of exposure mask in N-type polycrystalline silicon layer surface screen printing
Grid line figure is consistent；
S4, etching: HNO is used3With the mixed solution of HF, front side of silicon wafer is performed etching, is removing unmasked areas just
The ultra-thin silicon oxide layer in face and N-type polycrystalline silicon layer, then remove exposure mask；
S5, diffusion: High temperature diffusion is carried out in the front of silicon wafer, forms N-type emitter；
S6, cleaning: the phosphorosilicate glass diffuseed to form and edge PN junction are removed；
S7, annealing: oxide layer is formed in the ultra-thin silicon oxide layer plane in front of silicon wafer；
S8, the preparation of back side polysilicon layer: the ultra-thin silicon oxide layer in one layer of back side and one layer of P are prepared at the back side of p type single crystal silicon
Type polysilicon layer, the thickness control of the ultra-thin silicon oxide layer in the back side use hot HNO in 1-2nm3Solution oxide or dry oxidation method
Preparation, the thickness control of p-type polysilicon layer use PECVD to prepare in 30-50nm；
S9, the preparation of front SiNx antireflection layer: SiNx antireflection layer is prepared with PECVD in front side of silicon wafer, controls thickness
In 60-90nm, refractive index in 2.08-2.12；
S10, printing: Ag grid line is printed on positive N-type polycrystalline silicon layer, and is printed on p-type polysilicon layer overleaf
Al back surface field.
Preferably, suede structure includes pyramid and reverse pyramid.
Preferably, in step S4, used HNO3It is 45%-50%:6%-8% with HF concentration ratio.
Compared with prior art, the beneficial effects of the present invention are:
Tunnel oxidation layer passivation contact (TOPCon) structure of the invention not only has good chemical passivation effect, utilizes
What the polysilicon that the oxide layer of one layer of ultra-thin permission electron hole tunnelling is adulterated with one layer of N-type or p-type formed, different doping
Type has different carrier selectivity, while avoiding directly contacting for metal electrode and silicon substrate, reduces compound, mentions
High battery efficiency.
The present invention utilizes tunnel oxidation layer to be passivated contact structures in the tow sides of battery, has good surface passivation
Effect is passivated silicon face immediately below front metal grid line and below the Al-BSF of the back side, avoids metal and silicon substrate
Direct contact, reduce surface recombination, promoted battery conversion efficiency.
Detailed description of the invention
Fig. 1 is overall structure diagram of the invention；
Fig. 2 is preparation method flow diagram of the invention.
In figure: 1P type monocrystalline silicon, the ultra-thin silicon oxide layer in 2 fronts, 3N type polysilicon layer, 4N type emitter, 5 oxide layers, 6 back
The ultra-thin silicon oxide layer in face, 7P type polysilicon layer, 8SiNx antireflection layer, 9Ag grid line, 10Al back surface field.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention provides a kind of technical solution referring to FIG. 1-2:
A kind of p-type high-efficiency battery of passivation on double surfaces contact, including p type single crystal silicon 1,1 front of p type single crystal silicon are provided with N-type
Emitter 4, N-type emitter 4 are provided with the ultra-thin silicon oxide layer 2 in front, ultra-thin 2 top of silicon oxide layer in front far from p type single crystal silicon 1
It is provided with N-type polycrystalline silicon layer 3, the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 are in same vertical plane, and N-type polycrystalline
Silicon layer 3 covers the ultra-thin silicon oxide layer 2 in front completely, forms extraordinary tunnel oxidation layer passivation contact structures, the ultra-thin oxygen in front
The conplane two sides of SiClx layer 2 are provided with oxide layer 5, aoxidize to be formed by subsequent anneal, and oxide layer 5 is silicon oxide layer, with
Ultra-thin 2 thickness of silicon oxide layer in front is identical, and SiNx antireflection layer 8, and N-type are provided with above N-type polycrystalline silicon layer 3 and oxide layer 5
Ag grid line 9 is provided on polysilicon layer 3, Ag grid line 9 passes through SiNx antireflection layer 8 and is connected on N-type polycrystalline silicon layer 3.
1 back side of p type single crystal silicon is provided with the ultra-thin silicon oxide layer 6 in the back side, and the ultra-thin silicon oxide layer 6 in the back side is far from p type single crystal silicon 1
Side is provided with p-type polysilicon layer 7, forms the tunnel oxidation layer passivation contact structures at the back side, is arranged below p-type polysilicon layer 7
There is Al back surface field 10.
A kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact, comprising the following steps: S1, cleaning and texturing: by P
Type monocrystalline silicon 1 is once purged to prepare special suede structure, and suede structure includes pyramid and reverse pyramid, controls p-type list
1 surface reflectivity of crystal silicon is in 9-11%；
S2, the preparation of front polysilicon: in the 1 front one layer of ultra-thin oxidation in front of preparation of p type single crystal silicon for having prepared flannelette
Silicon layer 2 and one layer of N-type polycrystalline silicon layer 3, the thickness control of the ultra-thin silicon oxide layer 2 in front use hot HNO3 solution oxygen in 1-2nm
Change or the preparation of dry oxidation method, the thickness control of N-type polycrystalline silicon layer 3 use PECVD to prepare in 30-50nm；
S3, it prepares exposure mask: preparing one layer of exposure mask, the figure and Ag of exposure mask in 3 surface screen printing of N-type polycrystalline silicon layer
9 figure of grid line is consistent；
S4, etching: HNO is used3With the mixed solution of HF, used HNO3It is 45%-50%:6%- with HF concentration ratio
8%, front side of silicon wafer is performed etching, the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 of unmasked areas is removed, then goes
Except exposure mask；
S5, diffusion: High temperature diffusion is carried out in the front of silicon wafer, forms N-type emitter 4；
S6, cleaning: the phosphorosilicate glass diffuseed to form and edge PN junction are removed；
S7, annealing: oxide layer 5 is formed in ultra-thin 2 plane of silicon oxide layer in front of silicon wafer；
S8, the preparation of back side polysilicon layer: the ultra-thin silicon oxide layer 6 in one layer of back side and one layer are prepared at the back side of p type single crystal silicon 1
P-type polysilicon layer 7, the thickness control of the ultra-thin silicon oxide layer 6 in the back side use hot HNO in 1-2nm3Solution oxide or dry method oxygen
The preparation of change method, the thickness control of p-type polysilicon layer 7 use PECVD to prepare in 30-50nm；
Prepared by S9, front SiNx antireflection layer 8: preparing SiNx antireflection layer 8 in front side of silicon wafer with PECVD, control is thick
Degree is in 60-90nm, refractive index in 2.08-2.12；
S10, printing: printing Ag grid line 9 on positive N-type polycrystalline silicon layer 3, and figure is consistent with the mask pattern in S3,
And Al back surface field 10 is printed on p-type polysilicon layer 7 overleaf.
Embodiment one:
A kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact, comprising the following steps:
S1, cleaning and texturing: special suede structure is prepared by p type single crystal silicon 1 is once purged, suede structure includes pyramid
And reverse pyramid, 1 surface reflectivity of p type single crystal silicon is controlled 10%；
S2, the preparation of front polysilicon: in the 1 front one layer of ultra-thin oxidation in front of preparation of p type single crystal silicon for having prepared flannelette
Silicon layer 2 and one layer of N-type polycrystalline silicon layer 3, the thickness control of the ultra-thin silicon oxide layer 2 in front use dry oxidation legal system in 1nm
Standby, the thickness control of N-type polycrystalline silicon layer 3 uses PECVD to prepare in 30nm；
S3, it prepares exposure mask: preparing one layer of exposure mask, the figure and Ag of exposure mask in 3 surface screen printing of N-type polycrystalline silicon layer
9 figure of grid line is consistent, and the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 are hidden；
S4, etching: HNO is used3With the mixed solution of HF, used HNO3It is 50%:8% with HF concentration ratio, to silicon wafer
Front performs etching, and removes the ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 of unmasked areas, i.e., by the ultra-thin oxidation in front
The ultra-thin silicon oxide layer 2 in front and N-type polycrystalline silicon layer 3 of 2 two sides of silicon layer are got rid of, and covering on N-type polycrystalline silicon layer 3 is then removed
Film；
S5, diffusion: High temperature diffusion is carried out in the front of silicon wafer, forms N-type emitter 4；
S6, cleaning: the phosphorosilicate glass diffuseed to form and edge PN junction are removed；
S7, annealing: oxide layer 5 is formed in ultra-thin 2 plane of silicon oxide layer in front of silicon wafer；
S8, the preparation of back side polysilicon layer: the ultra-thin silicon oxide layer 6 in one layer of back side and one layer are prepared at the back side of p type single crystal silicon 1
P-type polysilicon layer 7, the thickness control of the ultra-thin silicon oxide layer 6 in the back side use hot HNO in 1nm3Solution oxide or dry oxidation
Method preparation, the thickness control of p-type polysilicon layer 7 use PECVD to prepare in 30nm；
Prepared by S9, front SiNx antireflection layer 8: preparing SiNx antireflection layer 8 in front side of silicon wafer with PECVD, control is thick
Degree is in 60nm, refractive index 2.10；
S10, printing: Ag grid line 9 is printed on positive N-type polycrystalline silicon layer 3, and is printed on p-type polysilicon layer 7 overleaf
Brush Al back surface field 10.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (4)
1. a kind of p-type high-efficiency battery of passivation on double surfaces contact, including p type single crystal silicon (1), it is characterised in that: the p type single crystal silicon
(1) front is provided with N-type emitter (4), and the N-type emitter (4) is provided with the ultra-thin oxidation in front far from p type single crystal silicon (1)
Silicon layer (2), the ultra-thin silicon oxide layer in front (2) top is provided with N-type polycrystalline silicon layer (3), and the ultra-thin silicon oxide layer (2) in front
Conplane two sides are provided with oxide layer (5), are provided with SiNx anti-reflection above the N-type polycrystalline silicon layer (3) and oxide layer (5)
It penetrates layer (8), and is provided with Ag grid line (9) on N-type polycrystalline silicon layer (3), the Ag grid line (9) connects across SiNx antireflection layer (8)
It is connected on N-type polycrystalline silicon layer (3)；
P type single crystal silicon (1) back side is provided with the ultra-thin silicon oxide layer in the back side (6), and the ultra-thin silicon oxide layer in the back side (6) is separate
P type single crystal silicon (1) side is provided with p-type polysilicon layer (7), is provided with Al back surface field (10) below the p-type polysilicon layer (7).
2. a kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact, which comprises the following steps: S1, cleaning
Making herbs into wool: special suede structure is prepared by p type single crystal silicon (1) is once purged, controls p type single crystal silicon (1) surface reflectivity in 9-
11%；
S2, the preparation of front polysilicon: in the one layer of ultra-thin silica in front of p type single crystal silicon (1) front preparation for having prepared flannelette
Layer (2) and one layer of N-type polycrystalline silicon layer (3), the thickness control of the ultra-thin silicon oxide layer (2) in front use hot HNO in 1-2nm3It is molten
Liquid oxidation or the preparation of dry oxidation method, the thickness control of N-type polycrystalline silicon layer (3) use PECVD to prepare in 30-50nm；
S3, it prepares exposure mask: preparing one layer of exposure mask, the figure and Ag grid of exposure mask in N-type polycrystalline silicon layer (3) surface screen printing
Line (9) figure is consistent；
S4, etching: HNO is used3With the mixed solution of HF, front side of silicon wafer is performed etching, the front for removing unmasked areas is ultra-thin
Silicon oxide layer (2) and N-type polycrystalline silicon layer (3), then remove exposure mask；
S5, diffusion: High temperature diffusion is carried out in the front of silicon wafer, is formed N-type emitter (4)；
S6, cleaning: the phosphorosilicate glass diffuseed to form and edge PN junction are removed；
S7, annealing: oxide layer (5) are formed in ultra-thin silicon oxide layer (2) plane in front of silicon wafer；
S8, the preparation of back side polysilicon layer: one layer of ultra-thin silicon oxide layer in the back side (6) and one layer are prepared at the back side of p type single crystal silicon (1)
P-type polysilicon layer (7), the thickness control of the ultra-thin silicon oxide layer in the back side (6) use hot HNO in 1-2nm3Solution oxide is dry
The preparation of method oxidizing process, the thickness control of p-type polysilicon layer (7) use PECVD to prepare in 30-50nm；
S9, front SiNx antireflection layer (8) preparation: SiNx antireflection layer (8) are prepared with PECVD in front side of silicon wafer, control is thick
Degree is in 60-90nm, refractive index in 2.08-2.12；
S10, printing: Ag grid line (9) are printed on positive N-type polycrystalline silicon layer (3), and on p-type polysilicon layer (7) overleaf
It prints Al back surface field (10).
3. a kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact according to claim 2, it is characterised in that:
Suede structure includes pyramid and reverse pyramid.
4. a kind of preparation method of the p-type high-efficiency battery of passivation on double surfaces contact according to claim 2, it is characterised in that:
In step S4, used HNO3It is 45%-50%:6%-8% with HF concentration ratio.
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