CN110136759B

CN110136759B - Circuit for reducing data disturbance caused by read operation

Info

Publication number: CN110136759B
Application number: CN201810130957.6A
Authority: CN
Inventors: 叶力; 戴瑾; 夏文斌
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2018-02-09
Filing date: 2018-02-09
Publication date: 2021-01-12
Anticipated expiration: 2038-02-09
Also published as: CN110136759A

Abstract

The invention discloses a circuit for reducing data disturbance caused by read operation, wherein a storage unit to be tested is connected with a bit line and a source line, and a selection tube is connected between the source line and the storage unit to be tested; further comprising: the comparison amplifying circuit is connected with a current mirror circuit, and the bit line and the source line are connected with a current direction selection switch; the current direction selection switch is connected to the current mirror circuit. The invention effectively solves the problem that the read current can generate certain writing action in a certain direction and has disturbance effect on the stored data, the memory unit to be tested is connected to the bit line and the source line through the selection tube, and a selection switch is additionally arranged to configure the direction of the read current before a comparison amplification circuit is accessed to read signals. The disturbance influence of the read operation on the information stored in the memory cell is reduced. The flexibility of the current direction configuration of the reading circuit is increased, and the error rate of the MRAM can be reduced in a targeted manner according to different application requirements and the process performance of the storage unit.

Description

Circuit for reducing data disturbance caused by read operation

Technical Field

The present invention relates to a circuit, and more particularly, to a circuit for reducing data disturbance caused by read operation applied in MRAM technology.

Background

MRAM is a new memory and storage technology, can be read and written randomly as SRAM/DRAM, and can permanently retain data after power failure as Flash memory.

The chip has good economy, and the silicon chip area occupied by unit capacity has great advantages compared with SRAM, NOR Flash frequently used in the chips and embedded NOR Flash. Its performance is also quite good, the read-write time delay is close to the best SRAM, and the power consumption is the best in various memory and storage technologies. Also MRAM is not compatible with standard CMOS semiconductor processes like DRAM and Flash. The MRAM may be integrated with the logic circuit in one chip.

The principle of MRAM is based on a structure called MTJ (magnetic tunnel junction). It is composed of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material. The lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer with a variable magnetization direction, which may be parallel or anti-parallel to the fixed magnetization layer. Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has a low resistance and the latter case has a high resistance. The process of reading the MRAM is to measure the resistance of the MTJ. Using the newer STT-MRAM technology, writing to MRAM is also simpler: write operations are performed through the MTJ using a stronger current than read. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.

Each memory cell of MRAM consists of an MTJ and a MOS transistor. The gate of the MOS tube is connected to Word Line of the chip to switch on or off the unit, and the MTJ and the MOS tube are connected in series on Bit Line of the chip. Read-write operations are performed on Bit Line

The read process of an MRAM is the detection and comparison of the resistance of the memory cell. Whether the memory cell is in the high resistance state or the low resistance state is generally determined by combining the reference cells into a standard resistance to compare with the memory cell.

As shown, fig. 1 is a circuit diagram of a prior art sense amplifier circuit, which is a popular design: p1, P2 and P3 are the same PMOS tubes, forming a current mirror, and the current of each path above is equal (I _ read). The difference in resistance causes a difference between V _ out and V _ out _ n, which is input to the comparator of the next stage to generate an output. The example in the figure is a path of memory cells, comparing a path of reference cells in the P state with a path of reference cells in the AP state. In actual use, multiple memory cells can be compared with m AP and n P reference cells.

The sense amplifier circuit design has the advantage of using multiple reference cells in parallel averaging to offset the floating of memory cell resistance due to non-uniformity of the process. The disadvantage is that in the sense operation the direction of the current through the memory cell is fixed, i.e.: for the memory cell in the high resistance state or the low resistance state, the current direction from the bit line to the source line is applied. Considering that the direction of the write current of a memory cell is binary, the read current will produce a certain writing action in a certain direction, having a disturbing effect on the stored data.

Disclosure of Invention

In view of the foregoing defects in the prior art, the technical problem to be solved by the present invention is to provide a circuit for reducing data disturbance caused by read operation, wherein a memory cell to be tested is connected to a bit line and a source line, and a select transistor is connected between the source line and the memory cell to be tested; further comprising: the comparison amplifying circuit is connected with a current mirror circuit, and the bit line and the source line are connected with a current direction selection switch; the current direction selection switch is connected to the current mirror circuit.

Preferably, the current direction selection switch selects a current to flow from the memory cell to be tested to the selection tube or from the selection tube to the memory cell to be tested.

Preferably, the power supply further comprises a control signal terminal, and the control signal terminal is connected with the current direction selection switch.

Preferably, the current direction selection switch includes: two branch circuits are connected respectively on the bit line, source line, branch circuit includes: the first NMOS is connected between the input end and the output end, and a first inverter and a second NMOS are connected between the input end and the output end in series; the first NMOS gate of one said branch circuit is connected to the second NMOS gate of another said branch circuit by a connection line, and further comprising: and a control signal end outputs control signals to the two connecting wires, and the control signal end controls and changes the potentials of the two output ends and controls the current direction.

Preferably, the control signal end is connected with one of the connecting lines, and a second inverter is connected in series between the control signal end and the other connecting line.

Preferably, the current mirror circuit has a reference signal output end and a signal output end to be measured, and the reference signal output end and the signal output end to be measured are respectively connected to the two input ends of the comparison amplifying circuit.

Compared with the prior art, the invention effectively solves the problems that the reading current can generate certain writing action in a certain direction and has disturbance effect on the stored data, the memory unit to be tested is connected to the bit line and the source line through the selection tube, and a selection switch is additionally arranged to configure the direction of the reading current before a signal is read by the comparison and amplification circuit. The disturbance influence of the read operation on the information stored in the memory cell is reduced. The flexibility of the current direction configuration of the reading circuit is increased, and the error rate of the MRAM can be optimized in a targeted manner according to different application requirements and the process performance of the storage unit.

The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.

Drawings

FIG. 1 is a circuit diagram of a prior art sense amplifier circuit;

FIG. 2 is a circuit diagram of the present invention;

fig. 3 is a circuit diagram of a first embodiment of the present invention.

Detailed Description

As shown in the figure, fig. 2 is a circuit diagram of the present invention, which is a circuit for reducing data disturbance caused by read operation, wherein a memory cell 1 to be tested is connected to a bit line 3 and a source line 4, and a select transistor 2 is connected between the source line 4 and the memory cell 1 to be tested; further comprising: the comparison amplifying circuit is connected with a current mirror circuit, a current direction selection switch 5 is connected between the bit line 3, the source line 4 and the two comparison ends, and the current direction selection switch is connected with the current mirror circuit. The disturbing effect of the read current on the memory cell depends on the ratio of the critical switching current of the memory cell itself to the magnitude of the applied current. The memory unit 1 to be tested is connected to a bit line 3 and a source line 4 through a selection tube 2, a selection switch is additionally arranged to configure the direction of a reading current before a signal is read by a comparison amplification circuit, and the reading current flows from the selection tube 2 to the memory unit 1 to be tested under the default condition. The selection switch can also be controlled by the test mode to configure the read current to flow from the memory cell 1 to be tested to the selection tube 2.

Further, the current direction selection switch 5 selects the current to flow from the memory cell 1 to be tested to the selection tube 2 or from the selection tube 2 to the memory cell 1 to be tested.

Furthermore, the device also comprises a control signal terminal 7, and the control signal terminal 7 is connected with the current direction selection switch 5.

Fig. 3 is a circuit diagram of a first embodiment of the present invention, and further, the current direction selection switch 5 includes: two branch circuits are connected respectively on bit line 3, source line 4, and the branch circuit includes: input end, output end, a first NMOS53 is connected between the input end and the output end, a first inverter 52, a second NMOS51 is connected in series between the input end and the output end; the gate of the first NMOS53 of one branch circuit is connected with the gate of the second NMOS51 of the other branch circuit through a connecting wire, and the circuit further comprises: a control signal terminal 7 outputs control signals to the two connecting wires, and the control signal terminal 7 controls and changes the potentials of the two output terminals to control the current direction.

Further, the control signal terminal 7 is connected to a connection line, and a second inverter 71 is connected in series between the control signal terminal 7 and the other connection line.

Furthermore, the current mirror circuit is provided with a reference signal output end and a signal output end to be measured, and the reference signal output end and the signal output end to be measured are respectively connected with the two input ends of the comparison amplifying circuit.

Specifically, the voltage signal on the bit line bitline may be applied to the resistor to be measured through the point C in the current mirror circuit.

The principle of the invention is as follows: during reading operation, a predetermined voltage is configured between the bit line 3 and the source line 4, the voltage is distributed between the memory cell and the NMOS of the selection tube, the voltage obtained by dividing the high-resistance state memory cell is higher than that obtained by dividing the low-resistance state memory cell, and the critical inversion voltage required by the high-resistance state memory cell is generally higher than that of the low-resistance state cell. The direction of the read current configuration should be determined according to the electrical characteristics of the memory cell and the specific design of the selection transistor 2 and the field effect transistor used in the sense amplifier. Generally speaking, the high resistance state memory cell is more likely to be disturbed by the read current. Therefore, the read current is configured in the reverse direction and the write current for the high resistance state by default, which helps the high resistance state memory cell to reduce read disturbance. If the result of the production line test shows that the low-resistance state is the direction which is easier to be disturbed, the configuration of the direction of the reading current is switched through the test mode, and the low-resistance state storage unit is helped to reduce the reading disturbance.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. A circuit for reducing data disturbance caused by read operation is characterized in that a memory unit to be tested is connected with a bit line and a source line, and a selection tube is connected between the source line and the memory unit to be tested; further comprising: the comparison amplifying circuit is connected with a current mirror circuit, and the bit line and the source line are connected with a current direction selection switch; the current direction selection switch is connected with the current mirror circuit; the control signal end is connected with the current direction selection switch; the current direction selection switch includes: two branch circuits are connected respectively on the bit line, source line, branch circuit includes: the first NMOS is connected between the input end and the output end, and a first inverter and a second NMOS are connected between the input end and the output end in series; the first NMOS gate electrode of one branch circuit is connected with the second NMOS gate electrode of the other branch circuit through a connecting wire; the control signal end outputs control signals to the two connecting wires, and the control signal end controls and changes the potentials of the two output ends and controls the current direction.

2. The circuit for reducing data disturbance due to read operation of claim 1, wherein the current direction selection switch selects whether a current flows from the memory cell under test to the select transistor or from the select transistor to the memory cell under test.

3. The circuit of claim 1, wherein the control signal terminal is connected to one of the connection lines, and a second inverter is connected in series between the control signal terminal and the other of the connection lines.

4. The circuit of claim 1, wherein the current mirror circuit has a reference signal output terminal and a signal-to-be-measured output terminal, and the reference signal output terminal and the signal-to-be-measured output terminal are respectively connected to two input terminals of the comparing and amplifying circuit.