CN110136666A - Sequence controller and timing control panel - Google Patents
Sequence controller and timing control panel Download PDFInfo
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- CN110136666A CN110136666A CN201910366280.0A CN201910366280A CN110136666A CN 110136666 A CN110136666 A CN 110136666A CN 201910366280 A CN201910366280 A CN 201910366280A CN 110136666 A CN110136666 A CN 110136666A
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- integrated circuit
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- physical address
- sequence controller
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
This announcement provides a kind of sequence controller and timing control panel.The sequence controller includes micro-control unit, interior integrated circuit from unit and Serial Peripheral Interface (SPI) master unit.The micro-control unit is to control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit.The sequence controller further includes a look-up table, to map physical address data of the interior integrated circuit from the logical address data of unit to the Serial Peripheral Interface (SPI) master unit.
Description
[technical field]
This announcement is related to field of display technology, in particular to a kind of sequence controller and timing control panel.
[background technique]
In liquid crystal television panel display industry, due to partial power managing chip (Power Manage Integral
Chip, PMIC) in nonvolatile semiconductor memory member is not present, but the data of configuration register in PMIC are stored in external sudden strain of a muscle
It deposits in (Flash Memory) and turns serial outer through interior integrated circuit (Inter-Integrated Circuit, I2C) bus
If interface (Serial Peripheral Interface, SPI) bus is accessed.
What current I2C turned the address expression in SPI protocol in the data read and write in flash memory, in data structure is flash memory
Actual physical address.But since the physical address that the register data that each supplier is supported stores in a flash memory is different,
The data of each supplier cannot be read with identical order by resulting in user.
Therefore it is in need a kind of sequence controller and timing control panel be provided, it is of the existing technology to solve the problems, such as.
[summary of the invention]
In order to solve the above technical problems, the one of this announcement is designed to provide a kind of sequence controller and timing control panel,
The uniformity that instruction can be reached facilitates the importing of address administration and product.
To reach above-mentioned purpose, this announcement provides a kind of sequence controller, including micro-control unit, interior integrated circuit are from list
Member and Serial Peripheral Interface (SPI) master unit.The micro-control unit is to execute following effect:
Control the interior integrated circuit from unit and outside first in integrated circuit master unit communicated；
The Serial Peripheral Interface (SPI) master unit is controlled to be communicated with external Serial Peripheral Interface (SPI) from unit；And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit.
The sequence controller further includes a look-up table, to map logical address number of the interior integrated circuit from unit
According to the physical address data to the Serial Peripheral Interface (SPI) master unit.
In this announcement embodiment therein, in described first integrated circuit master unit be located at power management chip it
In, the power management chip includes the first register cell and the second register cell.
In this announcement embodiment therein, the Serial Peripheral Interface (SPI) is located among flash cell from unit.Institute
Stating flash cell includes multiple storage sectors.The storage sector has respective physical address.First physical address is corresponding
Data of the storage sector to store first register cell.It uses the corresponding storage sector of second physical address
To store the data of second register cell.
In this announcement embodiment therein, the corresponding storage sector of first physical address and described the
The corresponding storage sector of two physical address is not adjacent.
In this announcement embodiment therein, if the micro-control unit is to judge institute in interior integrated circuit instruction
Stating logical address data is more than a default value, then is addressed to second physical address, is otherwise addressed to described first physically
Location.
In this announcement embodiment therein, the power management chip is to penetrate integrated circuit in described first
The interior integrated circuit of master unit and the sequence controller is stored in the flash cell from unit communications with reading
The data of the data of first register cell and second register cell.
In this announcement embodiment therein, the sequence controller may be electrically connected to external management module, institute
Stating management module includes integrated circuit master unit in second, and the management module is to penetrate the main list of integrated circuit in described second
First and the sequence controller the interior integrated circuit is stored in the flash cell from unit communications with being written or reading
First register cell data and second register cell data.
This announcement also provides a kind of timing control plate, including sequence controller, power management chip and flash cell.
The sequence controller includes micro-control unit, interior integrated circuit from unit and Serial Peripheral Interface (SPI) master unit.The micro-control
Unit processed is to execute following effect:
Interior integrated circuit integrated circuit master unit out of unit and the power management chip first is controlled to carry out
Communication；
The Serial Peripheral Interface (SPI) for controlling the Serial Peripheral Interface (SPI) master unit and the flash cell is communicated from unit；
And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit.
The sequence controller further includes a look-up table, to map logical address number of the interior integrated circuit from unit
According to the physical address data to the Serial Peripheral Interface (SPI) master unit.
In this announcement embodiment therein, the power management chip includes the first register cell and second
Register cell.The flash cell includes multiple storage sectors.The storage sector has respective physical address.First object
Manage data of the corresponding storage sector in address to store first register cell.The corresponding institute of second physical address
State data of the storage sector to store second register cell.The corresponding storage sector of first physical address
The storage sector corresponding with second physical address is not adjacent.
In this announcement embodiment therein, if the micro-control unit is to judge institute in interior integrated circuit instruction
Stating logical address data is more than a default value, then is addressed to second physical address, is otherwise addressed to described first physically
Location.
Since in the sequence controller and timing control panel of this revealed embodiment, the micro-control unit is to control
Data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit is stated, and the sequence controller also wraps
A look-up table is included, to map the interior integrated circuit from the logical address data of unit to the Serial Peripheral Interface (SPI) master unit
Physical address data.Therefore, the physical address image of the storage sector of the flash cell can be made solid to defaulting
Fixed logical address facilitates the importing of address administration and product.In addition, the micro-control unit judges seeking for the logical address
Location step can further reach the uniformity of instruction.
For the above content of this announcement can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's accompanying drawings, makees
Detailed description are as follows:
[Detailed description of the invention]
Fig. 1 shows the structural schematic diagram of the timing control plate of the embodiment according to this announcement；
Fig. 2 shows the data structure schematic diagram of the look-up table of the embodiment according to this announcement；
Fig. 3 is shown according to the interior integrated circuit of an embodiment of this announcement from the online of unit and interior integrated circuit master unit
Schematic diagram；
Fig. 4 is shown according to the Serial Peripheral Interface (SPI) master unit of an embodiment of this announcement and Serial Peripheral Interface (SPI) from unit
On-line mode schematic diagram；
Fig. 5 shows the micro-control unit decision logic address according to an embodiment of this announcement and is addressed to physical address
Steps flow chart schematic diagram；
Fig. 6 shows the instruction format schematic diagram of the interior integrated circuit unit of the embodiment according to this announcement；And
Fig. 7 shows the reading instruction execution flow schematic diagram of the interior integrated circuit unit of the embodiment according to this announcement.
[specific embodiment]
In order to which the above-mentioned and other purposes of this announcement, feature, advantage can be clearer and more comprehensible, it is excellent that spy is hereafter lifted into this announcement
Embodiment is selected, and cooperates institute's accompanying drawings, is described in detail below.Furthermore the direction term that this announcement is previously mentioned, such as above and below,
Top, bottom, front, rear, left and right, inside and outside, side layer, around, center, it is horizontal, laterally, vertically, longitudinally, axial direction, radial direction, top layer or
Lowest level etc. is only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand this announcement, and
It is non-to limit this announcement.
The similar unit of structure is to be given the same reference numerals in the figure.
Referring to Fig.1, this announcement provides a kind of sequence controller 100, including micro-control unit 110, interior integrated circuit are from list
Member 120 and Serial Peripheral Interface (SPI) master unit 130.The micro-control unit 110 is to execute following effect:
Control the interior integrated circuit from unit 120 and outside first in integrated circuit master unit 220 communicated；
The Serial Peripheral Interface (SPI) master unit 130 is controlled to be communicated with external Serial Peripheral Interface (SPI) from unit 330；With
And
Control data conversion of the interior integrated circuit between unit 120 and the Serial Peripheral Interface (SPI) master unit 130.
The sequence controller 100 further includes a look-up table 140, to map the interior integrated circuit from unit 120
Logical address data to the Serial Peripheral Interface (SPI) master unit 130 physical address data.
In this announcement embodiment therein, integrated circuit master unit 220 is located at power management core in described first
Among piece 200, the power management chip 200 includes the first register cell 20A and the second register cell 20B.
In this announcement embodiment therein, the Serial Peripheral Interface (SPI) from unit 330 be located at flash cell 300 it
In.The flash cell 300 include multiple storage sector 3S1,3S2,3S3 ... 3Sn.The storage sector 3S1,3S2,
3S3 ... 3Sn has respective physical address.The corresponding storage sector 3S1 of first physical address is to store described first
The data of register cell 20A.The corresponding storage sector 3S3 of second physical address is to store the second register list
The data of first 20B.
In this announcement embodiment therein, the corresponding storage sector 3S1 of first physical address and institute
It is not adjacent to state the corresponding storage sector 3S3 of the second physical address.
Specifically, referring to Fig. 2, in this announcement embodiment therein, data structure such as Fig. 2 of the look-up table 140
It is shown.The data volume of one register cell for example has 42 data.A storage sector is for example in the flash cell
4KB data can be deposited.Then the logical address number of first register cell is, for example, from 0 to 41.Correspond to the flash memory
It is, for example, 01F000h to 01F029h that the physical address of sector 3S1 is stored described in unit.First register cell is patrolled
Collecting address number is, for example, from 42 to 83.Correspond to described in the flash cell store sector 3S3 physical address be, for example,
03F000h to 03F029h.The physical address 01F000h to 01F029hea and the storage sector 3S3 of the storage sector 3S1
Physical address 03F000h to 03F029h it is not adjacent.
Specifically, the corresponding storage sector of first physical address and second physical address can be selected
The corresponding storage sector is adjacent or not adjacent, this announcement is without being limited thereto.The storage sector is not adjacent to increase the sudden strain of a muscle
The flexibility ratio of memory cell storage data.
Specifically, referring to Fig. 3, interior integrated circuit integrated circuit master unit 220 out of unit 120 and described first
On-line mode is as shown, interior integrated circuit unit bus is communicated using serial data line SDA and serial time clock line SCL.
Specifically, referring to Fig. 4, the Serial Peripheral Interface (SPI) master unit 130 and the Serial Peripheral Interface (SPI) are from unit 330
On-line mode is as shown, Serial Peripheral Interface (SPI) unit bus uses four interfaces: serial frequency line SCLK, it is main go out from entering line
MOSI, master enter from outlet MISO and slave selection line SS.
Referring to Fig. 5, in this announcement embodiment therein, if the micro-control unit 110 is interior integrated to judge
Logical address data described in circuit instruction is more than a default value, then is addressed to second physical address, is otherwise addressed to institute
State the first physical address.
Specifically, the judgment step of the micro-control unit 110 includes: step S10: receiving instruction；Step S20: sentence
Severed finger enable in logical address whether less than a register cell data volume；If so, thening follow the steps S30: being addressed to
One physical address；S40 is thened follow the steps if not: being addressed to the second physical address；After executing the step S30 or step S40, hold
Row step S50: reading or write-in data.
Specifically, micro-control unit decision logic address and being addressed to the programming language code of physical address for example:
Wherein offset is offset address, and CodeSize is the size of data of each register cell, and length is read-write
Data length, above numerical value are citing, this announcement is without being limited thereto.
Referring to Fig.1, in this announcement embodiment therein, the power management chip 200 is to through described the
The interior integrated circuit of integrated circuit master unit 220 and the sequence controller 100 is communicated from unit 120 in one, to read
Be stored in the first register cell 20A in the flash cell 300 data and the second register cell 20B
Data.
In this announcement embodiment therein, the sequence controller 100 may be electrically connected to external management module
400, the management module 400 includes integrated circuit master unit 420 in second, and the management module 400 is to through described the
The interior integrated circuit of integrated circuit master unit 420 and the sequence controller 100 is communicated from unit 120 in two, with write-in
Or read the data of the first register cell 20A being stored in the flash cell 300 and second register
The data of unit 20B.
Specifically, the instruction format of interior integrated circuit unit is as shown in the figure referring to Fig. 6.Interior integrated circuit master unit is sent
Initial signal Start communicates to open.All interior integrated circuits can enter after receiving initial signal Start from unit to be received
Data pattern.Then, interior integrated circuit master unit sends the address address of communication target device totally 7 and one readings
Or write R/W information.1 indicates to read, and 0 indicates to write.Come again, after interior integrated circuit receives address address from unit, meets the address
The interior integrated circuit of address can send the response Ack an of position from unit.Interior integrated circuit master unit receives response Ack meeting
The R/W information that reads or writes depending on its script enters reception or output mode.Then in the data of transmission, interior integrated circuit can from unit
To issue a response Ack at the end of the transmission of each byte.Finally, interior integrated circuit master unit issues at the end of transmission
Stop signal Stop.
Specifically, referring to Fig. 6 and Fig. 7, within integrated circuit unit reading instruction format for.As shown, described
Interior integrated circuit master unit 220 sends initial signal Start to open communication.The interior integrated circuit is received from unit 120
It can enter after initial signal Start and receive data pattern.Then, the interior integrated circuit master unit 220 sends communication target and sets
Standby address address totally 7 and one reading R information 1.Come again, the interior integrated circuit receives address from unit 120
After address, the interior integrated circuit for meeting address address can send the response Ack an of position from unit 120 and touch
Hair interrupts.After the interior integrated circuit master unit 220 receives response Ack, the instruction generation read to flash cell 300 is then transmitted
Code Cmd.Reading instruction code Cmd is, for example, 0BH, this announcement is without being limited thereto.And the micro-control unit 110 detects interruption
Afterwards, it waits and receives instruction code 0BH.After instruction code transmits, the interior integrated circuit sends a response from unit 120
Ack simultaneously triggers interruption.After the interior integrated circuit master unit 220 receives response Ack, the flash cell 300 is then transmitted
Address details Flash add.After the micro-control unit 110 detects interruption, waits and receive address details Flash add.
After address details transmit, the interior integrated circuit sends a response Ack from unit 120 and triggers interruption.The microcontroller
Unit 110 will read instruction code Cmd and address details Flash add and penetrate 130 pairs of institutes of the Serial Peripheral Interface (SPI) master unit
Serial Peripheral Interface (SPI) is stated to send from unit 330.The flash cell 300 reads data data 0, data 1 etc. in the address
And return, two data instances are only lifted in this announcement, but this announcement is without being limited thereto.
After data data 0, data 1 pass back to the micro-control unit 110, the micro-control unit 110 can control institute
It states interior integrated circuit and issues an initial signal Start from unit 120.The interior integrated circuit master unit 220 receives starting letter
Read mode can be entered after number Start.The interior integrated circuit then issues oneself address address totally 7 from unit 120
Position, one reading R information 1 and response Ack simultaneously trigger interruption.After the micro-control unit 110 detects interruption, just start
Data data 0 is transmitted from unit 120 to the interior integrated circuit master unit 220 through the interior integrated circuit.It is described interior integrated
After circuit master unit 220 receives response Ack, waits and read data data 0.It is described interior after the data for often receiving a byte
Integrated circuit master unit 220 can send a response Ack.After the micro-control unit 110 detects response Ack, through described
Interior integrated circuit transmits next data from unit 120 to the interior integrated circuit master unit 220.After data receiver is complete,
The interior integrated circuit master unit 220 can send unresponsive nAck and stop signal Stop.The micro-control unit 110 is received
To after unresponsive nAck, stop reading data from flash cell 300 immediately.
Referring to Fig.1, this announcement also provides a kind of timing control plate 1000, including sequence controller 100, power management chip
200 and flash cell 300.The sequence controller 100 include micro-control unit 110, interior integrated circuit from unit 120 with
And Serial Peripheral Interface (SPI) master unit 130.The micro-control unit 100 is to execute following effect:
Control the interior integrated circuit main list of integrated circuit out of unit 120 and the power management chip 200 first
Member 220 is communicated；
The Serial Peripheral Interface (SPI) of the Serial Peripheral Interface (SPI) master unit 130 and the flash cell 300 is controlled from unit 330
It is communicated；And
Control data conversion of the interior integrated circuit between unit 120 and the Serial Peripheral Interface (SPI) master unit 130.
The sequence controller 100 further includes a look-up table 140, to map the interior integrated circuit from unit 120
Logical address data to the Serial Peripheral Interface (SPI) master unit 130 physical address data.
In this announcement embodiment therein, the power management chip 200 include the first register cell 20A with
And the second register cell 20B.The flash cell 300 include multiple storage sector 3S1,3S2,3S3 ... 3Sn.The storage
Sector 3S1,3S2,3S3 ... 3Sn have respective physical address.The corresponding storage sector 3S1 of first physical address to
Store the data of the first register cell 20A.The corresponding storage sector 3S3 of second physical address is described to store
The data of second register cell 20B.The corresponding storage sector 3S1 of first physical address with described second physically
The corresponding storage sector 3S3 in location is not adjacent.
Specifically, referring to Fig. 2, in this announcement embodiment therein, data structure such as Fig. 2 of the look-up table 140
It is shown.The data volume of one register cell for example has 42 data.A storage sector is for example in the flash cell
4KB data can be deposited.Then the logical address number of first register cell is, for example, from 0 to 41.Correspond to the flash memory
It is, for example, 01F000h to 01F029h that the physical address of sector 3S1 is stored described in unit.First register cell is patrolled
Collecting address number is, for example, from 42 to 83.Correspond to described in the flash cell store sector 3S3 physical address be, for example,
03F000h to 03F029h.The physical address 01F000h to 01F029hea and the storage sector 3S3 of the storage sector 3S1
Physical address 03F000h to 03F029h it is not adjacent.
Specifically, the corresponding storage sector of first physical address and second physical address can be selected
The corresponding storage sector is adjacent or not adjacent, this announcement is without being limited thereto.The storage sector is not adjacent to increase the sudden strain of a muscle
The flexibility ratio of memory cell storage data.
Specifically, referring to Fig. 3, interior integrated circuit integrated circuit master unit 220 out of unit 120 and described first
On-line mode is as shown, interior integrated circuit unit bus is communicated using serial data line SDA and serial time clock line SCL.
Specifically, referring to Fig. 4, the Serial Peripheral Interface (SPI) master unit 130 and the Serial Peripheral Interface (SPI) are from unit 330
On-line mode is as shown, Serial Peripheral Interface (SPI) unit bus uses four interfaces: serial frequency line SCLK, it is main go out from entering line
MOSI, master enter from outlet MISO and slave selection line SS.
Referring to Fig. 5, in this announcement embodiment therein, if the micro-control unit 110 is interior integrated to judge
Logical address data described in circuit instruction is more than a default value, then is addressed to second physical address, is otherwise addressed to institute
State the first physical address.
Specifically, the judgment step of the micro-control unit 110 includes: step S10: receiving instruction；Step S20: sentence
Severed finger enable in logical address whether less than a register cell data volume；If so, thening follow the steps S30: being addressed to
One physical address；S40 is thened follow the steps if not: being addressed to the second physical address；After executing the step S30 or step S40, hold
Row step S50: reading or write-in data.
Specifically, micro-control unit decision logic address and being addressed to the programming language code of physical address for example:
Wherein offset is offset address, and CodeSize is the size of data of each register cell, and length is read-write
Data length, above numerical value are citing, this announcement is without being limited thereto.
Specifically, the instruction format of interior integrated circuit unit is as shown in the figure referring to Fig. 6.Interior integrated circuit master unit is sent
Initial signal Start communicates to open.All interior integrated circuits can enter after receiving initial signal Start from unit to be received
Data pattern.Then, interior integrated circuit master unit sends the address address of communication target device totally 7 and one readings
Or write R/W information.1 indicates to read, and 0 indicates to write.Come again, after interior integrated circuit receives address address from unit, meets the address
The interior integrated circuit of address can send the response Ack an of position from unit.Interior integrated circuit master unit receives response Ack meeting
The R/W information that reads or writes depending on its script enters reception or output mode.Then in the data of transmission, interior integrated circuit can from unit
To issue a response Ack at the end of the transmission of each byte.Finally, interior integrated circuit master unit issues at the end of transmission
Stop signal Stop.
Specifically, referring to Fig. 6 and Fig. 7, within integrated circuit unit reading instruction format for.As shown,
The interior integrated circuit master unit 220 sends initial signal Start to open communication.The interior integrated circuit is from list
Member 120 can enter reception data pattern after receiving initial signal Start.Then, the interior integrated circuit master unit 220 is sent
Communicate the address address of target device totally 7 and one reading R information 1.Come again, the interior integrated circuit is from unit 120
After receiving address address, the interior integrated circuit for meeting address address can send answering for a position from unit 120
It answers Ack and triggers interruption.After the interior integrated circuit master unit 220 receives response Ack, then transmits and flash cell 300 is read
The instruction code Cmd taken.Reading instruction code Cmd is, for example, 0BH, this announcement is without being limited thereto.And the micro-control unit 110 is detectd
After measuring interruption, waits and receive instruction code 0BH.After instruction code transmits, the interior integrated circuit is sent out from unit 120
It send a response Ack and triggers interruption.After the interior integrated circuit master unit 220 receives response Ack, the flash memory list is then transmitted
The address details Flash add of member 300.After the micro-control unit 110 detects interruption, waits and receive address details
Flash add.After address details transmit, the interior integrated circuit sends a response Ack from unit 120 and triggers interruption.
The micro-control unit 110 will read instruction code Cmd and address details Flash add and penetrate the main list of the Serial Peripheral Interface (SPI)
First 130 pairs of Serial Peripheral Interface (SPI)s are sent from unit 330.The flash cell 300 read data data 0 in the address,
Data 1 etc. are simultaneously returned, and two data instances are only lifted in this announcement, but this announcement is without being limited thereto.
After data data 0, data 1 pass back to the micro-control unit 110, the micro-control unit 110 can control institute
It states interior integrated circuit and issues an initial signal Start from unit 120.The interior integrated circuit master unit 220 receives starting letter
Read mode can be entered after number Start.The interior integrated circuit then issues oneself address address totally 7 from unit 120
Position, one reading R information 1 and response Ack simultaneously trigger interruption.After the micro-control unit 110 detects interruption, just start
Data data 0 is transmitted from unit 120 to the interior integrated circuit master unit 220 through the interior integrated circuit.It is described interior integrated
After circuit master unit 220 receives response Ack, waits and read data data 0.It is described interior after the data for often receiving a byte
Integrated circuit master unit 220 can send a response Ack.After the micro-control unit 110 detects response Ack, through described
Interior integrated circuit transmits next data from unit 120 to the interior integrated circuit master unit 220.After data receiver is complete,
The interior integrated circuit master unit 220 can send unresponsive nAck and stop signal Stop.The micro-control unit 110 is received
To after unresponsive nAck, stop reading data from flash cell 300 immediately.
Although this announcement, those skilled in the art have shown and described relative to one or more implementations
It will be appreciated that equivalent variations and modification based on the reading and understanding to the specification and drawings.This announcement includes all such repairs
Change and modification, and is limited only by the scope of the following claims.In particular, to various functions executed by the above components, use
It is intended to correspond in the term for describing such component and executes the specified function of the component (such as it is functionally of equal value
) random component (unless otherwise instructed), even if in structure with execute the exemplary of this specification shown in this article and realize
The open structure of function in mode is not equivalent.In addition, although the special characteristic of this specification is relative to several realization sides
Only one in formula is disclosed, but this feature can with such as can be for a given or particular application expectation and it is advantageous
One or more other features combinations of other implementations.Moreover, with regard to term " includes ", " having ", " containing " or its deformation
For being used in specific embodiments or claims, such term is intended to wrap in a manner similar to the term " comprising "
It includes.
The above is only the preferred embodiments of this announcement, it is noted that for those of ordinary skill in the art, is not departing from
Under the premise of this announcement principle, several improvements and modifications can also be made, these improvements and modifications also should be regarded as the guarantor of this announcement
Protect range.
Claims (10)
1. a kind of sequence controller, which is characterized in that connect including micro-control unit, interior integrated circuit from unit and serial peripheral
Mouth master unit, the micro-control unit is to execute following effect:
Control the interior integrated circuit from unit and outside first in integrated circuit master unit communicated；
The Serial Peripheral Interface (SPI) master unit is controlled to be communicated with external Serial Peripheral Interface (SPI) from unit；And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit；
Wherein, the sequence controller further includes a look-up table, to map logical address of the interior integrated circuit from unit
Data to the Serial Peripheral Interface (SPI) master unit physical address data.
2. sequence controller as described in claim 1, which is characterized in that integrated circuit master unit is located at power supply in described first
Among managing chip, the power management chip includes the first register cell and the second register cell.
3. sequence controller as claimed in claim 2, which is characterized in that the Serial Peripheral Interface (SPI) is located at flash memory list from unit
Among member, the flash cell includes multiple storage sectors, and the storage sector has respective physical address, wherein first
Data of the corresponding storage sector of physical address to store first register cell, the second physical address are corresponding
Data of the storage sector to store second register cell.
4. sequence controller as claimed in claim 3, which is characterized in that the corresponding storage fan of first physical address
The area storage sector corresponding with second physical address is not adjacent.
5. sequence controller as claimed in claim 3, which is characterized in that if the micro-control unit is to judge interior integrated electricity
Logical address data described in the instruction of road is more than a default value, then is addressed to second physical address, is otherwise addressed to described
First physical address.
6. sequence controller as claimed in claim 3, which is characterized in that the power management chip is to penetrate described first
The interior integrated circuit of interior integrated circuit master unit and the sequence controller is stored in the sudden strain of a muscle from unit communications, to read
The data of first register cell in memory cell and the data of second register cell.
7. sequence controller as claimed in claim 3, which is characterized in that the sequence controller may be electrically connected to external pipe
Module is managed, the management module includes integrated circuit master unit in second, wherein the management module is to penetrate described second
The interior integrated circuit of interior integrated circuit master unit and the sequence controller is stored in from unit communications with being written or reading
The data of first register cell in the flash cell and the data of second register cell.
8. a kind of timing control plate, which is characterized in that described including sequence controller, power management chip and flash cell
Sequence controller includes micro-control unit, interior integrated circuit from unit and Serial Peripheral Interface (SPI) master unit, the microcontroller list
Member is to execute following effect:
Interior integrated circuit integrated circuit master unit out of unit and the power management chip first is controlled to be communicated；
The Serial Peripheral Interface (SPI) for controlling the Serial Peripheral Interface (SPI) master unit and the flash cell is communicated from unit；And
Control data conversion of the interior integrated circuit between unit and the Serial Peripheral Interface (SPI) master unit；
Wherein, the sequence controller further includes a look-up table, to map logical address of the interior integrated circuit from unit
Data to the Serial Peripheral Interface (SPI) master unit physical address data.
9. timing control plate as claimed in claim 8, which is characterized in that the power management chip includes the first register list
Member and the second register cell, the flash cell include multiple storage sectors, and the storage sector has respective physics
Address, wherein data of the corresponding storage sector of the first physical address to store first register cell, second
Data of the corresponding storage sector of physical address to store second register cell, wherein first physics
The corresponding storage sector in the address storage sector corresponding with second physical address is not adjacent.
10. timing control plate as claimed in claim 9, which is characterized in that if the micro-control unit is interior integrated to judge
Logical address data described in circuit instruction is more than a default value, then is addressed to second physical address, is otherwise addressed to institute
State the first physical address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910366280.0A CN110136666A (en) | 2019-05-05 | 2019-05-05 | Sequence controller and timing control panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910366280.0A CN110136666A (en) | 2019-05-05 | 2019-05-05 | Sequence controller and timing control panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110136666A true CN110136666A (en) | 2019-08-16 |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110025699A1 (en) * | 2009-07-28 | 2011-02-03 | Seiko Epson Corporation | Integrated circuit device and electronic apparatus |
| CN102063377A (en) * | 2009-11-16 | 2011-05-18 | 联发科技股份有限公司 | Method of managing data access of a storage medium and storage controller |
| CN103377135A (en) * | 2012-04-25 | 2013-10-30 | 上海海尔集成电路有限公司 | Addressing method, device and system |
| CN105096860A (en) * | 2015-07-31 | 2015-11-25 | 深圳市华星光电技术有限公司 | Communication method, communication device and system of TFTLCD drive circuit |
| CN105761692A (en) * | 2016-05-04 | 2016-07-13 | 深圳市华星光电技术有限公司 | System for online adjusting gamma coding of liquid crystal display panel |
| CN105788551A (en) * | 2016-05-05 | 2016-07-20 | 深圳市华星光电技术有限公司 | Driving system compatible with multiple display modes |
| CN106201901A (en) * | 2014-12-10 | 2016-12-07 | 爱思开海力士有限公司 | Including the controller of mapping table, the storage system including semiconductor storage unit and operational approach thereof |
| CN106713808A (en) * | 2016-11-29 | 2017-05-24 | 西安天圆光电科技有限公司 | Digital image data format conversion circuit and realization method thereof |
| CN107863058A (en) * | 2017-11-22 | 2018-03-30 | 深圳市华星光电技术有限公司 | The control circuit and control method of display panel |
| KR20180062587A (en) * | 2016-11-30 | 2018-06-11 | 엘지디스플레이 주식회사 | Real Time Compensation Circuit And Electroluminescent Display Device Including The Same |
| CN108198536A (en) * | 2017-12-29 | 2018-06-22 | 深圳市华星光电技术有限公司 | Voltage calibration method and calibration system based on sequence controller |
-
2019
- 2019-05-05 CN CN201910366280.0A patent/CN110136666A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110025699A1 (en) * | 2009-07-28 | 2011-02-03 | Seiko Epson Corporation | Integrated circuit device and electronic apparatus |
| CN102063377A (en) * | 2009-11-16 | 2011-05-18 | 联发科技股份有限公司 | Method of managing data access of a storage medium and storage controller |
| CN103377135A (en) * | 2012-04-25 | 2013-10-30 | 上海海尔集成电路有限公司 | Addressing method, device and system |
| CN106201901A (en) * | 2014-12-10 | 2016-12-07 | 爱思开海力士有限公司 | Including the controller of mapping table, the storage system including semiconductor storage unit and operational approach thereof |
| CN105096860A (en) * | 2015-07-31 | 2015-11-25 | 深圳市华星光电技术有限公司 | Communication method, communication device and system of TFTLCD drive circuit |
| CN105761692A (en) * | 2016-05-04 | 2016-07-13 | 深圳市华星光电技术有限公司 | System for online adjusting gamma coding of liquid crystal display panel |
| CN105788551A (en) * | 2016-05-05 | 2016-07-20 | 深圳市华星光电技术有限公司 | Driving system compatible with multiple display modes |
| CN106713808A (en) * | 2016-11-29 | 2017-05-24 | 西安天圆光电科技有限公司 | Digital image data format conversion circuit and realization method thereof |
| KR20180062587A (en) * | 2016-11-30 | 2018-06-11 | 엘지디스플레이 주식회사 | Real Time Compensation Circuit And Electroluminescent Display Device Including The Same |
| CN107863058A (en) * | 2017-11-22 | 2018-03-30 | 深圳市华星光电技术有限公司 | The control circuit and control method of display panel |
| CN108198536A (en) * | 2017-12-29 | 2018-06-22 | 深圳市华星光电技术有限公司 | Voltage calibration method and calibration system based on sequence controller |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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