CN103377135A - Addressing method, device and system - Google Patents
Addressing method, device and system Download PDFInfo
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- CN103377135A CN103377135A CN2012101244377A CN201210124437A CN103377135A CN 103377135 A CN103377135 A CN 103377135A CN 2012101244377 A CN2012101244377 A CN 2012101244377A CN 201210124437 A CN201210124437 A CN 201210124437A CN 103377135 A CN103377135 A CN 103377135A
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Abstract
The invention provides an addressing method, device and system. The addressing method comprises the steps of obtaining an addressing instruction; confirming a selected first physical address subspace according to a first BSR set value; establishing mapping relation of the selected first physical address subspace and a first logic address subspace in a pre-established logic address space; confirming a logic address corresponding to the addressing instruction; confirming a physical address in the selected first physical address subspace corresponding to the logic address according to the mapping relation of the selected first physical address subspace and the first logic address subspace if the logic address is located in the first logic address subspace; confirming a physical address in a second physical address subspace corresponding to the logic address according to mapping relation of the pre-established physical address subspace and a second logic address subspace if the logic address is located in the first logic address subspace of a pre-established physical address space.
Description
Technical field
The present invention relates to addressing technique, relate in particular to a kind of addressing method, Apparatus and system.
Background technology
Microprocessor application is increasingly extensive, to the also constantly increase of demand of data storage space.But because the command bits of microprocessor tolerance system has been limited to the addressing range of addressing instruction to the data storage space.Now, the addressing range of addressing instruction can not cover whole data space, can only the addressing subregion.For instance, data space is 2
10=1024 bytes, address realm 000H～3FFH, the addressing instruction bit wide of microprocessor is 16, comprises 9 bit instruction codes and 7 positional operands, and wherein, 7 positional operands represent the address information of addressing, and addressing range is 2
7=128 bytes.Fig. 1 is the synoptic diagram of 16 bit addressing instructions in the prior art.
Data space is comprised of universal random access memory (General Purpose Random Access Memory is called for short GPR) and specified register (Special Function Register is called for short SFR) usually.GPR and the SFR addressing scheme in data space has two kinds: alternating expression addressing and unified addressing.In the scheme of alternating expression addressing, no matter be directly address or indirect addressing, GPR and SFR are in the distribution mode of " dispersing " all the time.Although the GPR in each data storage area (BANK) is that the address is continuous, there is not continuity in the GPR address among the adjacent BANK.And the discontinuous shortcoming in GPR address will cause microprocessor can't better support the senior program languages such as C language, because high level language need to use Large-scale array and structure, and large-scale array and structure need to take a large amount of continuous GPR.
In the scheme of unified addressing, because the address continuity of GPR, greatly facilitate to the support of Large-scale array, structure with to the support of higher level lanquage, still, when needs carry out data transmission and processing between different B ANK when, need to switch very frequently the BANK operation.During directly address, memory block mask register (Bank Select Register is called for short BSR) need to be set frequently, these operate frequently the instruction that all can greatly reduce microprocessor and carry out efficient.
Summary of the invention
The invention provides a kind of addressing method, Apparatus and system, directly address need frequently arrange the problem of BSR when different B ANK between carrying out data transmission and processing in the unified addressing scheme in order to solve in the prior art.
One aspect of the present invention provides a kind of addressing method, comprising:
Obtain addressing instruction;
Determine the first physical address subspace of selection according to the settings of the first memory block mask register BSR;
The mapping relations of the first logical address subspace in the logical address space of setting up the first physical address subspace of described selection and making up in advance;
Determine the logical address that described addressing instruction is corresponding;
If described logical address is positioned at described the first logical address subspace, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding;
If described logical address is positioned at the second logical address subspace of the described logical address space that makes up in advance, then according to the second physical address subspace of setting up in advance and the mapping relations of described the second logical address subspace, determine the physical address in described the second physical address subspace corresponding to described logical address.
Another aspect of the present invention provides a kind of device for addressing, comprising:
Acquisition module is used for obtaining addressing instruction;
Select module, be used for determining according to the settings of the first memory block mask register BSR the first physical address subspace of selection;
Mapping block is for the mapping relations of logical address space the first logical address subspace of setting up the first physical address subspace of described selection and making up in advance;
Determination module is used for determining logical address corresponding to described addressing instruction;
Addressed module, be positioned at described the first logical address subspace if be used for described logical address, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space that makes up in advance, then according to the second physical address subspace of setting up in advance and the mapping relations of described the second logical address subspace, determine the physical address in described the second physical address subspace corresponding to described logical address.
Another aspect of the present invention provides a kind of addressing system, comprising:
Processor, the first memory block mask register BSR, comprise the first physical address space of at least two the first physical address subspaces and comprise the second physical address space of at least one the second physical address subspace;
Described processor comprises aforesaid device for addressing.
Technique effect of the present invention is: by the logical address space that comprises the first logical address subspace and the second logical address subspace that makes up in advance, when getting access to addressing instruction, the first physical address subspace mapping that BSR is selected is to the first logical address subspace, add in advance the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space of setting up, the logic-based address space is according to addressing instruction addressing the first physical address subspace or the second physical address subspace, solved the problem that directly address when carrying out data transmission and processing in the unified addressing scheme between different B ANK (being different physical address subspaces) in the prior art need frequently arrange BSR, realize that directly address need not frequently to revise the settings of BSR, only just can between the first physical address subspace and the second physical address subspace, switch by revising addressing instruction, improve the instruction of microprocessor and carried out efficient and data transmission efficiency.
Description of drawings
Fig. 1 is the synoptic diagram of 16 bit addressing instructions in the prior art;
Address mapping synoptic diagram when Fig. 2 is the data space directly address of alternating expression addressing;
Address mapping synoptic diagram when Fig. 3 is the data space indirect addressing of alternating expression addressing;
Address mapping synoptic diagram when Fig. 4 is the data space directly address of unified addressing;
The schematic flow sheet of a kind of addressing method that Fig. 5 provides for the embodiment of the invention;
Fig. 6 is the mapping of the address in second physical address subspace situation synoptic diagram in the embodiment of the invention.
The structural representation of a kind of device for addressing that Fig. 7 provides for the embodiment of the invention;
The structural representation of a kind of addressing system that Fig. 8 provides for the embodiment of the invention.
Embodiment
For the embodiment of the invention is carried out clear, detailed introduction, introduce first in the prior art directly address and indirect addressing under two kinds of addressing schemes.
1) alternating expression addressing
The tentation data storage space is 2
10=1024 bytes, address realm 000H～3FFH, wherein the storage space of GPR is 768 bytes, the storage space of SFR is 256 bytes.The addressing instruction bit wide of microprocessor is 16, comprises 9 bit instruction codes and 7 positional operands, and data space is divided into 8 BANK, and each BANK is 128 bytes, and low 32 address assignment in BANK are to SFR, and high 96 address assignment are to GPR.
Address mapping synoptic diagram when Fig. 2 is the data space directly address of alternating expression addressing.As shown in Figure 2, during directly address, select mapped BANK by BSR, addressing instruction can this BANK of addressing.Each BANK is 128 bytes, is just in time covered by the addressing space of an addressing instruction.
Address mapping synoptic diagram when Fig. 3 is the data space indirect addressing of alternating expression addressing.As shown in Figure 3, during indirect addressing, microprocessor is accessed indirect index register and indirect data register among the SFR by the mode of directly address, thereby realizes the function of indirect addressing.Because the bit wide of indirect addressing indexed registers is not subjected to the restriction of addressing instruction bit wide, so indirect addressing can cover whole data space fully.
2) unified addressing
The tentation data storage space is 2
10=1024 bytes, address realm 000H～3FFH, wherein the storage space of GPR is 768 bytes, the storage space of SFR is 256 bytes.The addressing instruction bit wide of supposing microprocessor is 16, comprises 9 bit instruction codes and 7 positional operands, and data space is divided into 8 BANK, and each BANK is 128 bytes, and BANK0～BANK5 distributes to GPR, and BANK6～BANK7 distributes to SFR.
Address mapping synoptic diagram when Fig. 4 is the data space directly address of unified addressing.As shown in Figure 4, during directly address, select mapped BANK by BSR, comprise the BANK that distributes to GPR and the BANK that distributes to SFR, addressing instruction can this BANK of addressing.Each BANK is 128 bytes, is just in time covered by the addressing space of an addressing instruction.
During indirect addressing, similar in address mapping mode and the alternating expression encoding scheme.
Can find out that no matter be that directly address or indirect addressing all are the same, directly address need to arrange BSR frequently, indirect addressing then needs to arrange frequently the high address value of indirect index register.These operate frequently the instruction that all can greatly reduce microprocessor and carry out efficient.
The schematic flow sheet of a kind of addressing method that Fig. 5 provides for the embodiment of the invention.As shown in Figure 5, the method comprises:
501, obtain addressing instruction;
For instance, device for addressing obtains addressing instruction.In the embodiment of the invention, device for addressing is arranged in the processor.Particularly, device for addressing can obtain addressing instruction from the programmed instruction memory block.The bit wide of addressing instruction depends on the instruction storage space of processor.Addressing instruction comprises order code and operand.
502, determine the first physical address subspace of selection according to the settings of a BSR;
The physical address subspace is equivalent to BANK, and the first physical address subspace is that the first physical address space obtains according to certain regular subregion, and the first physical address subspace can be divided at least two the first physical address subspaces.Described the first physical address space can for ROM (read-only memory) (Read-Only Memory is called for short ROM), random access memory (Random Access Memory is called for short RAM) or SFR, particularly, can also be the GPR among the RAM.Correspondingly, the first physical address subspace can be ROM memory block, RAM memory block or SFR memory block, specifically can also be the GPR memory block in the RAM memory block.For instance, the GPR memory block refers to distribute to the data storage area of GPR, and the SFR memory block refers to distribute to the data storage area of SFR.The size of each first physical address subspace is the same.Particularly, the settings of a BSR are set according to programmed instruction by processor.
503, set up the first physical address subspace of described selection and the logical address space that makes up in advance in the mapping relations of the first logical address subspace;
Particularly, also comprised before 501:
Addressing range according to addressing instruction makes up described logical address space, and described logical address space comprises described the first logical address subspace and the second logical address subspace;
With the big or small subregion of the first physical address space according to described the first logical address subspace, form at least two the first physical address subspaces, with the big or small subregion of the second physical address space according to described the second logical address subspace, form at least one second physical address subspace.
Particularly, the addressing range of addressing instruction determines that according to the figure place of operand in the addressing instruction described logical address space can cover the addressing range of addressing instruction, i.e. addressing space.For instance, if the figure place of operand is 8 in the addressing instruction, then logical address space is 2
8=256 bytes, i.e. 00H～FFH.The size of described the first logical address subspace equals the size of the first physical address subspace, and the size of described the second logical address subspace equals the size of the second physical address subspace, and the size of each second physical address subspace is the same.Described the second physical address space can be ROM, RAM or SFR, particularly, can also be the GPR among the RAM.Correspondingly, the second physical address subspace can be ROM memory block, RAM memory block or SFR memory block, particularly, can also be the GPR memory block in the RAM memory block.The second logical address subspace is for setting up mapping relations with the second physical address subspace.The first physical address space can be identical with the second physical address space, also can be different.For instance, during the varying in size of and first logical address subspace and second logical address subspace identical with the second physical address space, the Same Physical address space can form the first physical address subspace and the second physical address subspace of different numbers when the first physical address space.Particularly, the first logical address subspace and the second logical address subspace position in described logical address space also can be pre-set, be positioned at the low level of described logical address space such as the first logical address subspace, the second logical address subspace is positioned at the high position of described logical address space.More preferably, the first logical address subspace is big or small identical with the second logical address subspace, and correspondingly, the size of the first physical address subspace and the second physical address subspace is also identical.
504, determine the logical address that described addressing instruction is corresponding;
In the embodiment of the invention, the logical address that described addressing instruction is corresponding is determined according to operand in the described addressing instruction.For instance, if operand is 36H in the addressing instruction, determine that then corresponding logical address is 36H.
If 505 described logical addresses are positioned at described the first logical address subspace, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space that makes up in advance, then according to the second physical address subspace of setting up in advance and the mapping relations of described the second logical address subspace, determine the physical address in described the second physical address subspace corresponding to described logical address.
For instance, the address realm of logic of propositions address space is 00H～FFH, wherein the address realm of the first logical address subspace is 00H～7FH, the address realm of the second logical address subspace is 80H～FFH, if described logical address is 36H, then be positioned at the first logical address subspace, if described logical address is 96H, then be positioned at the second logical address subspace.Further, if the address realm of the first physical address subspace of selecting is 0080H～00FFH, physical address in the first physical address subspace of the described selection that then logical address 36H is corresponding is 00C6H, if with the second logical address subspace the address realm of the second physical address subspace of mapping relations being arranged is FF80H～FFFFH, the physical address in the second physical address subspace that then logical address 96H is corresponding is FF96H.Namely, if described logical address is positioned at the first logical address subspace, with described logical address with respect to the skew of the start address of the first logical address subspace as the skew of physical address with respect to the start address of the first physical address subspace of described selection; If described logical address is positioned at the second logical address subspace, with described logical address with respect to the skew of the start address of the second logical address subspace as the skew of physical address with respect to the start address of described the second physical address subspace.
After finishing the addressing process, determined physical address by above-mentioned steps 501～505, can also carry out reading of data in position corresponding to this physical address or the operation such as write according to programmed instruction, present embodiment not be done restriction to this.
In an optional embodiment of the present invention, if the second physical address subspace only has one, also comprise after at least one second physical address subspace of described formation:
Set up the mapping relations of described the second logical address subspace and described the second physical address subspace.
That is to say, in the situation of only having second a physical address subspace, can set up in advance the mapping relations between this second physical address subspace and the second logical address subspace, and the mapping relations of this second logical address subspace and this second physical address subspace can remain unchanged.Fig. 6 is the mapping of the address in second physical address subspace situation synoptic diagram in the embodiment of the invention.Wherein, 0000H～07FFH has been assigned to the first physical address space, and FF80H～FFFFH has been assigned to the second physical address space, keeps in addition physical address space; The first physical address space has been divided into 16 the first physical address subspaces, and the second physical address space only comprises second a physical address subspace; The logical address subspace corresponding with the first physical address space is the first logical address subspace in the logical address space, and the logical address subspace corresponding with the second physical address space is the second logical address subspace.
In another alternative embodiment of the present invention, if the second physical address subspace has at least two, then also comprise:
Determine the second physical address subspace of selection according to the settings of the 2nd BSR;
Set up the second physical address subspace of described selection and the mapping relations of described the second logical address subspace;
Accordingly, according to the second physical address subspace of setting up in advance and the mapping relations of described the second logical address subspace, determine that the physical address in described the second physical address subspace corresponding to described logical address specifically comprises in 505:
According to the second physical address subspace of described selection and the mapping relations of described the second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
That is to say, the 2nd BSR is set again, be used for from a plurality of the second physical address subspaces selecting one, with the second physical address subspace mapping of selecting to the second logical address subspace.In this case, the mapping object of the second logical address subspace may change.With a BSR similarly, the settings of the 2nd BSR also can be set according to programmed instruction by processor.
Switch frequently the BANK operation when carrying out data transmission and processing in order further to reduce between the different memory areas, can also be with described logical address space expansion, to comprise that more logical address subspace is to be mapped to different physical address subspaces.Particularly, described logical address space also comprises the 3rd logical address subspace, also comprises before 501:
With the big or small subregion of the 3rd physical address space according to described the 3rd logical address subspace, form at least two the 3rd physical address subspaces;
Also comprise after 501:
Determine the 3rd physical address subspace of selection according to the settings of the 3rd BSR;
Set up the 3rd physical address subspace of described selection and the mapping relations of described the 3rd logical address subspace;
Accordingly, also comprise after 504:
If described logical address is positioned at described the 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in described the 3rd physical address subspace corresponding to described logical address.
Wherein, the size of the 3rd physical address subspace and the 3rd logical address subspace is big or small identical.Described the 3rd physical address space can be ROM, RAM or SFR, can also be the GPR among the RAM.Correspondingly, described the 3rd physical address subspace also can be SFR memory block, ROM memory block or RAM memory block, can also be the GP memory block R in the RAM memory block.The 3rd physical address space with the first physical address space, the second physical address space can be identical, and is or different.Described the first physical address subspace, the second physical address subspace, the 3rd physical address subspace can be same memory blocks, also can be different memory blocks.In addition, similar with the second physical address subspace, when the 3rd physical address subspace only has one, need not to arrange the 3rd BSR, can before 501, set up in advance the mapping relations of this 3rd physical address subspace and the 3rd logical address subspace.
Particularly, when logical address space also comprises the 3rd logical address subspace, can design addressing instruction and have larger addressing range, namely increase the figure place of operand.For instance, when the figure place of operand was 8, the addressing range of addressing instruction was 2
8=256 bytes, the size of the first/two logical address subspace is 2
7=128 bytes, when having increased size when also being the 3rd logical address subspace of 128 bytes, figure place that can the design operation number is 9, namely the addressing range of addressing instruction is 2
9=512 bytes can cover three logical address subspaces, even 4 logical address subspaces.If the addressing range of addressing instruction is constant, also the address realm of each logical address subspace can be reduced, correspondingly reduce the size of BANK.For instance, when the figure place of operand was 8, the addressing range of addressing instruction was 2
8=256 bytes, the size of the first/two logical address subspace is 2
7=128 bytes when needs increase by the 3rd logical address subspace, can all be designed to 2 with the size of 3 logical address subspaces
6=64 bytes, correspondingly the size design with each BANK is 64 bytes.If the address realm of the addressing range of addressing instruction and each logical address subspace is all constant, also can be by the addressing range of software change in logical address space.For instance, addressing range in the logical address space is initially the first logical address subspace and the second logical address subspace, after having finished an addressing by the first logical address subspace, addressing range in the logical address space can be set in the second logical address subspace and the 3rd logical address subspace, after having finished an addressing by the 3rd logical address subspace, can again the addressing range in the logical address space be set in the first logical address subspace and the second logical address subspace.
Need to prove that when logical address space also comprised the more logical address subspace such as the 4th logical address subspace, the 5th logical address subspace, addressing method also was similar with said process.In addition, also can determine according to the figure place of the operand of addressing instruction the size of logical address space, then according to different physical address spaces logical address space is divided into and each physical address space a plurality of logical address subspace one to one, and is the physical address subspace according to each physical address space subregion of large young pathbreaker of the logical address subspace of correspondence.
Need to prove that the embodiment of the invention mainly is the improvement to directly address.During indirect addressing, processor is accessed indirect index register and indirect data register among the SFR by the mode of directly address, thereby realizes the function of indirect addressing.Because the bit wide of indirect addressing indexed registers is not subjected to the restriction of addressing instruction bit wide, so indirect addressing can cover whole data space, i.e. all physical address spaces fully.
The logical address space that comprise first logical address subspace and second logical address subspace of the embodiment of the invention by making up in advance, when getting access to addressing instruction, the first physical address subspace mapping that BSR is selected is to the first logical address subspace, add in advance the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space of setting up, the logic-based address space is according to addressing instruction addressing the first physical address subspace or the second physical address subspace, solved the problem that directly address when carrying out data transmission and processing in the unified addressing scheme between different B ANK (being different physical address subspaces) in the prior art need frequently arrange BSR, realize that directly address need not frequently to revise the settings of BSR, only just can between the first physical address subspace and the second physical address subspace, switch by revising addressing instruction, improve the instruction of microprocessor and carried out efficient and data transmission efficiency.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can be finished by the relevant hardware of programmed instruction.Aforesaid program can be stored in the computer read/write memory medium.This program is carried out the step that comprises above-mentioned each embodiment of the method when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
The structural representation of a kind of device for addressing that Fig. 7 provides for the embodiment of the invention.As shown in Figure 7, this device comprises:
Acquisition module 71 is used for obtaining addressing instruction;
Select module 72, be used for determining according to the settings of a BSR the first physical address subspace of selection;
Mapping block 73 is for the mapping relations of logical address space the first logical address subspace of setting up the first physical address subspace of described selection and making up in advance;
Determination module 74 is used for determining logical address corresponding to described addressing instruction;
Addressed module 75, be positioned at described the first logical address subspace if be used for described logical address, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space that makes up in advance, then according to the second physical address subspace of setting up in advance and the mapping relations of described the second logical address subspace, determine the physical address in described the second physical address subspace corresponding to described logical address.
In an optional embodiment of the present invention, this device also comprises:
Make up module, be used for before acquisition module 71 obtains addressing instruction, comprise the logical address space of described the first logical address subspace and the second logical address subspace according to the addressing range structure of addressing instruction; With the big or small subregion of the first storage space according to described the first logical address subspace, form at least two the first physical address subspaces, with the big or small subregion of the second storage space according to described the second logical address subspace, form at least one second physical address subspace.Wherein, the size of described the first logical address subspace equals the size of the first physical address subspace, and the size of described the second logical address subspace equals the size of the second physical address subspace.
In another alternative embodiment of the present invention, if the second physical address subspace only has one, mapping block 73 also is used for,
After described structure module forms at least one second physical address subspace, set up the mapping relations of described the second logical address subspace and described the second physical address subspace.
In another alternative embodiment of the present invention, if the second physical address subspace has at least two, select module 72 also to be used for, determine the second physical address subspace of selecting according to the settings of the 2nd BSR;
Mapping block 73 also is used for, and sets up the second physical address subspace of described selection and the mapping relations of described the second logical address subspace;
Addressed module 75 specifically is used for,
If described logical address is positioned at the second logical address subspace of described logical address space, then according to the second physical address subspace of described selection and the mapping relations of described the second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
In another alternative embodiment of the present invention, described logical address space also comprises the 3rd logical address subspace, the size of described the 3rd logical address subspace equals the size of the 3rd physical address subspace, described structure module also was used for before acquisition module 71 obtains addressing instruction, with the big or small subregion of the 3rd storage space according to described the 3rd logical address subspace, form at least two the 3rd physical address subspaces;
Select module 72 also to be used for, determine the 3rd physical address subspace of selecting according to the settings of the 3rd BSR;
Mapping block 73 also is used for, and sets up the 3rd physical address subspace of described selection and the mapping relations of described the 3rd logical address subspace;
Addressed module 75 also is used for, if described logical address is positioned at described the 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in the 3rd physical address subspace of the described selection that described logical address is corresponding.
Described the first physical address subspace, the second physical address subspace, the 3rd physical address subspace can be respectively SFR memory block, ROM memory block or RAM memory block.More preferably, design the big or small identical of each logical address subspace, correspondingly, the size of each physical address subspace is also identical.
A kind of addressing method that the specific implementation of present embodiment provides with reference to the embodiment of the invention.The logical address space that comprise first logical address subspace and second logical address subspace of the embodiment of the invention by making up in advance, when getting access to addressing instruction, the first physical address subspace mapping that BSR is selected is to the first logical address subspace, add in advance the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space of setting up, the logic-based address space is according to addressing instruction addressing the 3rd physical address subspace or the second physical address subspace, solved the problem that directly address when carrying out data transmission and processing in the unified addressing scheme between different B ANK (being different physical address subspaces) in the prior art need frequently arrange BSR, realize that directly address need not frequently to revise the settings of BSR, only just can between the first physical address subspace and the second physical address subspace, switch by revising addressing instruction, improve the instruction of microprocessor and carried out efficient and data transmission efficiency.
The structural representation of a kind of addressing system that Fig. 8 provides for the embodiment of the invention.As shown in Figure 8, this system comprises: processor 81, a BSR82, comprise the first physical address space 83 of at least two the first physical address subspaces 831 and comprise the second physical address space 84 of at least one the second physical address subspace 841;
If it is a plurality of that the second physical address subspace 841 has, this system can further include the 2nd BSR.
Further, if logical address space is except the first logical address subspace and the second logical address subspace, also comprise the 3rd logical address subspace, then this system can also correspondingly comprise three physical address space corresponding with the 3rd logical address subspace, when the 3rd physical address space obtains at least two the 3rd physical address subspaces according to the big or small subregion of the 3rd logical address subspace, also comprise for the 3rd BSR that selects from least two the 3rd physical address subspaces.
Above-mentioned the first physical address space, the second physical address space, the 3rd physical address space can be respectively SFR, ROM or RAM.
In the application, processor 81, a BSR82, logical address space can realize in singlechip chip that the first physical address space, the second physical address space, the 3rd physical address space can be respectively on-chip memories, or chip external memory.
A kind of addressing method and device for addressing that the specific implementation of present embodiment provides with reference to the embodiment of the invention.The logical address space that comprise first logical address subspace and second logical address subspace of the embodiment of the invention by making up in advance, when getting access to addressing instruction, the first physical address subspace mapping that BSR is selected is to the first logical address subspace, add in advance the mapping relations of the second logical address subspace and the second physical address subspace in the logical address space of setting up, the logic-based address space is according to addressing instruction addressing the first physical address subspace or the second physical address subspace, solved the problem that directly address when carrying out data transmission and processing in the unified addressing scheme between different B ANK (being different physical address subspaces) in the prior art need frequently arrange BSR, realize that directly address need not frequently to revise the settings of BSR, only just can between the first physical address subspace and the second physical address subspace, switch by revising addressing instruction, improve the instruction of microprocessor and carried out efficient and data transmission efficiency.
It should be noted that at last: above each embodiment is not intended to limit only in order to technical scheme of the present invention to be described; Although with reference to aforementioned each embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps some or all of technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the scope of various embodiments of the present invention technical scheme.
Claims (12)
1. an addressing method is characterized in that, comprising:
Obtain addressing instruction;
Determine the first physical address subspace of selection according to the settings of the first memory block mask register BSR;
The mapping relations of the first logical address subspace in the logical address space of setting up the first physical address subspace of described selection and making up in advance;
Determine the logical address that described addressing instruction is corresponding;
If described logical address is positioned at described the first logical address subspace, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding;
If described logical address is positioned at the second logical address subspace of the described logical address space that makes up in advance, then according to the second physical address subspace of setting up in advance and the mapping relations of described the second logical address subspace, determine the physical address in described the second physical address subspace corresponding to described logical address.
2. method according to claim 1 is characterized in that, the described addressing instruction that obtains also comprises before:
Addressing range according to addressing instruction makes up the described logical address space that comprises the described logical address space in described the first logical address subspace and the second logical address subspace;
With the big or small subregion of the first physical address space according to described the first logical address subspace, form at least two the first physical address subspaces, with the big or small subregion of the second physical address space according to described the second logical address subspace, form at least one second physical address subspace.
3. method according to claim 2 is characterized in that, if the second physical address subspace only has one, also comprises after at least one second physical address subspace of described formation:
Set up the mapping relations of described the second logical address subspace and described the second physical address subspace.
4. method according to claim 2 is characterized in that, if the second physical address subspace has at least two, then described method also comprises:
Determine the second physical address subspace of selection according to the settings of the 2nd BSR;
Set up the second physical address subspace of described selection and the mapping relations of described the second logical address subspace;
The second physical address subspace that described basis is set up in advance and the mapping relations of described the second logical address subspace, determine that the physical address in described the second physical address subspace corresponding to described logical address specifically comprises:
According to the second physical address subspace of described selection and the mapping relations of described the second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
5. each described method is characterized in that according to claim 2-4, and described logical address space also comprises the 3rd logical address subspace, and the described addressing instruction that obtains also comprises before:
With the big or small subregion of the 3rd physical address space according to described the 3rd logical address subspace, form at least two the 3rd physical address subspaces;
The described addressing instruction that obtains also comprises afterwards:
Determine the 3rd physical address subspace of selection according to the settings of the 3rd BSR;
Set up the 3rd physical address subspace of described selection and the mapping relations of described the 3rd logical address subspace;
Logical address corresponding to described definite described addressing instruction also comprises afterwards:
If described logical address is positioned at described the 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in the 3rd physical address subspace of the described selection that described logical address is corresponding.
6. a device for addressing is characterized in that, comprising:
Acquisition module is used for obtaining addressing instruction;
Select module, be used for determining according to the settings of the first memory block mask register BSR the first physical address subspace of selection;
Mapping block is for the mapping relations of logical address space the first logical address subspace of setting up the first physical address subspace of described selection and making up in advance;
Determination module is for the logical address of determining the described logical address space that described addressing instruction is corresponding;
Addressed module, be positioned at described the first logical address subspace if be used for described logical address, then according to the first physical address subspace of described selection and the mapping relations of the first logical address subspace, determine the physical address in the first physical address subspace of the described selection that described logical address is corresponding; If described logical address is positioned at the second logical address subspace of the described logical address space that makes up in advance, then according to the second physical address subspace of setting up in advance and the mapping relations of described the second logical address subspace, determine the physical address in described the second physical address subspace corresponding to described logical address.
7. device according to claim 6 is characterized in that, also comprises:
Make up module, be used for before described acquisition module obtains addressing instruction, comprise the logical address space of described the first logical address subspace and the second logical address subspace according to the addressing range structure of addressing instruction; With the big or small subregion of the first storage space according to described the first logical address subspace, form at least two the first physical address subspaces, with the big or small subregion of the second storage space according to described the second logical address subspace, form at least one second physical address subspace.
8. device according to claim 7 is characterized in that, if the second physical address subspace only has one, described mapping block also is used for,
After described structure module construction forms at least one second physical address subspace, set up the mapping relations of described the second logical address subspace and described the second physical address subspace.
9. device according to claim 7 is characterized in that, if the second physical address subspace has at least two, described selection module also is used for, and determines the second physical address subspace of selecting according to the settings of the 2nd BSR;
Described mapping block also is used for, and sets up the second physical address subspace of described selection and the mapping relations of described the second logical address subspace;
Described addressed module specifically is used for,
If described logical address is positioned at the second logical address subspace of described logical address space, then according to the second physical address subspace of described selection and the mapping relations of described the second logical address subspace, determine the physical address in the second physical address subspace of the described selection that described logical address is corresponding.
10. each described device according to claim 7-9, it is characterized in that, described logical address space also comprises the 3rd logical address subspace, described structure module also was used for before described acquisition module obtains addressing instruction, with the big or small subregion of the 3rd storage space according to described the 3rd logical address subspace, form at least two the 3rd physical address subspaces;
Described selection module also is used for, and determines the 3rd physical address subspace of selecting according to the settings of the 3rd BSR;
Described mapping block also is used for, and sets up the 3rd physical address subspace of described selection and the mapping relations of described the 3rd logical address subspace;
Described addressed module also is used for, if described new logical address is positioned at described the 3rd logical address subspace, then according to the 3rd physical address subspace of described selection and the mapping relations of the 3rd logical address subspace, determine the physical address in the 3rd physical address subspace of the described selection that described new logical address is corresponding.
11. addressing system, it is characterized in that, comprising: processor, the first memory block mask register BSR, comprise the first physical address space of at least two the first physical address subspaces and comprise the second physical address space of at least one the second physical address subspace;
Described processor comprises such as each described device for addressing among the claim 6-10.
12. system according to claim 11 is characterized in that, described the first physical address space, the second physical address space are read only memory ROM, random access memory ram or specified register SFR.
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