CN102314396B - Method and device for accessing bytes by taking a block as base flash - Google Patents
Method and device for accessing bytes by taking a block as base flash Download PDFInfo
- Publication number
- CN102314396B CN102314396B CN201010224441.1A CN201010224441A CN102314396B CN 102314396 B CN102314396 B CN 102314396B CN 201010224441 A CN201010224441 A CN 201010224441A CN 102314396 B CN102314396 B CN 102314396B
- Authority
- CN
- China
- Prior art keywords
- data
- data structure
- field
- state
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a method and device for accessing bytes by taking a block as a base flash. In the technology, the requirement that data bytes stored in a flash memory every time need to be updated after a sector erasure operation can be avoided by using a one-erasing and multiple-programming progressive index structure to manage data in the flash memory. A data structure stored in an addressable sector of an array comprises index data, state data and bytes of the data so that a logic address is mapped to the sector, and one-erasing and multiple-programming program management can be used. The result is as follows: a great deal of write-in operation can be carried out at a given sector before one sector erasing operation. Therefore, flash can be used for accessing bytes at high speed.
Description
Technical field
The invention relates to flash memory technology, particularly about the high speed of flash memory devices, random-access data management technique.
Background technology
Electrically programmable erasable read-only memory (EEPROM) and flash memory comprise the storage unit between passage and field-effect transistor grid by charge storage.Stored electric charge can affect transistorized threshold voltage, and threshold voltage can change and can be used for sensing designation data according to stored electric charge.Wherein a kind of very habitual charge storage memory cells is called as a floating gate memory cell.In a floating gate memory cell, it can store charge in the conductive material layer between passage and grid.Another kind of charge storage memory cells kenel is called as a charge capturing storage unit, and it can replace floating grid with a dielectric layer.
Noun as used herein " write " refer to the operation that changes transistor threshold voltage, and be the operation that increases and reduce transistor threshold voltage for comprising.In electrically programmable erasable read-only memory (EEPROM) and flash device, first write operation involves an erase step, all storage unit in one storage compartments are set to erase status, carry out afterwards a programming step, storage unit selected in this storage compartments is set to programming state again.Noun as used herein " programming " refer to and in a flash memory, utilize the byte operation that then mode of a byte is carried out, noun as used herein " wipe " refer to the relation due to flash memory cell configuration, the operation of normally carrying out with section or the mode of block.Therefore,, in flash memory, for the single byte of programming, a larger section in this storage array must be first wiped in write operation, and is whole section storage data again again.
The mode that storage unit in electrically programmable erasable read-only memory (EEPROM) device can utilize a byte to follow a byte is wiped and is irrelevant with other data byte.Yet in order to want the then erase mode of a byte of activation one byte, the storage density of this electrically programmable erasable read-only memory (EEPROM) is relatively low.
Electrically programmable erasable read-only memory (EEPROM) and flash memory devices are normally as different application.Generally speaking, because its higher density, flash memory is more economical compared with electrically programmable erasable read-only memory (EEPROM) in mass data storing application aspect.And electrically programmable erasable read-only memory (EEPROM) is that then the reading and writing data of a byte is more suitable carrying out a byte to small amount of data, such as being that storing state data or configuration data etc. need to change or similar data etc. frequently.
In many electronic installations, include electrically programmable erasable read-only memory (EEPROM) and flash memory, to meet the difference storage need for exhibition of difference in functionality in this device simultaneously.Yet, use the storer of these two kinds of kenels to increase cost and the complexity of this device simultaneously.
It is exactly that it has limited permanance that flash memory can produce a specific problem, and the number that the storage unit in this device can maintain wiping of its operability and reliability and/or program cycles is limited.Therefore, repeat and write constantly single section, or the section of minority, can cause some section to become aging and defectiveness after the relatively short time.
Different " mean consumption " technology is suggested to extend the life-span of flash memory.A kind of mean consumption scheme is to use to record the number of times that each section is wiped free of.Then this counter is used to adjust data and is mapped in other section, with its consumption of balance.Can consult United States Patent (USP) the 6th, 000,006,5,485,595 and 5,341, No. 339 patents.
Although usage counter can extend the life-span of flash memory devices, yet limited read/write endurance issues still can limit flash memory in the application of the more number of times programming of needs and erase operation.
Another kind of mean consumption scheme is that new data is more write to the provider location that not have in flash memory devices used, rather than again covers the Data Position of script.Section erase operation number in the time of so can reducing the given write operation in flash memory devices.Can consult United States Patent (USP) the 5th, 845,313 and 6,115, No. 785 patents.
For the physical location change of trace data, can use programmable mapping table or address translation table.Programmable mapping table stores by the map information between the indicated logical address of an external system and the flash memory devices physical address that comprises valid data.In order correctly to follow the trail of the physical location of valid data, this programmable mapping table must be updated when operation.
In order to ensure valid data, be held, this map information must be held when interrupting power supply.Yet, because of programmable image address translation tables for this reason, upgraded constantly, store this map information and can reduce the life-span of this device in flash memory.Because the erasing speed that flash memory is relatively slow, so can seriously affect the performance of the device that uses flash memory.This programmable image address translation tables perhaps can alternatively be stored in another non-volatile memory circuits in this device.Yet, also can increase cost and the complexity of this device.
Therefore need to provide a kind of flash memory devices its go for need to be as the Performance Characteristics of the high speed byte access of electrically programmable erasable read-only memory (EEPROM), and also can utilize lower cost and complexity and solve endurance issues simultaneously.
Summary of the invention
The present invention is the method that discloses a kind of operation one flash memory, and it is applicable to high speed bytes store.A plurality of sections that the method comprises the data storage cell in this flash memory of arrangement with sector address are to store data structure separately, wherein a data structure is arranged to the byte (or data group of other N bit wide) of storage data, it is by logical address institute identification, and comprises an index field and a data field position.By wiping this index field and this data structure of initialization is carried out in this data field position.The logical address reflection of the byte of these data is to the sector address of the section of storage one data structure with these data.The byte that writes these data has a logical address and particular section matching addresses, a particular section address in this data field position of this this data structure of programming, wherein this data storage cell line segment wide with a specified byte in this data field position is corresponding, and in this data structure of programming corresponding byte wide line segment to store the byte of these data.In order to respond a logical address to read the byte of these data, the index field in this data structure is used for distinguishing the wide line segment of this specified byte that stores available data.This available data is provided and responds a read operation.
In one embodiment, this data structure comprises that an index field comprises a localizer field and has a storage unit storage M position (for example 28), in section, there is sequence of addresses, and comprise a data field position, the line segment that it comprises the M byte wide (for example 28 bytes) of sequentially arranging.Each of this sequence of addresses M position can be corresponding with of M byte wide line segment in identical address order.In this localizer field, last of M position has been programmed and corresponded to of this M byte wide line segment of most recently used in data field position.
In a described embodiment, provide an index field to comprise a localizer field and store M position according to sequence of addresses, and this data field position comprises the M byte wide line segment of arranging according to sequence of addresses herein.When each data storage cell stores a single position, localizer field comprises M data storage cell.In localizer field, store when a primary data storage cell is programmed and remaining data storage cell still keeps wiping in this localizer field, this localizer field is pointed to the one of the sequence of addresses of this byte wide line segment, when this stores this first and when a deputy storage unit is programmed and remaining data storage cell still keeps wiping in this localizer field, this localizer field point to this byte wide line segment sequence of addresses the two, and when all these M positions in this localizer field are all programmed, this localizer field is pointed to the last one of the sequence of addresses of this byte wide line segment.
In a described embodiment, this data structure provides an index field herein, the state position that it comprises this data structure, and after initialization, all storage unit in index field are at erase status.This state position comprises at least K-1 position arranges according to sequence of addresses, and when this data structure of initialization, indicates K current one of carrying out state.According to an example described herein, an original state wherein in this state position all K-1 positions be all wiped free of.At one first state, be programmed and when remaining data storage cell of this state position is wiped free of for the primary data storage cell when this state position of storage, at one second state for when storing that this first and one deputy one or more data storage cell of this state position is programmed and remaining data storage cell of this state position is wiped free of, and at a final state, be this state position all these K-1 be all programmed.
To the use in a data handling system, address translation table can store the logical address that the data byte of the storage unit of section in this flash memory is videoed.A plurality of data structure described herein can be initialised in section separately in storage unit, and is videoed to corresponding logical address according to address translation tables.State position in index field is used for the state of management data structures to maintain the correct of address translation table.
In the situation that all byte wide line segments in a specific data structure are all used, current byte in data structure can be copied to a new data structure, and this address translation tables can be used for upgrading that old data structure is videoed to new data structure.Management is copied to a program in new data structure by current byte and comprises this state position of renewal.For example, state position can comprise 4 positions, and can be used for representing 5 states.The original state of being indicated by state position is to represent that this data structure is initialised and does not have logical address to be mapped to this data structure.First state of being indicated by state position is to represent that the new data structure that logical address is videoed is selected and is applicable to for replacing old data structure.Second state of being indicated by state position is to represent that from source data structure (or other data structure), writing current data byte to new data structure completes.The third state of being indicated by state position is to represent that the program of wiping has started to reinitialize old data structure.The 4th state of being indicated by state position is to represent that a program of wiping old data structure completes, and reflection is effective to new data structure.
The routine package that one flash memory can be wiped in block border is containing distributing first and second block, and each block comprises L section, in L logical address of this flash memory.In this program, in this data structure of particular section initialization, comprise of this first and second block who wipes this L section that comprises this particular section, and for example, when position, M N bit data territory experiences write operation in this data structure in this first block (this data structure is full), data stored in the data structure of the section of this first block are moved to the data structure in this second block.
In addition, the present invention also discloses a kind of flash memory, a plurality of sections that comprise the data storage cell with sector address, have logic with according to said method storage data structure to carry out reading and write operation of byte mode in this flash memory.This device also comprises a data processor, it is integrated on identical chip with this flash memory, or can this flash memory of access in a computer system, and comprise the instruction that can be carried out by this data processor, comprise the instruction of the said method that can carry out described herein in a flash memory.These can be by the performed instruction of this data processor, can be stored in this flash memory or other can be by this data processor institute access part.
The present invention also discloses a kind of machine-readable data storage device, comprise a machine-readable data storing media, the instruction that storage can be carried out by processor, this processor has the function of access one storage array, a plurality of sections that this storage array comprises the data storage cell with sector address.This instruction comprises the logic of carrying out said method.
Technology described herein adds that to the operation of byte wide reference value is to help understanding.This program can for example, from writing a byte (8) sometimes, sometimes writes any N bit wide data group (for example 16 or 32) and produce, and has and understanding prior art and suitably adjusting the big or small situation of the data field position of this data structure.
In addition noun as used herein, " section " or " block " refer to one group or array data storage unit.These nouns are not must be strictly corresponding with the actual section of flash memory for limiting one group or array data storage unit, although herein in described program will " section " or " block " can there is its advantage with the actual section of flash memory is corresponding.
Utilization described herein is wiped one-time programming progressive index structure repeatedly and is managed the data in flash memory devices, can avoid the data byte being stored in flash memory devices being carried out to the demand that section erase operation just must upgrade afterwards at every turn.Be stored in byte that data structure in the addressable section of this array comprises index data, status data and these data for the logical address so far section of videoing, it can use wipes one-time programming program management repeatedly.Consequently, can before need to carrying out a section erase operation, a given section carry out the write operation of larger amt.So flash memory can be used as the use of high speed byte access.
Object of the present invention, feature, and embodiment, graphic being described of can arranging in pairs or groups in the chapters and sections of following embodiment.
Accompanying drawing explanation
The present invention is defined by claim scope.These and other objects, feature, and embodiment, graphic being described of can arranging in pairs or groups in the chapters and sections of following embodiment, wherein:
Figure 1A shows the concise and to the point block schematic diagram of a computer system, and it is applicable to use the use of data placement of the flash memory devices of technology described herein.
Figure 1B shows the block of the stored data structure of flash memory or the data placement of section that high speed byte access is used.
Fig. 2 is shown in the data array in an example block, and it comprises a plurality of sections.
Fig. 3 shows the reflection example of a logical address, and it is in the logical address of 128 bytes and flash memory devices physical address space, to have the mapping of a block of 128 sections.
Fig. 4 is shown in the data array in the data structure of a section of an example data storage unit.
The schematic diagram of translating between Fig. 5 display entity address space and logical address space.
Fig. 6 is the process flow diagram of a write operation according to an embodiment of the invention, and it is to store one to upgrade data byte to specific logic address.
Fig. 7 is shown in when operation example that is wiped free of data storage cell of programming in this index field.
Fig. 8 is the process flow diagram of a read operation according to an embodiment of the invention, and it is the data that read specific logic address.
Fig. 9 is the process flow diagram of an editing operation according to an embodiment of the invention.
Figure 10 is the process flow diagram of a conversion operations 1000 according to an embodiment of the invention, and it is to change and be stored in the data in status indicator field when the editing operation of Fig. 9.
Figure 11 shows according to the interclass graph of a relation of different software in one embodiment of the invention flash memory devices.
Figure 12 shows according to the present invention the interclass graph of a relation of different software in one second embodiment flash memory devices.
[main element symbol description]
100: computer system
112: bus subsystem
114: processor
116: network interface
118: telecommunication network
120: flash memory devices
122: User's Interface input media
125: block
128: section
130: User's Interface output unit
200: primary data region
210: write records area
230: write record data
300: logical address space
310: physical address space
520: address translation table
1110: low order quick flashing application programming interfaces
1120: intelligent quick flashing application programming interfaces
1130: user's program code
1200: byte read-write mode region
1210: flash memory devices access mode region
Embodiment
The following Fig. 1 of embodiment of the present invention collocation is described in detail to Figure 12.
Figure 1A shows the concise and to the point block schematic diagram of a computer system 100, it is applicable to use the use that comprises storage subsystem 120 data placements that block is basic flash memory devices of technology described herein, and it is for example the use of the flash memory devices data placement that serial peripheral interface (SPI) is compatible that this flash memory devices can be.Computer system 100 comprises at least one processor 114 conventionally, and it sees through bus subsystem 112 and links up with many peripheral units.These peripheral units can comprise extra flash memory devices (not shown), User's Interface input media 122, User's Interface output unit 130 and a network interface subsystem 116.These input-output devices can allow user and computer system 100 interactions.Network interface subsystem 116 is as the interface offering with external network, comprise an interface with telecommunication network 118, and the corresponding interface device seeing through in telecommunication network 118 and other computer system couples.Telecommunication network 118 can comprise computer system and the communication connection of many interconnection.These communication connections can be the mechanism of wired connection, optical fiber connection, wireless connections or out of Memory transmission.The telecommunication network 118 of one of them embodiment is the Internets, but telecommunication network 118 can be any applicable computer network in other embodiments.
User's Interface input media 122 can comprise keyboard, indicator device is for example mouse, and trajectory track device, Trackpad or figure flat board, scanner, Touch Screen, acoustic control input media are for example input medias of voice recognition system, microphone or other kenel etc.Generally speaking, use this noun " input media " be that representative wishes that comprising may be used to input message enters computer system 100 or device kenel or the mode of telecommunication network 118.
User's Interface output unit 130 can comprise that demonstration subsystem, printer, facsimile recorder or non-vision display case are as voice output etc.This shows that subsystem can comprise for example liquid crystal display of iconoscope (CRT), flat display apparatus, a projection arrangement, and other produces the mechanism of vision imaging etc.This demonstration subsystem also can comprise provides non-vision display case as voice output.Generally speaking, use this noun " output unit " be that representative is wished to comprise may be used to from computer system 100 or device kenel or the mode of other machine output information.
This storage subsystem 120 can comprise machine-readable data storage device, comprise the stored instruction of machine-readable data storing media that storage can processor be carried out, this processes utensil has access to comprise the ability of the storage array of a plurality of data segments storage unit, and wherein these instructions comprise the logic that can carry out program described herein.
In illustrative embodiment, processor 114 is carried out instruction to carry out the many operations that comprise outside flash memory devices described herein.Alternatively, this flash memory devices comprises that a processor or the controller of other kenel are to control data management and to carry out many operations described herein.For example, this controller can be the state machine that uses the known special function logic circuit of industry to form.In alternative embodiment, this controller comprises general object processor, and it can be applied on same integrated circuit, to carry out the computer program of this flash memory devices 120 of a control.And in another embodiment, the combination of general object processor and special function logic circuit can be used for implementing this controller.
As shown in Figure 1B, a flash memory can have a plurality of physical blocks, and it comprises block 0125-0 to block K 125-K, to store the data of utilizing above-mentioned Technical arrangements.Block 0125-0 to each block in block K 125-K can independent wiping in other block.The size of this block and number can be depending on the differences of embodiment and are changed.For example, in certain embodiments, the size of each block can be 2KB, 4KB, 8KB or 16KB.Alternatively also can use other block size.
As described above, this flash memory also can comprise that extra block is to store the instruction that logical and physical address is videoed and translated, and as the above-mentioned instruction in block 0125-0 to block K 125-K by data allocations.
Instruction comprises from the logical address of the specified flash memory devices 120 of computer system 100 and flash memory devices 120 block 0125-0 to the reflection between the physical address of block K 125-K.
To block K 125-K, each comprises one or more sections to block 0125-0.For example, the block of a 4KB can comprise the section of 128 32 bytes.Each in these 128 sections can comprise the data structure that stores a byte data.128 logical addresses, 128 sections in block so far of can videoing.As described below, sector address is videoed to the specific logic address of data byte, and is applicable to store the data structure as byte access.
The data structure of describing herein in a given section of the data storage cell in example comprises an index field and a data field position.This index field comprises the so far wide line segment of a specified byte in data field position of a localizer, and this data field position is the logical address of videoing for storing this data byte.In an embodiment, the status indicator field that one of section index field also comprises storage data is to indicate the state of this section.Herein in described example, section state maintains in the border of block, and the state of section in indication block, for example whether the section in a given block is work (working), inoperative (being wiped free of), pollution or temporary transient data at present.Therefore, all data structures in this block must have identical state.Alternatively, section state can maintain in section boundaries.In addition, in certain embodiments, each block can be used an independent status indicator, and is not contained in the index field of data structure of each section.
When write operation, an eraseable memory unit in index field be programmed to upgrade this localizer so far in data field position the line segment of byte wide be wiped free of that, and the line segment of this byte wide be wiped free of that in the specific data storage cell of wiping be programmed to store the reflection logical address of this data byte.
For the purpose of understanding, in following example, this noun " programming " refer to the data value in storage unit is changed to logic " 0 " and operation, and " wipe " and refer to the data value in storage unit is changed to logic " 1 " and operation.With programming and the corresponding data of erase status can be respectively also 1 and 0.In addition,, in multi-level cell memory, programming can be assumed to be a plurality of values.Yet, as described before, this noun " programming " typically refer in flash memory the then operation that storage unit is carried out for basis of a storage unit, and because the cause of flash memory cell configuration; " wipe " refer to the operation of carrying out for basis in a big way in flash memory, in the scope that can effectively carry out in a given array structure.Therefore,, according to the configuration of flash memory cell, programme in certain embodiments and wipe to comprise respectively and reduce and increase threshold voltage.
The size of this data field position must a block or section carry out the frequency of erase operation and the logical address number of the given block of flash memory devices so far of can videoing between accept or reject (will discuss below), and therefore can change depending on the difference of embodiment.
This flash memory devices also can comprise a plurality of inoperative blocks or section, its can be full in the data field position in the current data structure in, as a preparation unit to store every now and then more new data.
Fig. 2 shows the data array in a block, it comprise a plurality of from section 0 section to section M.In an embodiment, section 0 perhaps can be wiped independently to each section of section M.And herein in described example, section cannot be wiped independently, but erase operation is in block border, to carry out the use of usining as the high speed byte access in this array segment.As shown in Figure 1B, data structure is placed in addressable section, and comprises that an index region stores index field and position, storage data territory is come in a data area.
Data structure in section 0 comprises an index field 200-0, and it comprises the so far wide line segment of a specified byte in the 202-0 of data field position of a localizer, and it stores the data byte of counterlogic address.This localizer represents a series of programming and eraseable memory unit in this index field 200-0.
When thering is the write operation of videoing to a byte of the logical address of section 0 data storage cell, the localizer that an obliterated data storage unit in this index field is programmed to upgrade index field 200-0 points to so far the wide line segment of a specified byte in the 202-0 of data field position, it stores the data byte of counterlogic address, and the line segment of this byte wide be wiped free of that in the specific data storage cell of wiping be programmed to store the reflection logical address of this data byte.
In this illustrative example, data storage cell in index field is in order to respond writing order and being programmed with sequence of addresses separately, from first of the data storage cell in the index field of the first write operation, then be the second of the second write operation, until the data storage cell being programmed recently after storage unit still keeps wiping.Similarly, the line segment of the byte wide in data field position is for example that the mode of sequence of addresses writes according to one, from the first byte wide line segment of the first write operation, then be the second byte wide line segment of the second write operation, until the byte wide line segment after being programmed still keeps wiping (or empty) recently.
In alternate embodiment, for the data storage cell of order in index field that write responding separately is sequentially programmed, and the byte wide line segment in data field position also sequentially writes, and both orders can be from different shown in Fig. 2.For example, the final data storage unit starting program that the data storage cell in index region can be in the index field of the first write operation, by that analogy.
By writing new data more to the byte wide line segment being wiped free of in the 202-0 of data field position, rather than utilize an erase operation directly to be covered, being used for upgrading localizer and data storage cell does not need experience to wipe program the data storage cell to index field of the renewal byte of the data that are programmed to store.So can in a programming operation, compare with the number of write operation, only need the block of a decimal or the erase operation of section, and can effectively increase the endurance of flash memory.
Because more new data is the empty sections in position, data writing territory, it is full that this data field position finally can become.Therefore, in block 1 section 0 to the stored data structure of the section of section M otherwise time use the then then mode of a block of section or block of a section, again reflection to block 0 in section 0 in the data structure of the section institute mapping of section M.This noun " frequently " refer to once in a while, and do not need rule or regularly or carry out with the time interval equating.
Except distinguishing by the data that are stored in index field 200-0 status indicator field the state of section work in this block 1 or inoperative, the data in status indicator field be also used to confirm this more new data blocks by layout and be correctly stored in new block.These following Fig. 9 that can arrange in pairs or groups describe in more detail.
Fig. 3 shows the video reflection example of the block with section-0 to section-127 to flash memory devices 120 physical address spaces 320 of a 302-0 to 302-127 of logical address group in logical address space 300.In this illustration, each logical address in logical address space 300 is mapped to the section of 32 bytes of data storage cell in corresponding physical address space 320.Therefore, logical address 0000000 (reference number 302-0) is mapped to section 0304-0, and logical address 0000001 (reference number 302-1) is mapped to section 1304-1, by that analogy.
In this example, the index field that each section of data storage cell comprises one 4 bytes and the data field position of one 32 bytes, and be used for storing the data of 8 (1 bytes) of institute's counterlogic address.Therefore,, in this example, in the data field position of a given section of data storage cell, can become before full and support 32 single byte write operations to institute's counterlogic address in data field position.
Fig. 4 is the data placement in display block 0304-0 more.As shown in Figure 4, the section 0304-0 storage bag of data storage cell is containing the data structure of index field 400 and data field position 410.In this illustration, the data of index field 400 metas 0～27 form a localizer 420 to being used for the wide line segment of a specified byte of stored logic address 0000000 (reference number 302-0) 8 bit data of videoing in data field position 410.The data of the position 28～31 in index field form a status indicator field 430, it indicates a state of this section, the block of take in this example keeps as basic mode, indicates the common state (can describe in more detail below) of all section section-0 to section-127.
As shown in Figure 4, position 0～27 data form a localizer 420 and carry out to be used in position, identification data territory 410 particular section of stored logic address 0000000 (reference number 302-0) 8 bit data of videoing.For example, application for every storage unit, if the data of index field meta 0 are programmed, and the storage unit of all the other all positions 1～27 is wiped free of, this localizer 420 can point to section d0, and it is first section of the sequence of addresses in data field position 410.If the data of index field meta 0～1 are programmed, and the storage unit of all the other all positions 2～27 is wiped free of, and this localizer 420 can point to section d1, and it is second section of the sequence of addresses in data field position 410.Also can come arranging data to think which particular section of localizer 420 identifications can be used by technology alternatively.In addition,, in the embodiment of multiple position storage unit, a data storage cell can store two positions or above localizer.
The schematic diagram of translating between Fig. 5 display entity address space and logical address space.Logical address is to use an address translation table 520 to be mapped to corresponding block.For a specific logical address, these address translation tables 520 identifications therewith block and the section of data storage cell corresponding to logical address provide the block that corresponds to logical address.Then the localizer of index field that is stored in the data structure of corresponding data storage unit is read with identification and stores the section in the data field position of this logical address data.
The demand with regard to necessary scheduler translation tables 520 has been got rid of after the each more new data of flash memory devices 120 or the work section when this block in are changed in the use of localizer, and correct tracking that can activation valid data.Because address translation table 520 does not need to upgrade constantly, it can be stored in flash memory devices 120.When operation, address translation table 520 can be extracted in the storer of higher access speed, for example the DRAM of Fig. 1 processor or SRAM.
Fig. 6 is a process flow diagram by the performed write operation 600 of processor 114 according to an embodiment of the invention, and it is storage data byte or other N bit data section to specific logic address.Process flow diagram as shown here, should be appreciated that many steps can be combined, carry out abreast or carry out and can not affect the effect being wanted to reach with different orders, in some cases, only rearranging of different step can just can be reached identical effect adjusting in the lump some step, and in some cases, only rearranging of different step can be satisfied just and can reach identical effect in some condition.So rearrange and will be apparent to those skilled in the art.
In order to respond the order that writes of storage data byte to specific logic address, in step 610, the address translation table of discussing before using decides corresponding so far block or the section of the data storage cell of specific logic address.
In step 615, then the localizer of index field that is stored in the data structure of corresponding data storage unit is read to determine to store wipes section to store this data byte in this data field position.
In step 620, if not comprising, this data field position do not wipe section, this data field position is full.As in the case, this operation 600 proceeds to square 630, the more new data structure that wherein section stores this data structure is for this reason by layout.This editing operation meeting illustrates at following collocation Fig. 9.
If this data field position comprises, wipe section, this operation 600 proceeds to square 640.In step 640, the obliterated data storage unit in index field is programmed to upgrade this localizer and is so far wiped free of section, and this more new data be written into this and be wiped free of section.Then this operation 600 stops at step 650.
Fig. 7 is shown in the programme example of obliterated data storage unit in this index field of when operation.As shown in Figure 7, position 0～27 is used for storing localizer, and position 28～31 is used for storing a status indicator field, and it indicates a state (can describe in more detail below) of this section or block.In this example, in this block, to be configured to indicate section be work to the status indicator of each section, and its all positions are programmed to " 00000 ".
As shown in Figure 7, in order to respond one first write operation, this localizer upgrades by storage unit to the logical zero of program bit 1, when the second write operation, the storage unit of program bit 2 is to logical zero, by that analogy until all 28 positions in this localizer field are all programmed to logical zero.In this programming process, do not need to carry out erase operation.Although the given byte in this localizer field is accessed repeatedly in programming process, if but because do not have storage unit to need self-programming to change to the words of erase status in this byte, one programming process is to carry out that byte reads or other similar step is wiped in advance preventing, so do not need to carry out erase operation.
In alternate embodiment, can be with the data storage cell of programming in index field with the different order shown in Fig. 7.For example, in order to respond the first write operation, the order starting program of the last position 27 that the data storage cell in index region can be in the data storage cell of localizer, by that analogy.
Fig. 8 is a process flow diagram by the performed read operation 800 of processor 114 according to an embodiment of the invention, and it is the data that read specific logic address.
In order to respond a reading order that reads these specific logic address data, in step 810, the address translation table of discussing before using decides corresponding so far block or the section of the data storage cell of specific logic address.
In step 820, the localizer of index field that is stored in the data structure of corresponding data storage unit is read to determine to store (finally) work section in the data field position of this logical address data.Then the data that are stored in this work section are read and export in step 830.
As what discussed before, one of this block of layout new data set more frequently, and to write to one be previously the block of inoperative.
Fig. 9 is a process flow diagram by the performed editing operation 900 of processor 114 according to an embodiment of the invention.This operation 900 can be in data storage cell one section of a given block the data field position of data structure while becoming full or other is activated any time.
For more clearly for the purpose of the following discussion explanation, the work block before operation 900 starts is called " block A ", and inoperative block before operation 900 starts is called " block B ".The block using in this program can be the minimum storage unit group being wiped free of during to the erase operation of flash memory used.The section distributing in each block and the number of data structure can be to any number that is applicable to a default use pattern from 1.
In step 910, be stored in data in active section in block A data field position and be read and think and video to the logical address group layout one of block A new data set more.This more new data set comprise the valid data of videoing to the logical address group of block A.
In step 920, this more new data set write in the data field position of block B section.In step 930, address translation table is updated Yi Jiang logical address group and again videos to block B.In step 940, block A is wiped free of.In certain embodiments, the block A erase operation in step 940 can't carry out at once after the reflection again of step 930, but just carries out when the resource that is for example processor 114 is not carried out other operation.
As described above, the data in status indicator field be used to guarantee this more new data set by layout and correctly to exist be previously in the block of inoperative.
Figure 10 is a process flow diagram by the performed conversion operations 1000 of processor 114 according to an embodiment of the invention.It is when the editing operation 900 of Fig. 9, to change the data in the status indicator field that is stored in block A and all data structures of block B.
As shown in Figure 10, the position that is used for storing the data storage cell in work block A condition identification field when editing operation 900 starts is in a programming state (0000), and the position that is used for storing the data storage cell in inoperative block B status indicator field is in an erase status (1111).
When block, B is selected, and before more new data set is written into the data field position of block B, in step 1010 block B section the data storage cell of all 28 positions be programmed with by the data in block B status indicator field from " 1111 " change to " 0111 ".By mode like this just the data in block B status indicator field change, before more new data set is written into block B, the data in this status indicator field can be with determining whether that occurring is for example the interrupt event that power supply disappears.
Afterwards, the data in step 1020 block A data structure are written in the initialization data structure of block B.Afterwards in step 1030, whether this program determines that this writes and completes.After in the data field position that new data set is more write to block B (step 1020 and 1030), the data storage cell of step 1040 block B status indicator field meta 29 be programmed with by the data in block B status indicator field from " 0111 " change to " 0011 ".Data in status indicator field are used to guarantee the more new data set that comprises logical address group in block B.Afterwards, can carry out safely the data structure erase operation of block A, and this logical address of again videoing.When this program of wiping starts, can be to carry out or carry out when processor has available resource at once, the data in the status indicator field of step 1041 block B section are updated to " 0001 ".Afterwards, the erase operation of block A can start in step 1050, and this program waits until step 1060 completes wipes.
Because the status indicator field of block A is within block, the data of the erase operation (step 1050 to 1060) of this block A in also can erase status identification field, it can change to " 1111 " (inoperative) by the data in block A condition identification field.After the erase operation of this block A, the data storage cell of step 1070 block B status indicator field meta 31 be programmed with by the data in the status indicator field of block B section from " 0001 " change to " 0000 " (work).
In the process flow diagram of this conversion operations 1000, by block B status indicator field from " 1111 " conversion of (inoperative) to " 0000 " (work) involves the programming that has been wiped free of storage unit in this status indicator field.This technology has been eliminated the demand of just necessary obliterated data storage unit in the time at every turn need to changing status indicator field.Consequently, the data of status indicator field can be stored in block B, and do not need to store dividually.
In alternate embodiment, what the position that must be programmed while changing the data of status indicator field can be from shown in Figure 10 is different.
As viewed above, in certain embodiments, the block A erase operation in step 1050 does not need to carry out at once, but just carries out when the resource that is for example processor 114 is not carried out other operation.
Figure 11 shows according to the interclass graph of a relation of different software in one embodiment of the invention flash memory devices 120.User's program code 1130 comprises that logic is to provide logical address and order to read and data writing flash memory devices 120 so far.
These intelligent quick flashing application programming interfaces (API) 1120 are that a software module comprises that logic is to carry out logic-physical address reflection and to translate, and the data that logic read and write flash memory devices 120 so far with management are to carry out different operating described herein.These intelligent quick flashing application programming interfaces (API) 1120 are translated order and are provided instruction to low order quick flashing application programming interfaces (API) 1110 from user's program code 1130.These intelligent quick flashing application programming interfaces (API) 1120 are also used address translation table that the logical address of user's program code 1130 is translated into corresponding physical address, and then it offer low order quick flashing application programming interfaces (API) 1110 software modules.
These low order quick flashing application programming interfaces (API) 1110 are that a software driver is specially adapted to and flash memory devices 120 collocation work.These low order quick flashing application programming interfaces (API) 1110 comprise logic with carry out actual read with programming data and section erase so far flash memory devices 120 with response by intelligent quick flashing application programming interfaces (API) 1120 instruction being provided and physical address.
This flash memory devices 120, low order quick flashing application programming interfaces (API) 1110 and intelligent quick flashing application programming interfaces (API) 1120 are with the then read-write of the common emulation flash memory devices 120 of mode of a byte of a byte described herein.
This flash memory devices 120 can be implemented with commercial conventional flash memory devices, for example the MX25L512CMOS serial quick flashing of Wang Hong company.Consequently, the mode that these intelligent quick flashing application programming interfaces (API) 1120 provide a simulation byte described herein to follow a byte is carried out the ability of the read-write of flash memory devices 120, and must first not carry out the block action of erasing before not needing again to write these devices.
In Figure 11, these intelligent quick flashing application programming interfaces (API) the 1120th, are arranged between user's program code 1130 and low order quick flashing application programming interfaces (API) 1110.
Figure 12 shows according to the present invention the interclass graph of a relation of different software in one second embodiment flash memory devices 120, and wherein flash memory devices 120 comprises a byte read-write mode region 1200 and a flash memory devices accessing zone 1210.
In Figure 12, the reading and writing data of the mode of a byte is followed in the byte read-write mode region 1200 in these intelligent quick flashing application programming interfaces (API) 1120 operating flash memory storages 120 with an emulation byte described herein.In addition, these low order quick flashing application programming interfaces (API) 1110 operating flash storage access mode region 1210 with a byte then a byte or a page then the mode of a page flash memory devices 120 is carried out to data read or programme, and with a block then the mode of a block flash memory devices 120 is wiped.
In embodiment so, flash memory devices 120 can be simultaneously as electrically programmable erasable read-only memory (EEPROM) and a flash memory.Consequently, flash memory devices 120 can replace minute other electrically programmable erasable read-only memory (EEPROM) and flash memory, and it has reduced system cost and complicacy.
Technology described herein can activation be used block for basic flash memory is among the disposal system of greater number information.As an example, the read-write that technology described herein can the single byte data of emulation.More generally, it is other size data in basic flash memory that technology described herein can be used for reading and writing use block, and wherein the size of data of read-write is the size that is less than block.
The advantage of technology described herein comprises by take block as basic flash memory replacement expensive low-density electrically programmable erasable read-only memory (EEPROM), can save the cost of system.By implementing technology described herein, the read/write life-span of this flash memory can be increased 1000 times into surpassing traditional block access algorithm.
Although the present invention is described with reference to embodiment, so the present invention's creation is not limited to its detailed description.Substitute mode and revise pattern and advise in previous description, and other substitute mode and modification pattern will be thought by those skilled in the art and.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the identical result person in fact with the present invention, neither disengaging spiritual category of the present invention.Therefore, all these substitute modes and revise pattern system and be intended to drop among the category that the present invention defines in enclose claim scope and equipollent thereof.
Claims (22)
1. operate a method for a flash memory, comprise:
Arrange to have in this flash memory a plurality of sections of data storage cell of sector address to store data structure separately; arrange a data structure of one of the plurality of section with the N position of storage data, and this data structure comprise an index field and a data field position;
By wiping this index field and this data structure of initialization is carried out in this data field position; Wherein this data structure also comprises a state position, and this initialization comprises and wipe this state position, and wherein this state position comprises at least K-1 position, and when this data structure of initialization, indicates K current one of carrying out state;
By storing a data storage cell of corresponding with a specific N bit line segment in this data field position in this index field of programming; write the N position of these data with a logical address, and in this data field position of this data structure of programming a specific N bit line segment to store the N position of these data; And
In this index field by this data structure of programming, have the another one corresponding with another different N bit line segment in this data field position, the N that again writes the data with this same logical address is arranged in this data structure, and this different N bit line segment of programming.
2. method according to claim 1, more comprises:
This logical address of the N position of these data of videoing is to the sector address of the plurality of section of data storage cell.
3. method according to claim 1, the N position of wherein reading these data in this data structure by the N bit line segment reading in this data field position of being distinguished by this index field.
4. method according to claim 1, wherein this index field comprises a localizer field and sequentially stores M position, and this data field position comprises sequentially M the N bit line segment of arranging, wherein in this localizer field, last of M position has been programmed the one of the nearest use of this M N bit line segment corresponding in this data field position.
5. method according to claim 1, wherein this index field comprises a localizer field and sequentially stores M position, and this data field position comprises M the N bit line segment of sequentially arranging, wherein when this stores that a primary data storage cell is programmed and remaining data storage cell still keeps wiping in this localizer field, this localizer field is pointed to the one of the sequence of addresses of this N bit line segment, when this stores this first and when deputy one or more data storage cell is programmed and remaining data storage cell still keeps wiping in this localizer field, this localizer field point to this N bit line segment sequence of addresses the two, and when all these M positions in this localizer field are all programmed, this localizer field is pointed to the last one of the sequence of addresses of this N bit line segment.
6. method according to claim 1, wherein this data field position comprises M N bit line segment, comprising:
By wiping an index field and a data field position, carry out another data structure in the plurality of section of initialization data storage unit, this another data structure comprises this index field and this data field position;
When position, the M in this data structure N bit data territory is about to experience write operation, by the data storage cell in this index field of programming this other data structure corresponding with a specific N bit line segment in this data field position of other data structure, the N that writes these data with this same logical address is arranged in this other data structure, and in this data field position of this other data structure of programming this specific N bit line segment to store the N position of these data.
7. method according to claim 1, wherein this data structure comprises a state position, and this initialization comprises wipes this state position, wherein this state position comprises at least K-1 position, and when this data structure of initialization, indicate K current one of carrying out state, comprise an original state wherein in this state position all data storage cells be all wiped free of, one first state that wherein this K carries out state is programmed and when remaining data storage cell of this state position is wiped free of for the primary data storage cell when this state position of storage, and one second state that this K carries out state is programmed and when remaining data storage cell of this state position is wiped free of for this first and one deputy one or more data storage cell when this state position of storage, and when all these K-1 the positions that the individual final state that carries out state of this K is this state position are all programmed.
8. method according to claim 7, wherein this original state is initialised and there is no logical address reflection to this data structure, this second state is videoed for this data structure is selected, when one third state completes for writing N bit data from source data structure or other source, one the 4th state is wiped this source data structure for starting (if some words), and this final state is for completing and wipe when logical address is videoed to data structure this source data structure when any.
9. method according to claim 1, comprise and distribute first and second block, each block comprises L section, in L logical address of this flash memory, and wherein in this data structure of particular section initialization, comprise the one of this first and second block of wiping this L section that comprises this particular section.
10. method according to claim 1, comprises and distributes first and second block, and each block comprises L section, and in L logical address of this flash memory, and wherein this data field position in this data structure of this section comprises M N position section, comprising:
By wiping this second block, the data structure in this second block of initialization, and comprise:
When the position, M N bit data territory in this data structure in this first block is about to experience write operation, stored data in this first block are moved to the data structure in this second block.
11. 1 kinds of devices, comprise:
One storage array, a plurality of sections that comprise the data storage cell with sector address;
Storage data structure is in to store the logic in a plurality of sections of this data storage cell, and this data structure arranges the N position of storage data, in the data structure of one of the plurality of section, comprises an index field and a data field position;
By wiping this index field and this data field position, carry out the logic of this data structure of initialization; Wherein this data structure comprises a state position, and this initialization comprises and wipe this state position, and wherein this state position comprises at least K-1 position, and when this data structure of initialization, indicates K current one of carrying out state;
By storing a data storage cell of corresponding with a specific N bit line segment in this data field position in this index field of programming, write the N position of these data with a logical address, and in this data field position of this data structure of programming, a specific N bit line segment is to store the N position of these data, and in this index field by this data structure of programming, there is an another one corresponding with another different N bit line segment in this data field position, the N that again writes the data with this same logical address is arranged in this data structure, and the logic of this different N bit line segment of programming.
12. devices according to claim 11, wherein at least a portion of the logic of this storage, this initialized logic and this logic writing comprises a processor and is stored in the instruction that can be carried out by this processor in this storage array.
13. devices according to claim 11, more comprise:
Storer, store a logical address mapping table with this logical address of the N position of these data of videoing the group address to the plurality of section of this data storage cell.
14. devices according to claim 11, comprise that the N bit line segment by reading in this data field position of being distinguished by this index field reads the logic of the N position of these data in this data structure.
15. devices according to claim 11, wherein this index field comprises a localizer field and sequentially stores M position, and this data field position comprises sequentially M the N bit line segment of arranging, wherein in this localizer field, last of M position has been programmed the one of the nearest use of this M N bit line segment corresponding in this data field position.
16. devices according to claim 11, wherein this index field comprises a localizer field and sequentially stores M position, and this data field position comprises M the N bit line segment of sequentially arranging, wherein when this stores that a primary data storage cell is programmed and remaining data storage cell still keeps wiping in this localizer field, this localizer field is pointed to the one of the sequence of addresses of this N bit line segment, when this stores this first and when deputy one or more data storage cell is programmed and remaining data storage cell still keeps wiping in this localizer field, this localizer field point to this N bit line segment sequence of addresses the two, and when all these M positions in this localizer field are all programmed, this localizer field is pointed to the last one of the sequence of addresses of this N bit line segment.
17. devices according to claim 11, wherein this data field position comprises M N bit line segment, comprising:
By wiping this index field and a data field position, carry out the logic of another data structure of the plurality of section of initialization data storage unit, this another data structure comprises this index field and this data field position, and comprises:
When in this data structure, position, M N bit data territory is about to experience write operation, by the data storage cell in this index field of programming this other data structure corresponding with a specific N bit line segment in this data field position of other data structure, the N that writes these data with this same logical address is arranged in this other data structure, and in this data field position of this other data structure of programming this specific N bit line segment to store the logic of the N position of these data.
18. devices according to claim 11, wherein this data structure comprises a state position, and this initialization comprises wipes this state position, wherein this state position comprises at least K-1 position, and when this data structure of initialization, indicate K current one of carrying out state, comprise an original state wherein in this state position all data storage cells be all wiped free of, one first state that wherein this K carries out state is programmed and when remaining data storage cell of this state position is wiped free of for the primary data storage cell when this state position of storage, and one second state that this K carries out state is programmed and when remaining data storage cell of this state position is wiped free of for this first and one deputy one or more data storage cell when this state position of storage, and when all these K-1 the positions that the individual final state that carries out state of this K is this state position are all programmed.
19. devices according to claim 18, wherein this original state is initialised and there is no logical address reflection to this data structure, this second state is videoed for this data structure is selected, when one third state completes for writing N bit data from source data structure or other source, one the 4th state is wiped this source data structure for starting (if some words), and this final state is for completing and wipe when logical address is videoed to data structure this source data structure when any.
20. devices according to claim 11, comprise the logic of distributing first and second block, each block comprises L section, in L logical address of this storage array, and wherein in this data structure of particular section initialization, comprise the one of this first and second block of wiping this L section that comprises this particular section.
21. devices according to claim 11, comprise the logic of distributing first and second block, each block comprises L section, in L logical address of this storage array, and wherein this data field position in this data structure of this section comprises M N position section, comprising:
By wiping this second block, the logic of the data structure in this second block of initialization, and comprise:
When position, M N bit data territory is about to experience write operation in this data structure in this first block, stored data in this first block are moved to the logic of the data structure in this second block.
22. 1 kinds of machine-readable data storage devices, comprise:
One machine-readable data storing media, comprise for storing the module of the instruction that can be carried out by processor, this processor has the function of access one storage array, a plurality of sections that this storage array comprises the data storage cell with sector address, should comprise for storing the module of the instruction that can be carried out by processor:
For storage data structure, in to store the module of logic of a plurality of sections of this data storage cell, this data structure arranges the N position of storage data, in the data structure of one of the plurality of section, comprises an index field and a data field position;
For carry out the module of the logic of this data structure of initialization by wiping this index field and this data field position; And
For store the module with the data storage cell of that in this data field position, a specific N position section is corresponding by this index field of programming, this module is also for writing the N position of these data with a logical address, and in this data field position of this data structure of programming, a specific N position section is to store the N position of these data, and in this index field by this data structure of programming, there is an another one corresponding with another different N bit line segment in this data field position, the N that again writes the data with this same logical address is arranged in this data structure, and this different N bit line segment of programming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010224441.1A CN102314396B (en) | 2010-07-06 | 2010-07-06 | Method and device for accessing bytes by taking a block as base flash |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010224441.1A CN102314396B (en) | 2010-07-06 | 2010-07-06 | Method and device for accessing bytes by taking a block as base flash |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102314396A CN102314396A (en) | 2012-01-11 |
| CN102314396B true CN102314396B (en) | 2014-01-29 |
Family
ID=45427581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010224441.1A Active CN102314396B (en) | 2010-07-06 | 2010-07-06 | Method and device for accessing bytes by taking a block as base flash |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102314396B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI691895B (en) * | 2018-12-28 | 2020-04-21 | 新唐科技股份有限公司 | Data-programming methods, programming systems, data update methods, and storage devices |
| US20210035644A1 (en) * | 2019-08-01 | 2021-02-04 | Macronix International Co., Ltd. | Memory apparatus and data access method for memory |
| CN114115700A (en) * | 2020-08-31 | 2022-03-01 | 施耐德电气（中国）有限公司 | Flash memory data read-write method and flash memory data read-write device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5845313A (en) * | 1995-07-31 | 1998-12-01 | Lexar | Direct logical block addressing flash memory mass storage architecture |
| CN1770328A (en) * | 2004-09-30 | 2006-05-10 | 株式会社东芝 | Nonvolatile semiconductor memory device and data erasing method thereof |
| CN101123120A (en) * | 2007-09-06 | 2008-02-13 | 复旦大学 | Once programming memory and its operation method using resistor memory media |
| CN101335048A (en) * | 2007-06-29 | 2008-12-31 | 旺宏电子股份有限公司 | Double programming methods of a multi-level-cell nonvolatile memory |
| CN101364205A (en) * | 2005-06-01 | 2009-02-11 | 旺玖科技股份有限公司 | Flash memory system |
| CN101727987A (en) * | 2008-10-29 | 2010-06-09 | 旺宏电子股份有限公司 | Data programming and reading method and single time programmable memory applying the same |
| CN101740126A (en) * | 2008-11-13 | 2010-06-16 | 旺宏电子股份有限公司 | Memory and method applied in one program command for the memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7085879B2 (en) * | 2002-02-27 | 2006-08-01 | Microsoft Corporation | Dynamic data structures for tracking data stored in a flash memory device |
| JP2006285600A (en) * | 2005-03-31 | 2006-10-19 | Tokyo Electron Device Ltd | Storage, memory management device, memory management method, and program |
| WO2007058617A1 (en) * | 2005-11-17 | 2007-05-24 | Chee Keng Chang | A controller for non-volatile memories, and methods of operating the memory controller |
-
2010
- 2010-07-06 CN CN201010224441.1A patent/CN102314396B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5845313A (en) * | 1995-07-31 | 1998-12-01 | Lexar | Direct logical block addressing flash memory mass storage architecture |
| CN1770328A (en) * | 2004-09-30 | 2006-05-10 | 株式会社东芝 | Nonvolatile semiconductor memory device and data erasing method thereof |
| CN101364205A (en) * | 2005-06-01 | 2009-02-11 | 旺玖科技股份有限公司 | Flash memory system |
| CN101335048A (en) * | 2007-06-29 | 2008-12-31 | 旺宏电子股份有限公司 | Double programming methods of a multi-level-cell nonvolatile memory |
| CN101123120A (en) * | 2007-09-06 | 2008-02-13 | 复旦大学 | Once programming memory and its operation method using resistor memory media |
| CN101727987A (en) * | 2008-10-29 | 2010-06-09 | 旺宏电子股份有限公司 | Data programming and reading method and single time programmable memory applying the same |
| CN101740126A (en) * | 2008-11-13 | 2010-06-16 | 旺宏电子股份有限公司 | Memory and method applied in one program command for the memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102314396A (en) | 2012-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101923516B (en) | Block-based flash memory and its operation method | |
| US8386698B2 (en) | Data accessing method for flash memory and storage system and controller using the same | |
| US8055873B2 (en) | Data writing method for flash memory, and controller and system using the same | |
| CN101937319B (en) | Memory systems and mapping methods thereof | |
| TWI454906B (en) | Data read method, and flash memory controller and storage system using the same | |
| CN102317925B (en) | Memory system and method of controlling memory system | |
| US8001317B2 (en) | Data writing method for non-volatile memory and controller using the same | |
| US8239619B2 (en) | Method and apparatus for high-speed byte-access in block-based flash memory | |
| WO2009096180A1 (en) | Memory controller, nonvolatile storage device, and nonvolatile storage system | |
| CN101535963A (en) | Flash memory with programmable endurance | |
| US20090150597A1 (en) | Data writing method for flash memory and controller using the same | |
| CN101213510A (en) | Method and system for managing partitions in a storage device | |
| CN101494086B (en) | Memory device, controller and switching method for flash memory | |
| CN101494085B (en) | Prevent nonvolatile memory from method and the controller thereof of interference occurring to read | |
| US9037814B2 (en) | Flash memory management method and flash memory controller and storage system using the same | |
| WO2014074449A2 (en) | Wear leveling in flash memory devices with trim commands | |
| US20100042775A1 (en) | Block management method for flash memory, and storage system and controller using the same | |
| CN102157202A (en) | Method and controller for preventing nonvolatile memory from occurring read interference | |
| US8914587B2 (en) | Multi-threaded memory operation using block write interruption after a number or threshold of pages have been written in order to service another request | |
| CN104239096A (en) | Method and unit for realizing security data partitions in Android system | |
| CN101425338B (en) | Writing method for nonvolatile memory and controller using the method | |
| CN101866320B (en) | Data management method and flash memory storage system and controller using the same | |
| CN102968385B (en) | Method for writing data, Memory Controller and storage device | |
| CN117043753A (en) | Different write priorities in ZNS devices | |
| CN102314396B (en) | Method and device for accessing bytes by taking a block as base flash |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |